tree 547ce59ef61817fc02fb7ba134cf4738814f3da8
parent 0cb2bb1af5f16aec57a5266ba1d62379972d58d4
author Nishanth Menon <nm@ti.com> 1607660278 -0600
committer Nishanth Menon <nm@ti.com> 1608726985 -0600

ti: k3: Move USE_COHERENT_MEM only for the generic board

commit 65f7b81728d0 ("ti: k3: common: Use coherent memory for shared data")
introduced WARMBOOT_ENABLE_DCACHE_EARLY and USE_COHERENT_MEM to handle
multiple clusters across L3 cache systems. This is represented by
"generic" board in k3 platform.

On "lite" platforms, however, system level coherency is lacking since
we don't have a global monitor or an L3 cache controller. Though, at
a cluster level, ARM CPU level coherency is very much possible since
the max number of clusters permitted in lite platform configuration is
"1".

However, we need to be able to disable USE_COHERENT_MEM for the lite
configuration due to the lack of system level coherency.

See docs/getting_started/build-options.rst for further information.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4a0ec150b3f9ea12369254aef834a6cbe82d6be6