Merge "GIC-600: Fix MISRA-2012 defects" into integration
diff --git a/drivers/arm/gic/v3/gic-x00.c b/drivers/arm/gic/v3/gic-x00.c
index c9e9cb9..6e106ba 100644
--- a/drivers/arm/gic/v3/gic-x00.c
+++ b/drivers/arm/gic/v3/gic-x00.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -21,10 +21,10 @@
#include "gicv3_private.h"
/* GIC-600 specific register offsets */
-#define GICR_PWRR 0x24
-#define IIDR_MODEL_ARM_GIC_600 (0x0200043b)
-#define IIDR_MODEL_ARM_GIC_600AE (0x0300043b)
-#define IIDR_MODEL_ARM_GIC_CLAYTON (0x0400043b)
+#define GICR_PWRR 0x24U
+#define IIDR_MODEL_ARM_GIC_600 U(0x0200043b)
+#define IIDR_MODEL_ARM_GIC_600AE U(0x0300043b)
+#define IIDR_MODEL_ARM_GIC_CLAYTON U(0x0400043b)
/* GICR_PWRR fields */
#define PWRR_RDPD_SHIFT 0
@@ -32,17 +32,17 @@
#define PWRR_RDGPD_SHIFT 2
#define PWRR_RDGPO_SHIFT 3
-#define PWRR_RDPD (1 << PWRR_RDPD_SHIFT)
-#define PWRR_RDAG (1 << PWRR_RDAG_SHIFT)
-#define PWRR_RDGPD (1 << PWRR_RDGPD_SHIFT)
-#define PWRR_RDGPO (1 << PWRR_RDGPO_SHIFT)
+#define PWRR_RDPD (1U << PWRR_RDPD_SHIFT)
+#define PWRR_RDAG (1U << PWRR_RDAG_SHIFT)
+#define PWRR_RDGPD (1U << PWRR_RDGPD_SHIFT)
+#define PWRR_RDGPO (1U << PWRR_RDGPO_SHIFT)
/*
* Values to write to GICR_PWRR register to power redistributor
* for operating through the core (GICR_PWRR.RDAG = 0)
*/
-#define PWRR_ON (0 << PWRR_RDPD_SHIFT)
-#define PWRR_OFF (1 << PWRR_RDPD_SHIFT)
+#define PWRR_ON (0U << PWRR_RDPD_SHIFT)
+#define PWRR_OFF (1U << PWRR_RDPD_SHIFT)
#if GICV3_SUPPORT_GIC600
@@ -59,10 +59,14 @@
static void gicr_wait_group_not_in_transit(uintptr_t base)
{
+ uint32_t pwrr;
+
+ do {
+ pwrr = gicr_read_pwrr(base);
+
/* Check group not transitioning: RDGPD == RDGPO */
- while (((gicr_read_pwrr(base) & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) !=
- ((gicr_read_pwrr(base) & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT))
- ;
+ } while (((pwrr & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) !=
+ ((pwrr & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT));
}
static void gic600_pwr_on(uintptr_t base)
@@ -94,7 +98,7 @@
* In that case, wait as long as it's in transition, or has aborted
* the transition altogether for any reason.
*/
- if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0) {
+ if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0U) {
/* Wait until group not transitioning */
gicr_wait_group_not_in_transit(base);
}
@@ -104,12 +108,12 @@
{
uintptr_t gicr_base;
- assert(gicv3_driver_data);
+ assert(gicv3_driver_data != NULL);
assert(proc_num < gicv3_driver_data->rdistif_num);
- assert(gicv3_driver_data->rdistif_base_addrs);
+ assert(gicv3_driver_data->rdistif_base_addrs != NULL);
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
- assert(gicr_base);
+ assert(gicr_base != 0UL);
return gicr_base;
}
@@ -127,7 +131,7 @@
((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_CLAYTON));
}
-#endif
+#endif /* GICV3_SUPPORT_GIC600 */
void gicv3_distif_pre_save(unsigned int proc_num)
{
@@ -139,7 +143,6 @@
arm_gicv3_distif_post_restore(proc_num);
}
-
/*
* Power off GIC-600 redistributor (if configured and detected)
*/
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index 97b75b0..18d5b73 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -223,10 +223,10 @@
#define TYPER_PPI_NUM_MASK U(0x1f)
/* GICR_IIDR bit definitions */
-#define IIDR_PRODUCT_ID_MASK 0xff000000
-#define IIDR_VARIANT_MASK 0x000f0000
-#define IIDR_REVISION_MASK 0x0000f000
-#define IIDR_IMPLEMENTER_MASK 0x00000fff
+#define IIDR_PRODUCT_ID_MASK U(0xff000000)
+#define IIDR_VARIANT_MASK U(0x000f0000)
+#define IIDR_REVISION_MASK U(0x0000f000)
+#define IIDR_IMPLEMENTER_MASK U(0x00000fff)
#define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \
IIDR_IMPLEMENTER_MASK)