Tegra: memctrl_v2: allow CPU accesses to TZRAM
This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.
Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: Steven Kao <skao@nvidia.com>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index bd601e4..e120314 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -199,13 +199,22 @@
* Reset the access configuration registers to restrict access
* to the TZRAM aperture
*/
- for (index = MC_TZRAM_CLIENT_ACCESS_CFG0;
+ for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
index += 4U) {
tegra_mc_write_32(index, 0);
}
/*
+ * Enable CPU access configuration registers to access the TZRAM aperture
+ */
+ if (!tegra_chipid_is_t186()) {
+ val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
+ val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
+ tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
+ }
+
+ /*
* Set the TZRAM base. TZRAM base must be 4k aligned, at least.
*/
assert((phys_base & (uint64_t)0xFFF) == 0U);
@@ -232,6 +241,9 @@
val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
+ if (!tegra_chipid_is_t186()) {
+ val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
+ }
tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
/*