Merge changes from topic "hf_transfer_list" into integration
* changes:
fix(tlc): pass the flags from client interface
fix(tlc): relax entry addition from YAML files
feat(tlc): add --align argument
fix(tlc): add void entries to align data
fix(handoff): correct 8-bit modulo csum calculation
feat(tlc): formalise random generation of TEs
diff --git a/Makefile b/Makefile
index 384c1e4..6e0e584 100644
--- a/Makefile
+++ b/Makefile
@@ -882,6 +882,10 @@
CRYPTO_SUPPORT := 0
endif #($(MEASURED_BOOT)-$(TRUSTED_BOARD_BOOT))
+ifneq ($(filter 1 2 3,$(CRYPTO_SUPPORT)),)
+CRYPTO_LIB := $(BUILD_PLAT)/lib/libmbedtls.a
+endif
+
# SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled.
ifeq ($(SDEI_SUPPORT)-$(SDEI_IN_FCONF),0-1)
$(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled")
@@ -951,8 +955,21 @@
ifeq (${ENABLE_FEAT_RNG_TRAP},1)
$(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32")
endif
+
+ ifneq (${ENABLE_FEAT_FPMR},0)
+ $(error "ENABLE_FEAT_FPMR cannot be used with ARCH=aarch32")
+ endif
endif #(ARCH=aarch32)
+ifneq (${ENABLE_FEAT_FPMR},0)
+ ifeq (${ENABLE_FEAT_FGT},0)
+ $(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_FGT")
+ endif
+ ifeq (${ENABLE_FEAT_HCX},0)
+ $(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_HCX")
+ endif
+endif #(ENABLE_FEAT_FPMR)
+
ifneq (${ENABLE_SME_FOR_NS},0)
ifeq (${ENABLE_SVE_FOR_NS},0)
$(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
@@ -1264,6 +1281,7 @@
ENABLE_FEAT_ECV \
ENABLE_FEAT_FGT \
ENABLE_FEAT_FGT2 \
+ ENABLE_FEAT_FPMR \
ENABLE_FEAT_HCX \
ENABLE_FEAT_LS64_ACCDATA \
ENABLE_FEAT_MTE2 \
@@ -1425,6 +1443,7 @@
ENABLE_MPMM_FCONF \
ENABLE_FEAT_FGT \
ENABLE_FEAT_FGT2 \
+ ENABLE_FEAT_FPMR \
ENABLE_FEAT_ECV \
ENABLE_FEAT_AMUv1p1 \
ENABLE_FEAT_SEL2 \
@@ -1741,8 +1760,8 @@
$(q)set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
endif #(UNIX_MK)
-$(BUILD_PLAT)/romlib/romlib.bin $(BUILD_PLAT)/lib/libwrappers.a $&: $(BUILD_PLAT)/lib/libmbedtls.a $(BUILD_PLAT)/lib/libfdt.a $(BUILD_PLAT)/lib/libc.a
- $(q)${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
+$(BUILD_PLAT)/romlib/romlib.bin $(BUILD_PLAT)/lib/libwrappers.a $&: $(BUILD_PLAT)/lib/libfdt.a $(BUILD_PLAT)/lib/libc.a $(CRYPTO_LIB)
+ $(q)${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} CRYPTO_SUPPORT=${CRYPTO_SUPPORT} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
memmap: all
ifdef UNIX_MK
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 336ad2b..2f9dc65 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -150,6 +150,10 @@
BL31_SOURCES += lib/extensions/trf/aarch64/trf.c
endif
+ifneq (${ENABLE_FEAT_FPMR},0)
+BL31_SOURCES += lib/extensions/fpmr/fpmr.c
+endif
+
ifeq (${WORKAROUND_CVE_2017_5715},1)
BL31_SOURCES += lib/cpus/aarch64/wa_cve_2017_5715_bpiall.S \
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 8c03ab8..0f6be9f 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -280,6 +280,12 @@
ID_AA64MMFR3_EL1_D128_MASK);
}
+static unsigned int read_feat_fpmr_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT,
+ ID_AA64PFR2_EL1_FPMR_MASK);
+}
+
/***********************************************************************************
* TF-A supports many Arm architectural features starting from arch version
* (8.0 till 8.7+). These features are mostly enabled through build flags. This
@@ -405,6 +411,8 @@
"SME", 1, 2);
check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
"SME2", 2, 2);
+ check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(),
+ "FPMR", 1, 1);
/* v9.3 features */
check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index fda43dc..f1cb73b 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -843,6 +843,9 @@
- ``ERRATA_X4_2897503``: This applies errata 2897503 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+- ``ERRATA_X4_2923985``: This applies errata 2923985 workaround to Cortex-X4
+ CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
+
- ``ERRATA_X4_3076789``: This applies errata 3076789 workaround to Cortex-X4
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 7d067c6..bd11d68 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -351,6 +351,12 @@
This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
+- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point
+ Mode Register feature, allowing access to the FPMR register. FPMR register
+ controls the behaviors of FP8 instructions. It is an optional architectural
+ feature from v9.2 and upwards. This flag can take value of 0 to 2, to align
+ with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``.
+
- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps)
feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
Read Trap Register) during EL2 to EL3 context save/restore operations.
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index c414b1f..32c2b39 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -31,7 +31,7 @@
Clang/LLVM 18.1.8
Device Tree Compiler 1.6.1
GNU make 3.81
-mbed TLS\ [#f1]_ 3.6.1
+mbed TLS\ [#f1]_ 3.6.2
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry 1.3.2
diff --git a/docs/plat/qti.rst b/docs/plat/qti.rst
index 1d483e7..0f89500 100644
--- a/docs/plat/qti.rst
+++ b/docs/plat/qti.rst
@@ -2,7 +2,7 @@
===========================
Trusted Firmware-A (TF-A) implements the EL3 firmware layer for QTI SC7180,
-SC7280.
+SC7280 and QCS615.
Boot Trace
-------------
@@ -30,7 +30,8 @@
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sc7180 COREBOOT=1
-update value of CROSS_COMPILE argument with your cross-compilation toolchain.
+Update value of CROSS_COMPILE argument with your cross-compilation toolchain.
+Update the value of PLAT to be either of sc7180, sc7280 or qcs615
Additional QTISECLIB_PATH=<path to qtiseclib> can be added in build command.
if QTISECLIB_PATH is not added in build command stub implementation of qtiseclib
@@ -41,3 +42,4 @@
`link <https://github.com/coreboot/qc_blobs/blob/master/sc7180/qtiseclib/libqtisec.a?raw=true>`__
QTISELIB for SC7280 is available at
`link <https://github.com/coreboot/qc_blobs/blob/master/sc7280/qtiseclib/libqtisec.a?raw=true>`__
+QTISECLIB for QCS615 is not available yet and currently compile with stubs only.
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 765491e..b3c4c91 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -25,9 +25,9 @@
# Specify mbed TLS configuration file
ifeq (${PSA_CRYPTO},1)
- MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/psa_mbedtls_config.h>"
+ MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/default_psa_mbedtls_config.h>"
else
- MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/mbedtls_config-3.h>"
+ MBEDTLS_CONFIG_FILE ?= "<drivers/auth/mbedtls/default_mbedtls_config.h>"
endif
$(eval $(call add_define,MBEDTLS_CONFIG_FILE))
diff --git a/fdts/tc3-4-base.dtsi b/fdts/tc3-4-base.dtsi
index 2de5fd3..5ccfebb 100644
--- a/fdts/tc3-4-base.dtsi
+++ b/fdts/tc3-4-base.dtsi
@@ -52,6 +52,31 @@
};
};
+ rse_mbox_db_rx: mhu@RSE_MHU_RX_ADDR {
+ compatible = MHU_RX_COMPAT;
+ reg = <0x0 ADDRESSIFY(RSE_MHU_RX_ADDR) 0x0 MHU_OFFSET>;
+ clocks = <&soc_refclk>;
+ clock-names = "apb_pclk";
+ #mbox-cells = <MHU_MBOX_CELLS>;
+ interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = MHU_RX_INT_NAME;
+#if TARGET_FLAVOUR_FPGA
+ status = "disabled";
+#endif
+ };
+
+ rse_mbox_db_tx: mhu@RSE_MHU_TX_ADDR {
+ compatible = MHU_TX_COMPAT;
+ reg = <0x0 ADDRESSIFY(RSE_MHU_TX_ADDR) 0x0 MHU_OFFSET>;
+ clocks = <&soc_refclk>;
+ clock-names = "apb_pclk";
+ #mbox-cells = <MHU_MBOX_CELLS>;
+ interrupt-names = MHU_TX_INT_NAME;
+#if TARGET_FLAVOUR_FPGA
+ status = "disabled";
+#endif
+ };
+
gic: interrupt-controller@GIC_CTRL_ADDR {
ppi-partitions {
ppi_partition_little: interrupt-partition-0 {
@@ -80,5 +105,19 @@
mboxes = <&mbox_db_tx 0 0 0 &mbox_db_rx 0 0 0 &mbox_db_rx 0 0 1>;
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
+
+ rse {
+ compatible = "arm,rse";
+ mbox-names = "tx", "rx";
+ mboxes = <&rse_mbox_db_tx 0 0 0>, <&rse_mbox_db_rx 0 0 0>;
+#if TARGET_FLAVOUR_FPGA
+ status = "disabled";
+#endif
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
};
};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index ffe3b6d..3b02f91 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -13,6 +13,9 @@
#define MHU_TX_ADDR 46040000 /* hex */
#define MHU_RX_ADDR 46140000 /* hex */
+#define RSE_MHU_TX_ADDR 49010000 /* hex */
+#define RSE_MHU_RX_ADDR 49110000 /* hex */
+
#define LIT_CPU_PMU_COMPATIBLE "arm,cortex-a520-pmu"
#define MID_CPU_PMU_COMPATIBLE "arm,cortex-a725-pmu"
#define BIG_CPU_PMU_COMPATIBLE "arm,cortex-x925-pmu"
@@ -74,11 +77,6 @@
status = "okay";
};
- dsu-pmu {
- compatible = "arm,dsu-pmu";
- cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
- };
-
ni-pmu {
compatible = "arm,ni-tower";
reg = <0x0 0x4f000000 0x0 0x4000000>;
diff --git a/fdts/tc4.dts b/fdts/tc4.dts
index 135d30a..8b73b49 100644
--- a/fdts/tc4.dts
+++ b/fdts/tc4.dts
@@ -17,6 +17,9 @@
#define MID_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
#define BIG_CPU_PMU_COMPATIBLE "arm,armv8-pmuv3"
+#define RSE_MHU_TX_ADDR 49020000 /* hex */
+#define RSE_MHU_RX_ADDR 49030000 /* hex */
+
#define ETHERNET_ADDR 64000000
#define ETHERNET_INT 799
@@ -64,4 +67,8 @@
interrupt-names = "IRQAW";
iommus = <&smmu_700 0x200>;
};
+
+ dsu-pmu {
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 737d07a..3a7e2eb 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -465,6 +465,11 @@
#define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8)
#define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf)
+#define ID_AA64PFR2_EL1_FPMR_SHIFT U(32)
+#define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf)
+
+#define FPMR_IMPLEMENTED ULL(0x1)
+
#define VDISR_EL2 S3_4_C12_C1_1
#define VSESR_EL2 S3_4_C5_C2_3
@@ -605,6 +610,7 @@
#define SCR_NSE_SHIFT U(62)
#define SCR_FGTEN2_BIT (UL(1) << 59)
#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
+#define SCR_EnFPM_BIT (ULL(1) << 50)
#define SCR_GPF_BIT (UL(1) << 48)
#define SCR_D128En_BIT (UL(1) << 47)
#define SCR_TWEDEL_SHIFT U(30)
@@ -1522,6 +1528,11 @@
******************************************************************************/
#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
+/*******************************************************************************
+ * FEAT_FPMR - Floating point Mode Register
+ ******************************************************************************/
+#define FPMR S3_3_C4_C4_2
+
/* CLUSTERPWRDN_EL1 register definitions */
#define DSU_CLUSTER_PWR_OFF 0
#define DSU_CLUSTER_PWR_ON 1
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 59188da..8bdc13c 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -142,6 +142,8 @@
* +----------------------------+
* | FEAT_LS64_ACCDATA |
* +----------------------------+
+ * | FEAT_FPMR |
+ * +----------------------------+
*/
__attribute__((always_inline))
@@ -284,6 +286,12 @@
ID_AA64MMFR3_EL1_D128_MASK, D128_IMPLEMENTED,
ENABLE_FEAT_D128)
+/* FEAT_FPMR */
+CREATE_FEATURE_FUNCS(feat_fpmr, id_aa64pfr2_el1, ID_AA64PFR2_EL1_FPMR_SHIFT,
+ ID_AA64PFR2_EL1_FPMR_MASK, FPMR_IMPLEMENTED,
+ ENABLE_FEAT_FPMR)
+
+
__attribute__((always_inline))
static inline bool is_feat_sxpie_supported(void)
{
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 119c428..3f3f14d 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -718,6 +718,8 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
+DEFINE_RENAME_SYSREG_RW_FUNCS(fpmr, FPMR)
+
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)
diff --git a/include/drivers/auth/mbedtls/mbedtls_config-3.h b/include/drivers/auth/mbedtls/default_mbedtls_config.h
similarity index 96%
rename from include/drivers/auth/mbedtls/mbedtls_config-3.h
rename to include/drivers/auth/mbedtls/default_mbedtls_config.h
index 6ed9397..12a5fe1 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config-3.h
+++ b/include/drivers/auth/mbedtls/default_mbedtls_config.h
@@ -11,6 +11,11 @@
*/
/*
+ * This file is compatible with versions >= 3.6.2
+ */
+#define MBEDTLS_CONFIG_VERSION 0x03060200
+
+/*
* Key algorithms currently supported on mbed TLS libraries
*/
#define TF_MBEDTLS_RSA 1
diff --git a/include/drivers/auth/mbedtls/psa_mbedtls_config.h b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
similarity index 95%
rename from include/drivers/auth/mbedtls/psa_mbedtls_config.h
rename to include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
index 1001d89..8926051 100644
--- a/include/drivers/auth/mbedtls/psa_mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/default_psa_mbedtls_config.h
@@ -7,7 +7,7 @@
#ifndef PSA_MBEDTLS_CONFIG_H
#define PSA_MBEDTLS_CONFIG_H
-#include "mbedtls_config-3.h"
+#include "default_mbedtls_config.h"
#define MBEDTLS_PSA_CRYPTO_C
#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS
diff --git a/include/lib/extensions/fpmr.h b/include/lib/extensions/fpmr.h
new file mode 100644
index 0000000..bc3ee9e
--- /dev/null
+++ b/include/lib/extensions/fpmr.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FPMR_H
+#define FPMR_H
+
+#include <context.h>
+
+#if ENABLE_FEAT_FPMR
+void fpmr_enable_per_world(per_world_context_t *per_world_ctx);
+#else
+static inline void fpmr_enable_per_world(per_world_context_t *per_world_ctx)
+{
+}
+#endif /* ENABLE_FEAT_FPMR */
+
+#endif /* FPMR_H */
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index 320fd90..4ff0ea5 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -75,6 +75,12 @@
check_erratum_ls cortex_x4, ERRATUM(2897503), CPU_REV(0, 1)
+workaround_reset_start cortex_x4, ERRATUM(2923985), ERRATA_X4_2923985
+ sysreg_bit_set CORTEX_X4_CPUACTLR4_EL1, (BIT(11) | BIT(10))
+workaround_reset_end cortex_x4, ERRATUM(2923985)
+
+check_erratum_ls cortex_x4, ERRATUM(2923985), CPU_REV(0, 1)
+
workaround_reset_start cortex_x4, ERRATUM(3076789), ERRATA_X4_3076789
sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(14)
sysreg_bit_set CORTEX_X4_CPUACTLR3_EL1, BIT(13)
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4c20785..4a04a9d 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -843,6 +843,10 @@
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_2897503
+# Flag to apply erratum 2923985 workaround on reset. This erratum applies
+# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_X4_2923985
+
# Flag to apply erratum 3076789 workaround on reset. This erratum applies
# to revisions r0p0 and r0p1 of the Cortex-X4 cpu. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_X4_3076789
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 4ae1306..f963ed1 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -28,6 +28,7 @@
#include <lib/extensions/brbe.h>
#include <lib/extensions/debug_v8p9.h>
#include <lib/extensions/fgt2.h>
+#include <lib/extensions/fpmr.h>
#include <lib/extensions/mpam.h>
#include <lib/extensions/pmuv3.h>
#include <lib/extensions/sme.h>
@@ -291,6 +292,13 @@
scr_el3 |= SCR_D128En_BIT;
}
+ if (is_feat_fpmr_supported()) {
+ /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR
+ * register.
+ */
+ scr_el3 |= SCR_EnFPM_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
/* Initialize EL2 context registers */
@@ -714,6 +722,10 @@
if (is_feat_mpam_supported()) {
mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
}
+
+ if (is_feat_fpmr_supported()) {
+ fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
+ }
}
#endif /* IMAGE_BL31 */
diff --git a/lib/extensions/fpmr/fpmr.c b/lib/extensions/fpmr/fpmr.c
new file mode 100644
index 0000000..8e37e7a
--- /dev/null
+++ b/lib/extensions/fpmr/fpmr.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_features.h>
+#include <arch_helpers.h>
+#include <lib/extensions/fpmr.h>
+
+void fpmr_enable_per_world(per_world_context_t *per_world_ctx)
+{
+ u_register_t reg;
+
+ /* Disable Floating point Trap in CPTR_EL3. */
+ reg = per_world_ctx->ctx_cptr_el3;
+ reg &= ~TFP_BIT;
+ per_world_ctx->ctx_cptr_el3 = reg;
+}
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index bc31a2f..01a0395 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -12,17 +12,26 @@
BUILD_DIR = $(BUILD_PLAT)/romlib
LIB_DIR = $(BUILD_PLAT)/lib
WRAPPER_DIR = $(BUILD_PLAT)/libwrapper
-LIBS = $(LIB_DIR)/libmbedtls.a $(LIB_DIR)/libfdt.a $(LIB_DIR)/libc.a
+LIBS = $(LIB_DIR)/libfdt.a $(LIB_DIR)/libc.a
INC = $(INCLUDES:-I%=-I../../%)
PPFLAGS = $(INC) $(DEFINES) -P -x assembler-with-cpp -D__LINKER__ -MD -MP -MT $(BUILD_DIR)/romlib.ld
OBJS = $(BUILD_DIR)/jmptbl.o $(BUILD_DIR)/init.o
MAPFILE = $(BUILD_PLAT)/romlib/romlib.map
-ifneq ($(PLAT_DIR),)
- WRAPPER_SOURCES = $(sort $(shell $(ROMLIB_GEN) genwrappers -b $\
- $(WRAPPER_DIR) --list ../../$(PLAT_DIR)/jmptbl.i))
+PROCESSED_JMPTBL = ../../$(PLAT_DIR)/jmptbl.i
+
+# Determine if mbedtls is needed
+ifneq ($(filter $(CRYPTO_SUPPORT),1 2 3),)
+ PROCESSED_JMPTBL = $(BUILD_DIR)/jmptbl_processed.i
+ $(shell mkdir -p $(BUILD_DIR) && cat ../../$(PLAT_DIR)/jmptbl.i ../../$(PLAT_DIR)/jmptbl_mbedtls.i > $(BUILD_DIR)/jmptbl_processed.i)
+ LIBS += $(LIB_DIR)/libmbedtls.a
+endif
- WRAPPER_OBJS = $(WRAPPER_SOURCES:.s=.o)
+ifneq ($(PLAT_DIR),)
+ # Generate wrapper sources and objects
+ WRAPPER_SOURCES = $(sort $(shell $(ROMLIB_GEN) genwrappers -b $\
+ $(WRAPPER_DIR) --list $(PROCESSED_JMPTBL)))
+ WRAPPER_OBJS = $(WRAPPER_SOURCES:.s=.o)
endif
LDFLAGS := -Wl,--gc-sections -nostdlib
@@ -69,21 +78,21 @@
$(s)echo " AR $@"
$(q)$(aarch64-ar) -rc $@ $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
-$(BUILD_DIR)/jmptbl.i: ../../$(PLAT_DIR)/jmptbl.i | $$(@D)/
+$(BUILD_DIR)/jmptbl.i: $(PROCESSED_JMPTBL) | $$(@D)/
$(s)echo " PRE $@"
$(q)$(ROMLIB_GEN) pre --output $@ --deps $(BUILD_DIR)/jmptbl.d $<
-$(WRAPPER_SOURCES) $&: $(BUILD_DIR)/jmptbl.i | $$(@D)/
+$(WRAPPER_SOURCES) $&: $(PROCESSED_JMPTBL) | $$(@D)/
$(s)echo " WRP $<"
$(q)$(ROMLIB_GEN) genwrappers --bti=$(ENABLE_BTI) -b $(WRAPPER_DIR) $<
$(WRAPPER_OBJS): $(WRAPPER_DIR)/%.o: $(WRAPPER_DIR)/%.s | $$(@D)/
-$(BUILD_DIR)/jmptbl.s: $(BUILD_DIR)/jmptbl.i | $$(@D)/
+$(BUILD_DIR)/jmptbl.s: $(PROCESSED_JMPTBL) | $$(@D)/
$(s)echo " TBL $@"
$(q)$(ROMLIB_GEN) gentbl --output $@ --bti=$(ENABLE_BTI) $<
-$(BUILD_DIR)/romlib.ldflags: ../../$(PLAT_DIR)/jmptbl.i | $$(@D)/
+$(BUILD_DIR)/romlib.ldflags: $(PROCESSED_JMPTBL) | $$(@D)/
$(s)echo " LDFLAGS $@"
$(q)$(ROMLIB_GEN) link-flags $< > $@
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
deleted file mode 100644
index 44751a2..0000000
--- a/lib/romlib/jmptbl.i
+++ /dev/null
@@ -1,44 +0,0 @@
-#
-# Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-# Format:
-# lib function [patch]
-# Add "patch" at the end of the line to patch a function. For example:
-# mbedtls mbedtls_memory_buffer_alloc_init patch
-# Holes can be introduced in the table by using a special keyword "reserved".
-# Example:
-# reserved reserved
-# The jump table will contain an invalid instruction instead of branch
-
-rom rom_lib_init
-fdt fdt_getprop_namelen
-fdt fdt_setprop_inplace
-fdt fdt_check_header
-fdt fdt_node_offset_by_compatible
-fdt fdt_setprop_inplace_namelen_partial
-mbedtls mbedtls_asn1_get_alg
-mbedtls mbedtls_asn1_get_alg_null
-mbedtls mbedtls_asn1_get_bitstring_null
-mbedtls mbedtls_asn1_get_bool
-mbedtls mbedtls_asn1_get_int
-mbedtls mbedtls_asn1_get_tag
-mbedtls mbedtls_free
-mbedtls mbedtls_md
-mbedtls mbedtls_md_get_size
-mbedtls mbedtls_memory_buffer_alloc_init
-mbedtls mbedtls_oid_get_md_alg
-mbedtls mbedtls_oid_get_numeric_string
-mbedtls mbedtls_oid_get_pk_alg
-mbedtls mbedtls_oid_get_sig_alg
-mbedtls mbedtls_pk_free
-mbedtls mbedtls_pk_init
-mbedtls mbedtls_pk_parse_subpubkey
-mbedtls mbedtls_pk_verify_ext
-mbedtls mbedtls_platform_set_snprintf
-mbedtls mbedtls_x509_get_rsassa_pss_params
-mbedtls mbedtls_x509_get_sig_alg
-mbedtls mbedtls_md_info_from_type
-c exit
-c atexit
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index 57609d5..a1db0b8 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -408,6 +408,9 @@
# if FEAT_BRBE is implemented.
ENABLE_BRBE_FOR_NS ?= 0
+# Flag to enable Floating point exception Mode Register Feature (FEAT_FPMR)
+ENABLE_FEAT_FPMR ?= 0
+
#----
# 9.3
#----
diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i
index 077283e..a23de73 100644
--- a/plat/arm/board/fvp/jmptbl.i
+++ b/plat/arm/board/fvp/jmptbl.i
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -37,28 +37,5 @@
fdt fdt_get_alias
fdt fdt_node_offset_by_phandle
fdt fdt_add_subnode
-mbedtls mbedtls_asn1_get_alg
-mbedtls mbedtls_asn1_get_alg_null
-mbedtls mbedtls_asn1_get_bitstring_null
-mbedtls mbedtls_asn1_get_bool
-mbedtls mbedtls_asn1_get_int
-mbedtls mbedtls_asn1_get_len
-mbedtls mbedtls_asn1_get_tag
-mbedtls mbedtls_free
-mbedtls mbedtls_md
-mbedtls mbedtls_md_get_size
-mbedtls mbedtls_memory_buffer_alloc_init
-mbedtls mbedtls_oid_get_md_alg
-mbedtls mbedtls_oid_get_numeric_string
-mbedtls mbedtls_oid_get_pk_alg
-mbedtls mbedtls_oid_get_sig_alg
-mbedtls mbedtls_pk_free
-mbedtls mbedtls_pk_init
-mbedtls mbedtls_pk_parse_subpubkey
-mbedtls mbedtls_pk_verify_ext
-mbedtls mbedtls_platform_set_snprintf
-mbedtls mbedtls_x509_get_rsassa_pss_params
-mbedtls mbedtls_x509_get_sig_alg
-mbedtls mbedtls_md_info_from_type
c exit
c atexit
diff --git a/plat/arm/board/fvp/jmptbl_mbedtls.i b/plat/arm/board/fvp/jmptbl_mbedtls.i
new file mode 100644
index 0000000..6e1f017
--- /dev/null
+++ b/plat/arm/board/fvp/jmptbl_mbedtls.i
@@ -0,0 +1,38 @@
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform-specific ROMLIB MbedTLS functions can be added here.
+# During the build process, this file is appended to jmptbl.i
+# if MbedTLS support is required.
+#
+# Format:
+# lib function [patch]
+# Example:
+# mbedtls mbedtls_asn1_get_alg
+# mbedtls mbedtls_asn1_get_alg_null patch
+
+mbedtls mbedtls_asn1_get_alg
+mbedtls mbedtls_asn1_get_alg_null
+mbedtls mbedtls_asn1_get_bitstring_null
+mbedtls mbedtls_asn1_get_bool
+mbedtls mbedtls_asn1_get_int
+mbedtls mbedtls_asn1_get_len
+mbedtls mbedtls_asn1_get_tag
+mbedtls mbedtls_free
+mbedtls mbedtls_md
+mbedtls mbedtls_md_get_size
+mbedtls mbedtls_memory_buffer_alloc_init
+mbedtls mbedtls_oid_get_md_alg
+mbedtls mbedtls_oid_get_numeric_string
+mbedtls mbedtls_oid_get_pk_alg
+mbedtls mbedtls_oid_get_sig_alg
+mbedtls mbedtls_pk_free
+mbedtls mbedtls_pk_init
+mbedtls mbedtls_pk_parse_subpubkey
+mbedtls mbedtls_pk_verify_ext
+mbedtls mbedtls_platform_set_snprintf
+mbedtls mbedtls_x509_get_rsassa_pss_params
+mbedtls mbedtls_x509_get_sig_alg
+mbedtls mbedtls_md_info_from_type
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 1340a65..3b638e4 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -57,6 +57,7 @@
ENABLE_BRBE_FOR_NS := 2
ENABLE_TRBE_FOR_NS := 2
ENABLE_FEAT_D128 := 2
+ ENABLE_FEAT_FPMR := 2
endif
ENABLE_SYS_REG_TRACE_FOR_NS := 2
diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i
index 327a345..a62661d 100644
--- a/plat/arm/board/juno/jmptbl.i
+++ b/plat/arm/board/juno/jmptbl.i
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -36,28 +36,5 @@
fdt fdt_node_offset_by_phandle
fdt fdt_subnode_offset
fdt fdt_add_subnode
-mbedtls mbedtls_asn1_get_alg
-mbedtls mbedtls_asn1_get_alg_null
-mbedtls mbedtls_asn1_get_bitstring_null
-mbedtls mbedtls_asn1_get_bool
-mbedtls mbedtls_asn1_get_int
-mbedtls mbedtls_asn1_get_len
-mbedtls mbedtls_asn1_get_tag
-mbedtls mbedtls_free
-mbedtls mbedtls_md
-mbedtls mbedtls_md_get_size
-mbedtls mbedtls_memory_buffer_alloc_init
-mbedtls mbedtls_oid_get_md_alg
-mbedtls mbedtls_oid_get_numeric_string
-mbedtls mbedtls_oid_get_pk_alg
-mbedtls mbedtls_oid_get_sig_alg
-mbedtls mbedtls_pk_free
-mbedtls mbedtls_pk_init
-mbedtls mbedtls_pk_parse_subpubkey
-mbedtls mbedtls_pk_verify_ext
-mbedtls mbedtls_platform_set_snprintf
-mbedtls mbedtls_x509_get_rsassa_pss_params
-mbedtls mbedtls_x509_get_sig_alg
-mbedtls mbedtls_md_info_from_type
c exit
c atexit
diff --git a/plat/arm/board/juno/jmptbl_mbedtls.i b/plat/arm/board/juno/jmptbl_mbedtls.i
new file mode 100644
index 0000000..6e1f017
--- /dev/null
+++ b/plat/arm/board/juno/jmptbl_mbedtls.i
@@ -0,0 +1,38 @@
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform-specific ROMLIB MbedTLS functions can be added here.
+# During the build process, this file is appended to jmptbl.i
+# if MbedTLS support is required.
+#
+# Format:
+# lib function [patch]
+# Example:
+# mbedtls mbedtls_asn1_get_alg
+# mbedtls mbedtls_asn1_get_alg_null patch
+
+mbedtls mbedtls_asn1_get_alg
+mbedtls mbedtls_asn1_get_alg_null
+mbedtls mbedtls_asn1_get_bitstring_null
+mbedtls mbedtls_asn1_get_bool
+mbedtls mbedtls_asn1_get_int
+mbedtls mbedtls_asn1_get_len
+mbedtls mbedtls_asn1_get_tag
+mbedtls mbedtls_free
+mbedtls mbedtls_md
+mbedtls mbedtls_md_get_size
+mbedtls mbedtls_memory_buffer_alloc_init
+mbedtls mbedtls_oid_get_md_alg
+mbedtls mbedtls_oid_get_numeric_string
+mbedtls mbedtls_oid_get_pk_alg
+mbedtls mbedtls_oid_get_sig_alg
+mbedtls mbedtls_pk_free
+mbedtls mbedtls_pk_init
+mbedtls mbedtls_pk_parse_subpubkey
+mbedtls mbedtls_pk_verify_ext
+mbedtls mbedtls_platform_set_snprintf
+mbedtls mbedtls_x509_get_rsassa_pss_params
+mbedtls mbedtls_x509_get_sig_alg
+mbedtls mbedtls_md_info_from_type
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
index 9adf09a..48ca16c 100644
--- a/plat/arm/board/tc/include/tc_helpers.S
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -82,6 +82,9 @@
endfunc TC_HANDLER(3)
func TC_HANDLER(4)
+ mov x9, lr
+ bl enable_dsu_pmu_el1_access
+ mov lr, x9
ret
endfunc TC_HANDLER(4)
diff --git a/plat/arm/board/tc/plat_tc_mbedtls_config.h b/plat/arm/board/tc/plat_tc_mbedtls_config.h
index 4fd8b6b..9118b0b 100644
--- a/plat/arm/board/tc/plat_tc_mbedtls_config.h
+++ b/plat/arm/board/tc/plat_tc_mbedtls_config.h
@@ -8,7 +8,7 @@
#define PLAT_TC_MBEDTLS_CONFIG_H
#include <export/lib/utils_def_exp.h>
-#include <mbedtls_config-3.h>
+#include <default_mbedtls_config.h>
#ifndef TF_MBEDTLS_HEAP_SIZE
#error TF_MBEDTLS_HEAP_SIZE is not defined
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index 3178c06..759c85d 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -230,18 +230,17 @@
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG}))
+$(info Including rse_comms.mk)
+include drivers/arm/rse/rse_comms.mk
+
+BL1_SOURCES += ${RSE_COMMS_SOURCES}
+BL2_SOURCES += ${RSE_COMMS_SOURCES}
+BL31_SOURCES += ${RSE_COMMS_SOURCES}
+
# Include Measured Boot makefile before any Crypto library makefile.
# Crypto library makefile may need default definitions of Measured Boot build
# flags present in Measured Boot makefile.
-$(info Including rse_comms.mk)
ifeq (${MEASURED_BOOT},1)
- $(info Including rse_comms.mk)
- include drivers/arm/rse/rse_comms.mk
-
- BL1_SOURCES += ${RSE_COMMS_SOURCES}
- BL2_SOURCES += ${RSE_COMMS_SOURCES}
- PLAT_INCLUDES += -Iinclude/lib/psa
-
ifeq (${DICE_PROTECTION_ENVIRONMENT},1)
$(info Including qcbor.mk)
include drivers/measured_boot/rse/qcbor.mk
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 801872a..06055d4 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -26,6 +26,10 @@
#include <psa/crypto_values.h>
#endif /* PLATFORM_TEST_TFM_TESTSUITE */
+#include <drivers/arm/rse_comms.h>
+#include <plat/common/platform.h>
+#include "rse_platform_api.h"
+
#ifdef PLATFORM_TEST_TFM_TESTSUITE
/*
* We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
@@ -190,6 +194,12 @@
plat_arm_secure_wdt_start();
arm_bl31_plat_runtime_setup();
+
+ /* Initialise RSE communication channel */
+ status = rse_comms_init(PLAT_RSE_AP_SND_MHU_BASE, PLAT_RSE_AP_RCV_MHU_BASE);
+ if (status != PSA_SUCCESS) {
+ ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status);
+ }
}
void bl31_plat_runtime_setup(void)
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
index fed14f7..1ecfdb9 100644
--- a/plat/arm/board/tc/tc_plat.c
+++ b/plat/arm/board/tc/tc_plat.c
@@ -40,6 +40,7 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
TC_FLASH0_RO,
+ ARM_V2M_MAP_MEM_PROTECT,
TC_MAP_DEVICE,
TC_MAP_NS_DRAM1,
#if defined(SPD_spmd)
@@ -65,6 +66,7 @@
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
+ ARM_V2M_MAP_MEM_PROTECT,
TC_MAP_DEVICE,
PLAT_DTB_DRAM_NS,
#if SPM_MM
diff --git a/plat/arm/common/plat_arm_mbedtls_config.h b/plat/arm/common/plat_arm_mbedtls_config.h
index a5d0ec4..c2db595 100644
--- a/plat/arm/common/plat_arm_mbedtls_config.h
+++ b/plat/arm/common/plat_arm_mbedtls_config.h
@@ -7,7 +7,7 @@
#ifndef PLAT_ARM_MBEDTLS_CONFIG_H
#define PLAT_ARM_MBEDTLS_CONFIG_H
-#include <mbedtls_config-3.h>
+#include <default_mbedtls_config.h>
/**
* On Arm platforms, the ROTPK is always hashed using the SHA-256
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index dfa409f..e27af21 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -243,7 +243,8 @@
void mailbox_reset_warm(uint32_t reset_type);
void mailbox_clear_response(void);
-int intel_mailbox_get_config_status(uint32_t cmd, bool init_done);
+int intel_mailbox_get_config_status(uint32_t cmd, bool init_done,
+ uint32_t *err_states);
int intel_mailbox_is_fpga_not_ready(void);
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 94895ba..69f0008 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -638,7 +638,8 @@
return MBOX_RET_OK;
}
-int intel_mailbox_get_config_status(uint32_t cmd, bool init_done)
+int intel_mailbox_get_config_status(uint32_t cmd, bool init_done,
+ uint32_t *err_states)
{
int status;
uint32_t res, response[6];
@@ -653,6 +654,9 @@
res = response[RECONFIG_STATUS_STATE];
+ if (err_states != NULL)
+ *err_states = res;
+
if (res == MBOX_CFGSTAT_VAB_BS_PREAUTH) {
return MBOX_CFGSTAT_STATE_CONFIG;
}
@@ -684,11 +688,11 @@
int intel_mailbox_is_fpga_not_ready(void)
{
- int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true);
+ int ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true, NULL);
if ((ret != MBOX_RET_OK) && (ret != MBOX_CFGSTAT_STATE_CONFIG)) {
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
- false);
+ false, NULL);
}
return ret;
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 68deab9..71a626d 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -94,22 +94,25 @@
return 0;
}
-static uint32_t intel_mailbox_fpga_config_isdone(void)
+static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states)
{
uint32_t ret;
+ if (err_states == NULL)
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+
switch (request_type) {
case RECONFIGURATION:
ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
- true);
+ true, err_states);
break;
case BITSTREAM_AUTH:
ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS,
- false);
+ false, err_states);
break;
default:
ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS,
- false);
+ false, err_states);
break;
}
@@ -814,6 +817,7 @@
uint32_t retval = 0, completed_addr[3];
uint32_t retval2 = 0;
uint32_t mbox_error = 0;
+ uint32_t err_states = 0;
uint64_t retval64, rsu_respbuf[9];
uint32_t seu_respbuf[3];
int status = INTEL_SIP_SMC_STATUS_OK;
@@ -827,8 +831,8 @@
SMC_UUID_RET(handle, intl_svc_uid);
case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE:
- status = intel_mailbox_fpga_config_isdone();
- SMC_RET4(handle, status, 0, 0, 0);
+ status = intel_mailbox_fpga_config_isdone(&err_states);
+ SMC_RET4(handle, status, err_states, 0, 0);
case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM:
SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK,
diff --git a/plat/qti/common/src/qti_gic_v3.c b/plat/qti/common/src/qti_gic_v3.c
index f00267a..746c6f1 100644
--- a/plat/qti/common/src/qti_gic_v3.c
+++ b/plat/qti/common/src/qti_gic_v3.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, The Linux Foundation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,24 +54,36 @@
INTR_GROUP0,
GIC_INTR_CFG_EDGE),
#endif
+#ifdef QTISECLIB_INT_ID_A2_NOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_A2_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
INTR_GROUP0,
GIC_INTR_CFG_EDGE),
+#endif
+#ifdef QTISECLIB_INT_ID_CONFIG_NOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_CONFIG_NOC_ERROR,
GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
GIC_INTR_CFG_EDGE),
+#endif
+#ifdef QTISECLIB_INT_ID_DC_NOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_DC_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
INTR_GROUP0,
GIC_INTR_CFG_EDGE),
+#endif
+#ifdef QTISECLIB_INT_ID_MEM_NOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_MEM_NOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
INTR_GROUP0,
GIC_INTR_CFG_EDGE),
+#endif
+#ifdef QTISECLIB_INT_ID_SYSTEM_NOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_SYSTEM_NOC_ERROR,
GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
GIC_INTR_CFG_EDGE),
+#endif
+#ifdef QTISECLIB_INT_ID_MMSS_NOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_MMSS_NOC_ERROR,
GIC_HIGHEST_SEC_PRIORITY, INTR_GROUP0,
GIC_INTR_CFG_EDGE),
+#endif
#ifdef QTISECLIB_INT_ID_LPASS_AGNOC_ERROR
INTR_PROP_DESC(QTISECLIB_INT_ID_LPASS_AGNOC_ERROR, GIC_HIGHEST_SEC_PRIORITY,
INTR_GROUP0,
diff --git a/plat/qti/qcs615/inc/platform_def.h b/plat/qti/qcs615/inc/platform_def.h
new file mode 100644
index 0000000..5b8ff7d
--- /dev/null
+++ b/plat/qti/qcs615/inc/platform_def.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+/* Enable the dynamic translation tables library. */
+#define PLAT_XLAT_TABLES_DYNAMIC 1
+
+#include <common_def.h>
+
+#include <qti_board_def.h>
+#include <qtiseclib_defs_plat.h>
+
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+/*
+ * MPIDR_PRIMARY_CPU
+ * You just need to have the correct core_affinity_val i.e. [7:0]
+ * and cluster_affinity_val i.e. [15:8]
+ * the other bits will be ignored
+ */
+/*----------------------------------------------------------------------------*/
+#define MPIDR_PRIMARY_CPU 0x0000
+/*----------------------------------------------------------------------------*/
+
+#define QTI_PWR_LVL0 MPIDR_AFFLVL0
+#define QTI_PWR_LVL1 MPIDR_AFFLVL1
+#define QTI_PWR_LVL2 MPIDR_AFFLVL2
+#define QTI_PWR_LVL3 MPIDR_AFFLVL3
+
+/*
+ * Macros for local power states encoded by State-ID field
+ * within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define QTI_LOCAL_STATE_RUN 0
+/*
+ * Local power state for clock-gating. Valid only for CPU and not cluster power
+ * domains
+ */
+#define QTI_LOCAL_STATE_STB 1
+/*
+ * Local power state for retention. Valid for CPU and cluster power
+ * domains
+ */
+#define QTI_LOCAL_STATE_RET 2
+/*
+ * Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC
+ * power domains
+ */
+#define QTI_LOCAL_STATE_OFF 3
+/*
+ * Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC
+ * power domains
+ */
+#define QTI_LOCAL_STATE_DEEPOFF 4
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF
+
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/*
+ * Platform specific page table and MMU setup constants.
+ */
+#define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36)
+
+#define ARM_CACHE_WRITEBACK_SHIFT 6
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
+
+/*
+ * One cache line needed for bakery locks on ARM platforms
+ */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+/*----------------------------------------------------------------------------*/
+/* PSCI power domain topology definitions */
+/*----------------------------------------------------------------------------*/
+/* One domain each to represent RSC and PDC level */
+#define PLAT_PDC_COUNT 1
+#define PLAT_RSC_COUNT 1
+
+/* There is one top-level FCM cluster */
+#define PLAT_CLUSTER_COUNT 1
+
+/* No. of cores in the FCM cluster */
+#define PLAT_CLUSTER0_CORE_COUNT 8
+
+#define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT)
+
+#define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\
+ PLAT_RSC_COUNT +\
+ PLAT_CLUSTER_COUNT +\
+ PLATFORM_CORE_COUNT)
+
+#define PLAT_MAX_PWR_LVL 3
+
+/*****************************************************************************/
+/* Memory mapped Generic timer interfaces */
+/*****************************************************************************/
+
+/*----------------------------------------------------------------------------*/
+/* GIC-600 constants */
+/*----------------------------------------------------------------------------*/
+#define BASE_GICD_BASE 0x17A00000
+#define BASE_GICR_BASE 0x17A60000
+#define BASE_GICC_BASE 0x0
+#define BASE_GICH_BASE 0x0
+#define BASE_GICV_BASE 0x0
+
+#define QTI_GICD_BASE BASE_GICD_BASE
+#define QTI_GICR_BASE BASE_GICR_BASE
+#define QTI_GICC_BASE BASE_GICC_BASE
+
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+/* UART related constants. */
+/*----------------------------------------------------------------------------*/
+/* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */
+#define GENI4_CFG 0x0
+#define GENI4_IMAGE_REGS 0x100
+#define GENI4_DATA 0x600
+
+/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */
+#define GENI_STATUS_REG (GENI4_CFG + 0x00000040)
+#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1)
+#define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170)
+/* MASTER/TX ENGINE REGISTERS */
+#define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000)
+/* FIFO, STATUS REGISTERS AND MASKS */
+#define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100)
+
+#define GENI_M_CMD_TX (0x08000000)
+
+/*----------------------------------------------------------------------------*/
+/* Device address space for mapping. Excluding starting 4K */
+/*----------------------------------------------------------------------------*/
+#define QTI_DEVICE_BASE 0x1000
+#define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL31 at DDR as per memory map. BL31_BASE is calculated using the
+ * current BL31 debug size plus a little space for growth.
+ */
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+
+/*----------------------------------------------------------------------------*/
+/* AOSS registers */
+/*----------------------------------------------------------------------------*/
+#define QTI_PS_HOLD_REG 0x0C264000
+/*----------------------------------------------------------------------------*/
+/* AOP CMD DB address space for mapping */
+/*----------------------------------------------------------------------------*/
+#define QTI_AOP_CMD_DB_BASE 0x85F20000
+#define QTI_AOP_CMD_DB_SIZE 0x00020000
+/*----------------------------------------------------------------------------*/
+/* SOC hw version register */
+/*----------------------------------------------------------------------------*/
+#define QTI_SOC_VERSION_MASK U(0xFFFF)
+#define QTI_SOC_REVISION_REG 0x1FC8000
+#define QTI_SOC_REVISION_MASK U(0xFFFF)
+/*----------------------------------------------------------------------------*/
+/* LC PON register offsets */
+/*----------------------------------------------------------------------------*/
+#define PON_PS_HOLD_RESET_CTL 0x85a
+#define PON_PS_HOLD_RESET_CTL2 0x85b
+/*----------------------------------------------------------------------------*/
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/qti/qcs615/inc/qti_map_chipinfo.h b/plat/qti/qcs615/inc/qti_map_chipinfo.h
new file mode 100644
index 0000000..6092ea0
--- /dev/null
+++ b/plat/qti/qcs615/inc/qti_map_chipinfo.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef QTI_MAP_CHIPINFO_H
+#define QTI_MAP_CHIPINFO_H
+
+#include <stdint.h>
+
+#include <qti_plat.h>
+
+#define QTI_JTAG_ID_REG 0x786130
+#define QTI_JTAG_ID_SHIFT 12
+#define QTI_JTAG_ID_QCS615 U(0x02E9)
+#define QTI_JTAG_ID_SA6155P U(0x00EE)
+#define QTI_CHIPINFO_ID_QCS615 U(0x01E7)
+#define QTI_CHIPINFO_ID_SA6155P U(0x0179)
+#define QTI_DEFAULT_CHIPINFO_ID U(0xFFFF)
+
+static const chip_id_info_t g_map_jtag_chipinfo_id[] = {
+ {QTI_JTAG_ID_QCS615, QTI_CHIPINFO_ID_QCS615},
+ {QTI_JTAG_ID_SA6155P, QTI_CHIPINFO_ID_SA6155P},
+};
+
+#endif /* QTI_MAP_CHIPINFO_H */
diff --git a/plat/qti/qcs615/inc/qti_rng_io.h b/plat/qti/qcs615/inc/qti_rng_io.h
new file mode 100644
index 0000000..b5e521e
--- /dev/null
+++ b/plat/qti/qcs615/inc/qti_rng_io.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef QTI_RNG_IO_H
+#define QTI_RNG_IO_H
+
+#define SEC_PRNG_STATUS 0x791004
+#define SEC_PRNG_STATUS_DATA_AVAIL_BMSK 0x1
+#define SEC_PRNG_DATA_OUT 0x791000
+
+#endif /* QTI_RNG_IO_H */
+
diff --git a/plat/qti/qcs615/inc/qti_secure_io_cfg.h b/plat/qti/qcs615/inc/qti_secure_io_cfg.h
new file mode 100644
index 0000000..a78583e
--- /dev/null
+++ b/plat/qti/qcs615/inc/qti_secure_io_cfg.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QTI_SECURE_IO_CFG_H
+#define QTI_SECURE_IO_CFG_H
+
+#include <stdint.h>
+
+/*
+ * List of peripheral/IO memory areas that are protected from
+ * non-secure world but not required to be secure.
+ */
+#define APPS_SMMU_TBU_PWR_STATUS 0x15002204
+#define APPS_SMMU_CUSTOM_CFG 0x15002300
+#define APPS_SMMU_STATS_SYNC_INV_TBU_ACK 0x150025DC
+#define APPS_SMMU_SAFE_SEC_CFG 0x15002644
+#define APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x15002648
+
+static const uintptr_t qti_secure_io_allowed_regs[] = {
+ APPS_SMMU_TBU_PWR_STATUS,
+ APPS_SMMU_CUSTOM_CFG,
+ APPS_SMMU_STATS_SYNC_INV_TBU_ACK,
+ APPS_SMMU_SAFE_SEC_CFG,
+ APPS_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
+};
+
+static const uintptr_t qti_secure_io_debug_allowed_regs[] = {
+};
+
+
+#endif /* QTI_SECURE_IO_CFG_H */
diff --git a/plat/qti/qcs615/platform.mk b/plat/qti/qcs615/platform.mk
new file mode 100644
index 0000000..a3136cb
--- /dev/null
+++ b/plat/qti/qcs615/platform.mk
@@ -0,0 +1,142 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2024, The Linux Foundation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Makefile for QCS615 QTI platform.
+
+QTI_PLAT_PATH := plat/qti
+CHIPSET := ${PLAT}
+
+# Turn On Separate code & data.
+SEPARATE_CODE_AND_RODATA := 1
+USE_COHERENT_MEM := 0
+WARMBOOT_ENABLE_DCACHE_EARLY := 1
+HW_ASSISTED_COHERENCY := 1
+
+# Enable errata configs for cortex_a76 and cortex_a55
+# QCS615 CPU core revisions are r1p0
+ERRATA_A55_1221012 := 1
+ERRATA_A55_1530923 := 1
+ERRATA_A76_1073348 := 1
+ERRATA_A76_1130799 := 1
+ERRATA_A76_1220197 := 1
+ERRATA_A76_1257314 := 1
+ERRATA_A76_1262606 := 1
+ERRATA_A76_1262888 := 1
+ERRATA_A76_1275112 := 1
+ERRATA_A76_1791580 := 1
+ERRATA_A76_1165522 := 1
+ERRATA_A76_1868343 := 1
+ERRATA_A76_1946160 := 1
+ERRATA_A76_2743102 := 1
+
+# Disable the PSCI platform compatibility layer
+ENABLE_PLAT_COMPAT := 0
+
+# Enable PSCI v1.0 extended state ID format
+PSCI_EXTENDED_STATE_ID := 1
+ARM_RECOM_STATE_ID_ENC := 1
+PSCI_OS_INIT_MODE := 1
+
+COLD_BOOT_SINGLE_CPU := 1
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+RESET_TO_BL31 := 0
+
+QTI_SDI_BUILD := 0
+$(eval $(call assert_boolean,QTI_SDI_BUILD))
+$(eval $(call add_define,QTI_SDI_BUILD))
+
+#disable CTX_INCLUDE_AARCH32_REGS to support QCS615 gold cores
+override CTX_INCLUDE_AARCH32_REGS := 0
+
+# Set dynamic CVE_2018_3639 explicitly as it defaults to 0.
+# Others which are applicable: CVE_2017_5715 & CVE_2022_23960 default to 1
+DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
+
+# Enable stack protector.
+ENABLE_STACK_PROTECTOR := strong
+
+
+QTI_EXTERNAL_INCLUDES := -I${QTI_PLAT_PATH}/${CHIPSET}/inc \
+ -I${QTI_PLAT_PATH}/common/inc \
+ -I${QTI_PLAT_PATH}/common/inc/$(ARCH) \
+ -I${QTI_PLAT_PATH}/qtiseclib/inc \
+ -I${QTI_PLAT_PATH}/qtiseclib/inc/${CHIPSET} \
+
+QTI_BL31_SOURCES := $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_helpers.S \
+ $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_silver.S \
+ $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo4_gold.S \
+ $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_uart_console.S \
+ $(QTI_PLAT_PATH)/common/src/pm_ps_hold.c \
+ $(QTI_PLAT_PATH)/common/src/qti_stack_protector.c \
+ $(QTI_PLAT_PATH)/common/src/qti_common.c \
+ $(QTI_PLAT_PATH)/common/src/qti_bl31_setup.c \
+ $(QTI_PLAT_PATH)/common/src/qti_gic_v3.c \
+ $(QTI_PLAT_PATH)/common/src/qti_interrupt_svc.c \
+ $(QTI_PLAT_PATH)/common/src/qti_syscall.c \
+ $(QTI_PLAT_PATH)/common/src/qti_topology.c \
+ $(QTI_PLAT_PATH)/common/src/qti_pm.c \
+ $(QTI_PLAT_PATH)/common/src/qti_rng.c \
+ $(QTI_PLAT_PATH)/common/src/spmi_arb.c \
+ $(QTI_PLAT_PATH)/qtiseclib/src/qtiseclib_cb_interface.c \
+
+
+PLAT_INCLUDES := -Iinclude/plat/common/ \
+ ${QTI_EXTERNAL_INCLUDES}
+
+include lib/xlat_tables_v2/xlat_tables.mk
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
+ plat/common/aarch64/crash_console_helpers.S \
+ common/desc_image_load.c \
+ lib/bl_aux_params/bl_aux_params.c \
+
+include lib/coreboot/coreboot.mk
+
+#PSCI Sources.
+PSCI_SOURCES := plat/common/plat_psci_common.c \
+
+# GIC-600 configuration
+GICV3_SUPPORT_GIC600 := 1
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+#Timer sources
+TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \
+ drivers/delay_timer/delay_timer.c \
+
+#GIC sources.
+GIC_SOURCES := plat/common/plat_gicv3.c \
+ ${GICV3_SOURCES} \
+
+CPU_SOURCES := lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/cortex_a55.S \
+
+BL31_SOURCES += ${QTI_BL31_SOURCES} \
+ ${PSCI_SOURCES} \
+ ${GIC_SOURCES} \
+ ${TIMER_SOURCES} \
+ ${CPU_SOURCES} \
+
+LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}
+
+
+# Override this on the command line to point to the qtiseclib library which
+# will be available in coreboot.org
+QTISECLIB_PATH ?=
+
+ifeq ($(QTISECLIB_PATH),)
+# if No lib then use stub implementation for qtiseclib interface
+$(warning QTISECLIB_PATH is not provided while building, using stub implementation. \
+ Please refer docs/plat/qti.rst for more details \
+ THIS FIRMWARE WILL NOT BOOT!)
+BL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
+else
+# use library provided by QTISECLIB_PATH
+LDFLAGS += -L $(dir $(QTISECLIB_PATH))
+LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH)))
+endif
+
diff --git a/plat/qti/qtiseclib/inc/qcs615/qtiseclib_defs_plat.h b/plat/qti/qtiseclib/inc/qcs615/qtiseclib_defs_plat.h
new file mode 100644
index 0000000..2dbcc83
--- /dev/null
+++ b/plat/qti/qtiseclib/inc/qcs615/qtiseclib_defs_plat.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __QTISECLIB_DEFS_PLAT_H__
+#define __QTISECLIB_DEFS_PLAT_H__
+
+#define QTISECLIB_PLAT_CLUSTER_COUNT 1
+#define QTISECLIB_PLAT_CORE_COUNT 8
+
+#define BL31_BASE 0x86200000
+#define BL31_SIZE 0x00100000
+
+/*----------------------------------------------------------------------------*/
+/* AOP CMD DB address space for mapping */
+/*----------------------------------------------------------------------------*/
+#define QTI_AOP_CMD_DB_BASE 0x85F20000
+#define QTI_AOP_CMD_DB_SIZE 0x00020000
+
+/* Chipset specific secure interrupt number/ID defs. */
+#define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204)
+#define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21)
+
+#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_SEC (0xE6)
+#define QTISECLIB_INT_ID_VMIDMT_ERR_CLT_NONSEC (0xE7)
+#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_SEC (0xE8)
+#define QTISECLIB_INT_ID_VMIDMT_ERR_CFG_NONSEC (0xE9)
+
+#define QTISECLIB_INT_ID_XPU_SEC (0xE3)
+#define QTISECLIB_INT_ID_XPU_NON_SEC (0xE4)
+
+//NOC INterrupt
+#define QTISECLIB_INT_ID_A1_NOC_ERROR (0x18B)
+#define QTISECLIB_INT_ID_CONFIG_NOC_ERROR (0xE2)
+#define QTISECLIB_INT_ID_DC_NOC_ERROR (0x122)
+#define QTISECLIB_INT_ID_MEM_NOC_ERROR (0x6C) //GEM_NOC
+#define QTISECLIB_INT_ID_SYSTEM_NOC_ERROR (0xC6)
+#define QTISECLIB_INT_ID_MMSS_NOC_ERROR (0xBA)
+
+#endif /* __QTISECLIB_DEFS_PLAT_H__ */
diff --git a/plat/rockchip/common/drivers/pmu/pmu_com.h b/plat/rockchip/common/drivers/pmu/pmu_com.h
index 022bb02..84f9421 100644
--- a/plat/rockchip/common/drivers/pmu/pmu_com.h
+++ b/plat/rockchip/common/drivers/pmu/pmu_com.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,8 +32,6 @@
};
#pragma weak plat_ic_get_pending_interrupt_id
-#pragma weak pmu_power_domain_ctr
-#pragma weak check_cpu_wfie
static inline uint32_t pmu_power_domain_st(uint32_t pd)
{
diff --git a/plat/rockchip/px30/drivers/pmu/pmu.c b/plat/rockchip/px30/drivers/pmu/pmu.c
index 8770b2e..0d8e8b6 100644
--- a/plat/rockchip/px30/drivers/pmu/pmu.c
+++ b/plat/rockchip/px30/drivers/pmu/pmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -867,18 +867,6 @@
ERROR("Can't wait pll:%d lock\n", pll_id);
}
-static inline void pll_pwr_ctr(uint32_t pll_base, uint32_t pll_id, uint32_t pd)
-{
- mmio_write_32(pll_base + PLL_CON(1),
- BITS_WITH_WMASK(1, 1U, 15));
- if (pd)
- mmio_write_32(pll_base + PLL_CON(1),
- BITS_WITH_WMASK(1, 1, 14));
- else
- mmio_write_32(pll_base + PLL_CON(1),
- BITS_WITH_WMASK(0, 1, 14));
-}
-
static inline void pll_set_mode(uint32_t pll_id, uint32_t mode)
{
uint32_t val = BITS_WITH_WMASK(mode, 0x3, PLL_MODE_SHIFT(pll_id));
diff --git a/plat/rockchip/rk3288/drivers/pmu/pmu.c b/plat/rockchip/rk3288/drivers/pmu/pmu.c
index 085976c..9e17cff 100644
--- a/plat/rockchip/rk3288/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3288/drivers/pmu/pmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,90 +36,6 @@
ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
};
-static inline int rk3288_pmu_bus_idle(uint32_t req, uint32_t idle)
-{
- uint32_t mask = BIT(req);
- uint32_t idle_mask = 0;
- uint32_t idle_target = 0;
- uint32_t val;
- uint32_t wait_cnt = 0;
-
- switch (req) {
- case bus_ide_req_gpu:
- idle_mask = BIT(pmu_idle_ack_gpu) | BIT(pmu_idle_gpu);
- idle_target = (idle << pmu_idle_ack_gpu) |
- (idle << pmu_idle_gpu);
- break;
- case bus_ide_req_core:
- idle_mask = BIT(pmu_idle_ack_core) | BIT(pmu_idle_core);
- idle_target = (idle << pmu_idle_ack_core) |
- (idle << pmu_idle_core);
- break;
- case bus_ide_req_cpup:
- idle_mask = BIT(pmu_idle_ack_cpup) | BIT(pmu_idle_cpup);
- idle_target = (idle << pmu_idle_ack_cpup) |
- (idle << pmu_idle_cpup);
- break;
- case bus_ide_req_bus:
- idle_mask = BIT(pmu_idle_ack_bus) | BIT(pmu_idle_bus);
- idle_target = (idle << pmu_idle_ack_bus) |
- (idle << pmu_idle_bus);
- break;
- case bus_ide_req_dma:
- idle_mask = BIT(pmu_idle_ack_dma) | BIT(pmu_idle_dma);
- idle_target = (idle << pmu_idle_ack_dma) |
- (idle << pmu_idle_dma);
- break;
- case bus_ide_req_peri:
- idle_mask = BIT(pmu_idle_ack_peri) | BIT(pmu_idle_peri);
- idle_target = (idle << pmu_idle_ack_peri) |
- (idle << pmu_idle_peri);
- break;
- case bus_ide_req_video:
- idle_mask = BIT(pmu_idle_ack_video) | BIT(pmu_idle_video);
- idle_target = (idle << pmu_idle_ack_video) |
- (idle << pmu_idle_video);
- break;
- case bus_ide_req_hevc:
- idle_mask = BIT(pmu_idle_ack_hevc) | BIT(pmu_idle_hevc);
- idle_target = (idle << pmu_idle_ack_hevc) |
- (idle << pmu_idle_hevc);
- break;
- case bus_ide_req_vio:
- idle_mask = BIT(pmu_idle_ack_vio) | BIT(pmu_idle_vio);
- idle_target = (pmu_idle_ack_vio) |
- (idle << pmu_idle_vio);
- break;
- case bus_ide_req_alive:
- idle_mask = BIT(pmu_idle_ack_alive) | BIT(pmu_idle_alive);
- idle_target = (idle << pmu_idle_ack_alive) |
- (idle << pmu_idle_alive);
- break;
- default:
- ERROR("%s: Unsupported the idle request\n", __func__);
- break;
- }
-
- val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ);
- if (idle)
- val |= mask;
- else
- val &= ~mask;
-
- mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val);
-
- while ((mmio_read_32(PMU_BASE +
- PMU_BUS_IDE_ST) & idle_mask) != idle_target) {
- wait_cnt++;
- if (!(wait_cnt % MAX_WAIT_CONUT))
- WARN("%s:st=%x(%x)\n", __func__,
- mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST),
- idle_mask);
- }
-
- return 0;
-}
-
static bool rk3288_sleep_disable_osc(void)
{
static const uint32_t reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
index 3cdb7a2..49faba8 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -778,7 +778,7 @@
else if (twr_tmp <= 8)
twr_tmp = 8;
else if (twr_tmp <= 12)
- twr_tmp = twr_tmp;
+ ; /* do nothing */
else if (twr_tmp <= 14)
twr_tmp = 14;
else
diff --git a/plat/rockchip/rk3399/drivers/m0/Makefile b/plat/rockchip/rk3399/drivers/m0/Makefile
index 7913190..2bc87ae 100644
--- a/plat/rockchip/rk3399/drivers/m0/Makefile
+++ b/plat/rockchip/rk3399/drivers/m0/Makefile
@@ -5,13 +5,11 @@
#
include ../../../../../make_helpers/common.mk
+include ../../../../../make_helpers/build_macros.mk
include ../../../../../make_helpers/toolchain.mk
-# Cross Compile
-M0_CROSS_COMPILE ?= arm-none-eabi-
-
# Build architecture
-ARCH := cortex-m0
+ARCH := rk3399-m0
# Build platform
PLAT_M0 ?= rk3399m0
@@ -27,10 +25,13 @@
C_SOURCES_PMU := src/suspend.c
# Flags definition
-COMMON_FLAGS := -g -mcpu=$(ARCH) -mthumb -Wall -O3 -nostdlib -mfloat-abi=soft
+COMMON_FLAGS := -g -mcpu=cortex-m0 -mthumb -Wall -O3 -nostdlib -mfloat-abi=soft
CFLAGS := -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-common
-ASFLAGS := -Wa,--gdwarf-2
-LDFLAGS := -Wl,--gc-sections -Wl,--build-id=none
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
+CFLAGS += $(call cc_option, --param=min-pagesize=0)
+ASFLAGS := -Wa,--gdwarf-2 -Wa,--fatal-warnings
+LDFLAGS := -Wl,--gc-sections -Wl,--build-id=none -Wl,--fatal-warnings -z noexecstack
+LDFLAGS += $(call ld_option,-Xlinker --no-warn-rwx-segments)
# NOTE: The line continuation '\' is required in the next define otherwise we
# end up with a line-feed characer at the end of the last c filename.
@@ -62,7 +63,7 @@
$(OBJ) : $(2)
$(s)echo " CC $$<"
- $$(q)$(rk3399-m0-cc) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
+ $$(q)$($(ARCH)-cc) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
endef
define MAKE_S
@@ -70,7 +71,7 @@
$(OBJ) : $(2)
$(s)echo " AS $$<"
- $$(q)$(rk3399-m0-cc) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@
+ $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@
endef
define MAKE_OBJS
@@ -91,20 +92,20 @@
.DEFAULT_GOAL := all
$(LINKERFILE): $(LINKERFILE_SRC)
- $(rk3399-m0-cc) $(COMMON_FLAGS) $(INCLUDES) -P -E -D__LINKER__ -MMD -MF $@.d -MT $@ -o $@ $<
+ $(q)$($(ARCH)-cc) $(COMMON_FLAGS) $(INCLUDES) -P -E -D__LINKER__ -MMD -MF $@.d -MT $@ -o $@ $<
-include $(LINKERFILE).d
$(ELF) : $(OBJS) $(OBJS_COMMON) $(LINKERFILE)
$(s)echo " LD $@"
- $(q)$(rk3399-m0-cc) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS) $(OBJS_COMMON)
+ $(q)$($(ARCH)-ld) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS) $(OBJS_COMMON)
%.bin : %.elf
$(s)echo " BIN $@"
- $(q)$(rk3399-m0-oc) -O binary $< $@
+ $(q)$($(ARCH)-oc) -O binary $< $@
$(ELF_PMU) : $(OBJS_COMMON) $(OBJS_PMU) $(LINKERFILE)
$(s)echo " LD $@"
- $(q)$(rk3399-m0-cc) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE_PMU) -Wl,-T$(LINKERFILE) $(OBJS_PMU) $(OBJS_COMMON)
+ $(q)$($(ARCH)-ld) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE_PMU) -Wl,-T$(LINKERFILE) $(OBJS_PMU) $(OBJS_COMMON)
$(eval $(call MAKE_OBJS,$(BUILD),$(SOURCES_COMMON),$(1)))
$(eval $(call MAKE_OBJS,$(BUILD),$(SOURCES),$(1)))
diff --git a/plat/rockchip/rk3588/drivers/pmu/pmu.c b/plat/rockchip/rk3588/drivers/pmu/pmu.c
index f693dbd..a4128b2 100644
--- a/plat/rockchip/rk3588/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3588/drivers/pmu/pmu.c
@@ -760,10 +760,10 @@
"mrs x0, S3_0_C15_C2_7\n"
"orr x0, x0, #0x1\n"
"msr S3_0_C15_C2_7, x0\n"
- "wfi_loop:\n"
+ "1:\n"
"isb\n"
"wfi\n"
- "b wfi_loop\n");
+ "b 1b\n");
}
static void nonboot_cpus_off(void)