Tegra186: split MCE driver into public/private interfaces
This patch splits the MCE driver into public and private interfaces
to allow usage of common functionality across multiple SoCs.
Change-Id: Ib58080e730d72f11ff79507d8e0acffb2ad5c606
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h
new file mode 100644
index 0000000..6cc845d
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/mce.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MCE_H__
+#define __MCE_H__
+
+#include <mmio.h>
+#include <tegra_def.h>
+
+/*******************************************************************************
+ * MCE commands
+ ******************************************************************************/
+typedef enum mce_cmd {
+ MCE_CMD_ENTER_CSTATE = 0,
+ MCE_CMD_UPDATE_CSTATE_INFO = 1,
+ MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
+ MCE_CMD_READ_CSTATE_STATS = 3,
+ MCE_CMD_WRITE_CSTATE_STATS = 4,
+ MCE_CMD_IS_SC7_ALLOWED = 5,
+ MCE_CMD_ONLINE_CORE = 6,
+ MCE_CMD_CC3_CTRL = 7,
+ MCE_CMD_ECHO_DATA = 8,
+ MCE_CMD_READ_VERSIONS = 9,
+ MCE_CMD_ENUM_FEATURES = 10,
+ MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
+ MCE_CMD_ENUM_READ_MCA = 12,
+ MCE_CMD_ENUM_WRITE_MCA = 13,
+ MCE_CMD_ROC_FLUSH_CACHE = 14,
+ MCE_CMD_ROC_CLEAN_CACHE = 15,
+ MCE_CMD_ENABLE_LATIC = 16,
+ MCE_CMD_UNCORE_PERFMON_REQ = 17,
+ MCE_CMD_MISC_CCPLEX = 18,
+ MCE_CMD_IS_CCX_ALLOWED = 0xFE,
+ MCE_CMD_MAX = 0xFF,
+} mce_cmd_t;
+
+#define MCE_CMD_MASK 0xFF
+
+/*******************************************************************************
+ * Timeout value used to powerdown a core
+ ******************************************************************************/
+#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
+
+/*******************************************************************************
+ * Struct to prepare UPDATE_CSTATE_INFO request
+ ******************************************************************************/
+typedef struct mce_cstate_info {
+ /* cluster cstate value */
+ uint32_t cluster;
+ /* ccplex cstate value */
+ uint32_t ccplex;
+ /* system cstate value */
+ uint32_t system;
+ /* force system state? */
+ uint8_t system_state_force;
+ /* wake mask value */
+ uint32_t wake_mask;
+ /* update the wake mask? */
+ uint8_t update_wake_mask;
+} mce_cstate_info_t;
+
+/* public interfaces */
+int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
+ uint64_t arg2);
+int mce_update_reset_vector(void);
+int mce_update_gsc_videomem(void);
+int mce_update_gsc_tzdram(void);
+int mce_update_gsc_tzram(void);
+__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
+void mce_update_cstate_info(mce_cstate_info_t *cstate);
+void mce_verify_firmware_version(void);
+
+#endif /* __MCE_H__ */
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
similarity index 85%
rename from plat/nvidia/tegra/soc/t186/drivers/include/mce.h
rename to plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
index 441a2c1..ac4be57 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,60 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __MCE_H__
-#define __MCE_H__
+#ifndef __MCE_PRIVATE_H__
+#define __MCE_PRIVATE_H__
#include <mmio.h>
#include <tegra_def.h>
/*******************************************************************************
- * MCE commands
- ******************************************************************************/
-typedef enum mce_cmd {
- MCE_CMD_ENTER_CSTATE = 0,
- MCE_CMD_UPDATE_CSTATE_INFO = 1,
- MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
- MCE_CMD_READ_CSTATE_STATS = 3,
- MCE_CMD_WRITE_CSTATE_STATS = 4,
- MCE_CMD_IS_SC7_ALLOWED = 5,
- MCE_CMD_ONLINE_CORE = 6,
- MCE_CMD_CC3_CTRL = 7,
- MCE_CMD_ECHO_DATA = 8,
- MCE_CMD_READ_VERSIONS = 9,
- MCE_CMD_ENUM_FEATURES = 10,
- MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
- MCE_CMD_ENUM_READ_MCA = 12,
- MCE_CMD_ENUM_WRITE_MCA = 13,
- MCE_CMD_ROC_FLUSH_CACHE = 14,
- MCE_CMD_ROC_CLEAN_CACHE = 15,
- MCE_CMD_ENABLE_LATIC = 16,
- MCE_CMD_UNCORE_PERFMON_REQ = 17,
- MCE_CMD_MISC_CCPLEX = 18,
- MCE_CMD_IS_CCX_ALLOWED = 0xFE,
- MCE_CMD_MAX = 0xFF,
-} mce_cmd_t;
-
-#define MCE_CMD_MASK 0xFF
-
-/*******************************************************************************
- * Struct to prepare UPDATE_CSTATE_INFO request
- ******************************************************************************/
-typedef struct mce_cstate_info {
- /* cluster cstate value */
- uint32_t cluster;
- /* ccplex cstate value */
- uint32_t ccplex;
- /* system cstate value */
- uint32_t system;
- /* force system state? */
- uint8_t system_state_force;
- /* wake mask value */
- uint32_t wake_mask;
- /* update the wake mask? */
- uint8_t update_wake_mask;
-} mce_cstate_info_t;
-
-/*******************************************************************************
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
@@ -127,11 +80,6 @@
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
/*******************************************************************************
- * Timeout value used to powerdown a core
- ******************************************************************************/
-#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
-
-/*******************************************************************************
* MCA command struct
******************************************************************************/
typedef union mca_cmd {
@@ -353,16 +301,6 @@
uint32_t value);
} arch_mce_ops_t;
-int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
- uint64_t arg2);
-int mce_update_reset_vector(void);
-int mce_update_gsc_videomem(void);
-int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
-__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
-void mce_update_cstate_info(mce_cstate_info_t *cstate);
-void mce_verify_firmware_version(void);
-
/* declarations for ARI/NVG handler functions */
int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
@@ -399,4 +337,4 @@
int nvg_online_core(uint32_t ari_base, uint32_t core);
int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
-#endif /* __MCE_H__ */
+#endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index 7597c12..95b8c7b 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -33,7 +33,7 @@
#include <debug.h>
#include <denver.h>
#include <mmio.h>
-#include <mce.h>
+#include <mce_private.h>
#include <sys/errno.h>
#include <t18x_ari.h>
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 3a0edfb..0489f79 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -37,6 +37,7 @@
#include <debug.h>
#include <denver.h>
#include <mce.h>
+#include <mce_private.h>
#include <mmio.h>
#include <string.h>
#include <sys/errno.h>
@@ -491,7 +492,7 @@
uint32_t major, minor;
/*
- * MCE firmware is not running on simulation platforms.
+ * MCE firmware is not supported on simulation platforms.
*/
if (tegra_platform_is_emulation())
return;
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
index 25479a2..7ddafcb 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
@@ -33,7 +33,7 @@
#include <debug.h>
#include <denver.h>
#include <mmio.h>
-#include <mce.h>
+#include <mce_private.h>
#include <sys/errno.h>
#include <t18x_ari.h>