diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index 77d3af9..29fbf92 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -68,6 +68,7 @@
 
 /* SEU Commands */
 #define MBOX_CMD_SEU_ERR_READ				0x3C
+#define MBOX_CMD_SAFE_INJECT_SEU_ERR			0x41
 
 /* RSU Commands */
 #define MBOX_GET_SUBPARTITION_TABLE			0x5A
@@ -107,7 +108,7 @@
 #define MBOX_GET_MEASUREMENT				0x183
 
 /* Miscellaneous commands */
-#define MBOX_GET_ROM_PATCH_SHA384	0x1B0
+#define MBOX_GET_ROM_PATCH_SHA384			0x1B0
 
 /* Mailbox Definitions */
 
@@ -196,9 +197,9 @@
 #define RSU_VERSION_ACMF_MASK				0xff00
 
 /* Config Status Macros */
-#define CONFIG_STATUS_WORD_SIZE			16U
-#define CONFIG_STATUS_FW_VER_OFFSET		1
-#define CONFIG_STATUS_FW_VER_MASK		0x00FFFFFF
+#define CONFIG_STATUS_WORD_SIZE				16U
+#define CONFIG_STATUS_FW_VER_OFFSET			1
+#define CONFIG_STATUS_FW_VER_MASK			0x00FFFFFF
 
 /* Data structure */
 
@@ -249,5 +250,6 @@
 int mailbox_hwmon_readtemp(uint32_t chan, uint32_t *resp_buf);
 int mailbox_hwmon_readvolt(uint32_t chan, uint32_t *resp_buf);
 int mailbox_seu_err_status(uint32_t *resp_buf, uint32_t resp_buf_len);
+int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len);
 
 #endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 0668301..d45ab11 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,82 +9,82 @@
 
 
 /* SiP status response */
-#define INTEL_SIP_SMC_STATUS_OK					0
-#define INTEL_SIP_SMC_STATUS_BUSY				0x1
-#define INTEL_SIP_SMC_STATUS_REJECTED				0x2
-#define INTEL_SIP_SMC_STATUS_NO_RESPONSE			0x3
-#define INTEL_SIP_SMC_STATUS_ERROR				0x4
-#define INTEL_SIP_SMC_RSU_ERROR					0x7
-#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR		0x8
+#define INTEL_SIP_SMC_STATUS_OK						0
+#define INTEL_SIP_SMC_STATUS_BUSY					0x1
+#define INTEL_SIP_SMC_STATUS_REJECTED					0x2
+#define INTEL_SIP_SMC_STATUS_NO_RESPONSE				0x3
+#define INTEL_SIP_SMC_STATUS_ERROR					0x4
+#define INTEL_SIP_SMC_RSU_ERROR						0x7
+#define INTEL_SIP_SMC_SEU_ERR_READ_ERROR				0x8
 
 /* SiP mailbox error code */
-#define GENERIC_RESPONSE_ERROR					0x3FF
+#define GENERIC_RESPONSE_ERROR						0x3FF
 
 /* SiP V2 command code range */
-#define INTEL_SIP_SMC_CMD_MASK					0xFFFF
-#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN			0x400
-#define INTEL_SIP_SMC_CMD_V2_RANGE_END				0x4FF
+#define INTEL_SIP_SMC_CMD_MASK						0xFFFF
+#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN				0x400
+#define INTEL_SIP_SMC_CMD_V2_RANGE_END					0x4FF
 
 /* SiP V2 protocol header */
-#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK			0xF
-#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET			0U
-#define INTEL_SIP_SMC_HEADER_CID_MASK				0xF
-#define INTEL_SIP_SMC_HEADER_CID_OFFSET				4U
-#define INTEL_SIP_SMC_HEADER_VERSION_MASK			0xF
-#define INTEL_SIP_SMC_HEADER_VERSION_OFFSET			60U
+#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK				0xF
+#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET				0U
+#define INTEL_SIP_SMC_HEADER_CID_MASK					0xF
+#define INTEL_SIP_SMC_HEADER_CID_OFFSET					4U
+#define INTEL_SIP_SMC_HEADER_VERSION_MASK				0xF
+#define INTEL_SIP_SMC_HEADER_VERSION_OFFSET				60U
 
 /* SMC SiP service function identifier for version 1 */
 
 /* FPGA Reconfig */
-#define INTEL_SIP_SMC_FPGA_CONFIG_START				0xC2000001
-#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE				0x42000002
-#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE		0xC2000003
-#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE			0xC2000004
-#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM			0xC2000005
+#define INTEL_SIP_SMC_FPGA_CONFIG_START					0xC2000001
+#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE					0x42000002
+#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE			0xC2000003
+#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE				0xC2000004
+#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM				0xC2000005
 
 /* FPGA Bitstream Flag */
-#define FLAG_PARTIAL_CONFIG					BIT(0)
-#define FLAG_AUTHENTICATION					BIT(1)
-#define CONFIG_TEST_FLAG(_flag, _type)				(((flag) & FLAG_##_type) \
-								== FLAG_##_type)
+#define FLAG_PARTIAL_CONFIG						BIT(0)
+#define FLAG_AUTHENTICATION						BIT(1)
+#define CONFIG_TEST_FLAG(_flag, _type)					(((flag) & FLAG_##_type) \
+									== FLAG_##_type)
 
 /* Secure Register Access */
-#define INTEL_SIP_SMC_REG_READ				0xC2000007
-#define INTEL_SIP_SMC_REG_WRITE				0xC2000008
-#define INTEL_SIP_SMC_REG_UPDATE			0xC2000009
+#define INTEL_SIP_SMC_REG_READ						0xC2000007
+#define INTEL_SIP_SMC_REG_WRITE						0xC2000008
+#define INTEL_SIP_SMC_REG_UPDATE					0xC2000009
 
 /* Remote System Update */
-#define INTEL_SIP_SMC_RSU_STATUS				0xC200000B
-#define INTEL_SIP_SMC_RSU_UPDATE				0xC200000C
-#define INTEL_SIP_SMC_RSU_NOTIFY				0xC200000E
-#define INTEL_SIP_SMC_RSU_RETRY_COUNTER				0xC200000F
-#define INTEL_SIP_SMC_RSU_DCMF_VERSION				0xC2000010
-#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION			0xC2000011
-#define INTEL_SIP_SMC_RSU_MAX_RETRY				0xC2000012
-#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY			0xC2000013
-#define INTEL_SIP_SMC_RSU_DCMF_STATUS				0xC2000014
-#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS			0xC2000015
+#define INTEL_SIP_SMC_RSU_STATUS					0xC200000B
+#define INTEL_SIP_SMC_RSU_UPDATE					0xC200000C
+#define INTEL_SIP_SMC_RSU_NOTIFY					0xC200000E
+#define INTEL_SIP_SMC_RSU_RETRY_COUNTER					0xC200000F
+#define INTEL_SIP_SMC_RSU_DCMF_VERSION					0xC2000010
+#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION				0xC2000011
+#define INTEL_SIP_SMC_RSU_MAX_RETRY					0xC2000012
+#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY				0xC2000013
+#define INTEL_SIP_SMC_RSU_DCMF_STATUS					0xC2000014
+#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS				0xC2000015
 
 /* Hardware monitor */
-#define INTEL_SIP_SMC_HWMON_READTEMP				0xC2000020
-#define INTEL_SIP_SMC_HWMON_READVOLT				0xC2000021
-#define TEMP_CHANNEL_MAX					(1 << 15)
-#define VOLT_CHANNEL_MAX					(1 << 15)
+#define INTEL_SIP_SMC_HWMON_READTEMP					0xC2000020
+#define INTEL_SIP_SMC_HWMON_READVOLT					0xC2000021
+#define TEMP_CHANNEL_MAX						(1 << 15)
+#define VOLT_CHANNEL_MAX						(1 << 15)
 
 /* ECC */
-#define INTEL_SIP_SMC_ECC_DBE					0xC200000D
+#define INTEL_SIP_SMC_ECC_DBE						0xC200000D
 
 /* Generic Command */
-#define INTEL_SIP_SMC_SERVICE_COMPLETED				0xC200001E
-#define INTEL_SIP_SMC_FIRMWARE_VERSION				0xC200001F
-#define INTEL_SIP_SMC_HPS_SET_BRIDGES				0xC2000032
-#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384			0xC2000040
+#define INTEL_SIP_SMC_SERVICE_COMPLETED					0xC200001E
+#define INTEL_SIP_SMC_FIRMWARE_VERSION					0xC200001F
+#define INTEL_SIP_SMC_HPS_SET_BRIDGES					0xC2000032
+#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384				0xC2000040
 
-#define SERVICE_COMPLETED_MODE_ASYNC				0x00004F4E
+#define SERVICE_COMPLETED_MODE_ASYNC					0x00004F4E
 
 /* Mailbox Command */
-#define INTEL_SIP_SMC_MBOX_SEND_CMD				0xC200003C
-#define INTEL_SIP_SMC_GET_USERCODE				0xC200003D
+#define INTEL_SIP_SMC_MBOX_SEND_CMD					0xC200003C
+#define INTEL_SIP_SMC_GET_USERCODE					0xC200003D
 
 /* FPGA Crypto Services */
 #define INTEL_SIP_SMC_FCS_RANDOM_NUMBER					0xC200005A
@@ -140,21 +140,22 @@
 #define INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE				0xC200008E
 
 /* SEU ERR */
-#define INTEL_SIP_SMC_SEU_ERR_STATUS				0xC2000099
+#define INTEL_SIP_SMC_SEU_ERR_STATUS					0xC2000099
+#define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR				0xC200009A
 
-#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK				0xF
-#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK			0xF
-#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET			4U
-#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK				0xF
+#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK					0xF
+#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK				0xF
+#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET				4U
+#define INTEL_SIP_SMC_FCS_ECC_ALGO_MASK					0xF
 
 /* ECC DBE */
-#define WARM_RESET_WFI_FLAG					BIT(31)
-#define SYSMGR_ECC_DBE_COLD_RST_MASK				(SYSMGR_ECC_OCRAM_MASK |\
-								SYSMGR_ECC_DDR0_MASK |\
-								SYSMGR_ECC_DDR1_MASK)
+#define WARM_RESET_WFI_FLAG						BIT(31)
+#define SYSMGR_ECC_DBE_COLD_RST_MASK					(SYSMGR_ECC_OCRAM_MASK |\
+									SYSMGR_ECC_DDR0_MASK |\
+									SYSMGR_ECC_DDR1_MASK)
 
 /* Non-mailbox SMC Call */
-#define INTEL_SIP_SMC_SVC_VERSION				0xC2000200
+#define INTEL_SIP_SMC_SVC_VERSION					0xC2000200
 
 /**
  * SMC SiP service function identifier for version 2
@@ -162,31 +163,31 @@
  */
 
 /* V2: Non-mailbox function identifier */
-#define INTEL_SIP_SMC_V2_GET_SVC_VERSION			0xC2000400
-#define INTEL_SIP_SMC_V2_REG_READ				0xC2000401
-#define INTEL_SIP_SMC_V2_REG_WRITE				0xC2000402
-#define INTEL_SIP_SMC_V2_REG_UPDATE				0xC2000403
-#define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES			0xC2000404
-#define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR			0xC2000405
+#define INTEL_SIP_SMC_V2_GET_SVC_VERSION				0xC2000400
+#define INTEL_SIP_SMC_V2_REG_READ					0xC2000401
+#define INTEL_SIP_SMC_V2_REG_WRITE					0xC2000402
+#define INTEL_SIP_SMC_V2_REG_UPDATE					0xC2000403
+#define INTEL_SIP_SMC_V2_HPS_SET_BRIDGES				0xC2000404
+#define INTEL_SIP_SMC_V2_RSU_UPDATE_ADDR				0xC2000405
 
 /* V2: Mailbox function identifier */
-#define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND			0xC2000420
-#define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE			0xC2000421
+#define INTEL_SIP_SMC_V2_MAILBOX_SEND_COMMAND				0xC2000420
+#define INTEL_SIP_SMC_V2_MAILBOX_POLL_RESPONSE				0xC2000421
 
 /* SMC function IDs for SiP Service queries */
-#define SIP_SVC_CALL_COUNT					0x8200ff00
-#define SIP_SVC_UID						0x8200ff01
-#define SIP_SVC_VERSION						0x8200ff03
+#define SIP_SVC_CALL_COUNT						0x8200ff00
+#define SIP_SVC_UID							0x8200ff01
+#define SIP_SVC_VERSION							0x8200ff03
 
 /* SiP Service Calls version numbers */
 /*
  * Increase if there is any backward compatibility impact
  */
-#define SIP_SVC_VERSION_MAJOR					2
+#define SIP_SVC_VERSION_MAJOR						2
 /*
  * Increase if there is new SMC function ID being added
  */
-#define SIP_SVC_VERSION_MINOR					2
+#define SIP_SVC_VERSION_MINOR						2
 
 
 /* Structure Definitions */
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index d93fc8a..e2a25ea 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -696,3 +696,9 @@
 				CMD_CASUAL, resp_buf,
 				&resp_buf_len);
 }
+
+int mailbox_safe_inject_seu_err(uint32_t *arg, unsigned int len)
+{
+	return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SAFE_INJECT_SEU_ERR, arg, len,
+			CMD_CASUAL, NULL, NULL);
+}
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index c6530cf..13e49ea 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -689,15 +689,25 @@
 }
 
 /* SDM SEU Error services */
-static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz)
+static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz)
 {
-	if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) {
+	if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) {
 		return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
 	}
 
 	return INTEL_SIP_SMC_STATUS_OK;
 }
 
+/* SDM SAFE SEU Error inject services */
+static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len)
+{
+	if (mailbox_safe_inject_seu_err(command, len) < 0) {
+		return INTEL_SIP_SMC_SEU_ERR_READ_ERROR;
+	}
+
+	return INTEL_SIP_SMC_STATUS_OK;
+}
+
 /*
  * This function is responsible for handling all SiP calls from the NS world
  */
@@ -714,7 +724,8 @@
 	uint32_t retval = 0, completed_addr[3];
 	uint32_t retval2 = 0;
 	uint32_t mbox_error = 0;
-	uint64_t retval64, rsu_respbuf[9], seu_respbuf[3];
+	uint64_t retval64, rsu_respbuf[9];
+	uint32_t seu_respbuf[3];
 	int status = INTEL_SIP_SMC_STATUS_OK;
 	int mbox_status;
 	unsigned int len_in_resp;
@@ -1229,6 +1240,10 @@
 			SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]);
 		}
 
+	case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR:
+		status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
+		SMC_RET1(handle, status);
+
 	default:
 		return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
 			cookie, handle, flags);