Tegra186: Add smc handler for coresight clock gating
This change adds function to invoke for MISC_CCPLEX ARI calls and
the corresponding smc handler. This can be used to enable/disable
Coresight clock gating.
Change-Id: I4bc17aa478a46c29bfe17fd74f839a383ee2b644
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
index 66e212b..56e8afb 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
@@ -79,23 +79,24 @@
******************************************************************************/
typedef enum mce_cmd {
MCE_CMD_ENTER_CSTATE = 0,
- MCE_CMD_UPDATE_CSTATE_INFO,
- MCE_CMD_UPDATE_CROSSOVER_TIME,
- MCE_CMD_READ_CSTATE_STATS,
- MCE_CMD_WRITE_CSTATE_STATS,
- MCE_CMD_IS_SC7_ALLOWED,
- MCE_CMD_ONLINE_CORE,
- MCE_CMD_CC3_CTRL,
- MCE_CMD_ECHO_DATA,
- MCE_CMD_READ_VERSIONS,
- MCE_CMD_ENUM_FEATURES,
- MCE_CMD_ROC_FLUSH_CACHE_TRBITS,
- MCE_CMD_ENUM_READ_MCA,
- MCE_CMD_ENUM_WRITE_MCA,
- MCE_CMD_ROC_FLUSH_CACHE,
- MCE_CMD_ROC_CLEAN_CACHE,
- MCE_CMD_ENABLE_LATIC,
- MCE_CMD_UNCORE_PERFMON_REQ,
+ MCE_CMD_UPDATE_CSTATE_INFO = 1,
+ MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
+ MCE_CMD_READ_CSTATE_STATS = 3,
+ MCE_CMD_WRITE_CSTATE_STATS = 4,
+ MCE_CMD_IS_SC7_ALLOWED = 5,
+ MCE_CMD_ONLINE_CORE = 6,
+ MCE_CMD_CC3_CTRL = 7,
+ MCE_CMD_ECHO_DATA = 8,
+ MCE_CMD_READ_VERSIONS = 9,
+ MCE_CMD_ENUM_FEATURES = 10,
+ MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
+ MCE_CMD_ENUM_READ_MCA = 12,
+ MCE_CMD_ENUM_WRITE_MCA = 13,
+ MCE_CMD_ROC_FLUSH_CACHE = 14,
+ MCE_CMD_ROC_CLEAN_CACHE = 15,
+ MCE_CMD_ENABLE_LATIC = 16,
+ MCE_CMD_UNCORE_PERFMON_REQ = 17,
+ MCE_CMD_MISC_CCPLEX = 18,
MCE_CMD_IS_CCX_ALLOWED = 0xFE,
MCE_CMD_MAX = 0xFF,
} mce_cmd_t;
@@ -386,6 +387,12 @@
*/
int (*read_write_uncore_perfmon)(uint32_t ari_base,
uncore_perfmon_req_t req, uint64_t *data);
+ /*
+ * This ARI implements ARI_MISC_CCPLEX commands. This can be
+ * used to enable/disable coresight clock gating.
+ */
+ void (*misc_ccplex)(uint32_t ari_base, uint32_t index,
+ uint32_t value);
} arch_mce_ops_t;
int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
@@ -420,6 +427,7 @@
void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx);
int ari_read_write_uncore_perfmon(uint32_t ari_base,
uncore_perfmon_req_t req, uint64_t *data);
+void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value);
int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index 1168645..8d2a2b2 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -475,3 +475,22 @@
return (int)req.perfmon_status.val;
}
+
+void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
+{
+ /*
+ * This invokes the ARI_MISC_CCPLEX commands. This can be
+ * used to enable/disable coresight clock gating.
+ */
+
+ if ((index > TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) ||
+ ((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
+ (value > 1))) {
+ ERROR("%s: invalid parameters \n", __func__);
+ return;
+ }
+
+ /* clean the previous response state */
+ ari_clobber_response(ari_base);
+ (void)ari_request_wait(ari_base, 0, TEGRA_ARI_MISC_CCPLEX, index, value);
+}
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index afd4527..f953b2e 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -63,7 +63,8 @@
.read_write_mca = ari_read_write_mca,
.update_ccplex_gsc = ari_update_ccplex_gsc,
.enter_ccplex_state = ari_enter_ccplex_state,
- .read_write_uncore_perfmon = ari_read_write_uncore_perfmon
+ .read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
+ .misc_ccplex = ari_misc_ccplex
};
/* ARI functions handlers */
@@ -85,7 +86,8 @@
.read_write_mca = ari_read_write_mca,
.update_ccplex_gsc = ari_update_ccplex_gsc,
.enter_ccplex_state = ari_enter_ccplex_state,
- .read_write_uncore_perfmon = ari_read_write_uncore_perfmon
+ .read_write_uncore_perfmon = ari_read_write_uncore_perfmon,
+ .misc_ccplex = ari_misc_ccplex
};
typedef struct mce_config {
@@ -385,6 +387,11 @@
write_ctx_reg(gp_regs, CTX_GPREG_X1, arg1);
break;
+ case MCE_CMD_MISC_CCPLEX:
+ ops->misc_ccplex(cpu_ari_base, arg0, arg1);
+
+ break;
+
default:
ERROR("unknown MCE command (%d)\n", cmd);
return EINVAL;
diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index 8e33718..31e903e 100644
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -66,6 +66,7 @@
#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0x82FFFF0F
#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0x82FFFF10
#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0x82FFFF11
+#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0x82FFFF12
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls
@@ -104,6 +105,7 @@
case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
+ case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
/* clean up the high bits */
smc_fid &= MCE_CMD_MASK;