fix(layerscape): unlock write access SMMU_CBn_ACTLR
This patch is to fix Errata #841119 and #826419 failed apply in linux
because of SMMU_CBn_ACTLR register can't be modified in non-secure
states.
Signed-off-by: Howard Lu <howard.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2b23e7c8baa809f385917eb45b10ec6b26a9ada8
diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h
index d64c33b..bc17703 100644
--- a/include/drivers/nxp/smmu/nxp_smmu.h
+++ b/include/drivers/nxp/smmu/nxp_smmu.h
@@ -10,10 +10,13 @@
#define SMMU_SCR0 (0x0)
#define SMMU_NSCR0 (0x400)
+#define SMMU_SACR (0x10)
#define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400
+#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
+
static inline void bypass_smmu(uintptr_t smmu_base_addr)
{
uint32_t val;
@@ -27,4 +30,13 @@
mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
}
+static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
+{
+ uint32_t val;
+
+ val = mmio_read_32((smmu_base_addr + SMMU_SACR));
+ val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
+ mmio_write_32((smmu_base_addr + SMMU_SACR), val);
+}
+
#endif
diff --git a/plat/nxp/soc-ls1043a/soc.c b/plat/nxp/soc-ls1043a/soc.c
index 7badf8c..3e821d0 100644
--- a/plat/nxp/soc-ls1043a/soc.c
+++ b/plat/nxp/soc-ls1043a/soc.c
@@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -174,6 +172,12 @@
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-ls1043a/soc.mk b/plat/nxp/soc-ls1043a/soc.mk
index b6ce14e..0ebb377 100644
--- a/plat/nxp/soc-ls1043a/soc.mk
+++ b/plat/nxp/soc-ls1043a/soc.mk
@@ -19,8 +19,8 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes
diff --git a/plat/nxp/soc-ls1046a/soc.c b/plat/nxp/soc-ls1046a/soc.c
index d17e672..6dfea89 100644
--- a/plat/nxp/soc-ls1046a/soc.c
+++ b/plat/nxp/soc-ls1046a/soc.c
@@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -168,6 +166,12 @@
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters);
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-ls1046a/soc.mk b/plat/nxp/soc-ls1046a/soc.mk
index 8207dcd..7644027 100644
--- a/plat/nxp/soc-ls1046a/soc.mk
+++ b/plat/nxp/soc-ls1046a/soc.mk
@@ -19,8 +19,8 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes
diff --git a/plat/nxp/soc-ls1088a/soc.c b/plat/nxp/soc-ls1088a/soc.c
index 5f9f313..02d62ea 100644
--- a/plat/nxp/soc-ls1088a/soc.c
+++ b/plat/nxp/soc-ls1088a/soc.c
@@ -17,9 +17,7 @@
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <ls_interconnect.h>
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -254,6 +252,12 @@
MT_DEVICE | MT_RW | MT_NS);
}
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-ls1088a/soc.mk b/plat/nxp/soc-ls1088a/soc.mk
index 83ac9d0..6e39461 100644
--- a/plat/nxp/soc-ls1088a/soc.mk
+++ b/plat/nxp/soc-ls1088a/soc.mk
@@ -23,12 +23,12 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
-$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to
diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c
index df31393..427189d 100644
--- a/plat/nxp/soc-lx2160a/soc.c
+++ b/plat/nxp/soc-lx2160a/soc.c
@@ -23,9 +23,7 @@
#ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h>
#endif
-#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h>
-#endif
#include <nxp_timer.h>
#include <plat_console.h>
#include <plat_gic.h>
@@ -286,6 +284,12 @@
sfp_init(NXP_SFP_ADDR);
#endif
+ /*
+ * Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
+ */
+ smmu_cache_unlock(NXP_SMMU_ADDR);
+ INFO("SMMU Cache Unlocking is Configured.\n");
+
#if TRUSTED_BOARD_BOOT
uint32_t mode;
diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
index 75a3af2..239442c 100644
--- a/plat/nxp/soc-lx2160a/soc.mk
+++ b/plat/nxp/soc-lx2160a/soc.mk
@@ -36,12 +36,12 @@
# For Security Features
DISABLE_FUSE_WRITE := 1
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image
SAVE_KEYS=1
endif
-$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to