rockchip: add M0 source code and build system for RK3399
This CL supports add M0 source code to built into the bl31.bin, the
goal is that we can load the M0 code binary into SRAM and execute it.
We need the M0 help us to clean the power_mode_en bit during the AP
PMU enter the state machine with interrupt, and avoid to the AP can
not exit the loop forever.
Change-Id: I844582c54a1f0d44ca41290d44618df58679f341
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index d2213e9..604de9c 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -76,6 +76,7 @@
${RK_PLAT_SOC}/plat_sip_calls.c \
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
+ ${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \
${RK_PLAT_SOC}/drivers/pwm/pwm.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/dram/dram.c \
@@ -84,3 +85,19 @@
ENABLE_PLAT_COMPAT := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
+
+# M0 source build
+PLAT_M0 := ${PLAT}m0
+
+RK3399M0FW=${BUILD_PLAT}/m0/bin/${PLAT_M0}.bin
+$(eval $(call add_define,RK3399M0FW))
+
+# CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin
+export CCACHE_EXTRAFILES
+${BUILD_PLAT}/bl31/pmu_fw.o: CCACHE_EXTRAFILES=$(RK3399M0FW)
+${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c: $(RK3399M0FW)
+
+.PHONY: $(RK3399M0FW)
+$(RK3399M0FW):
+ $(MAKE) -C ${RK_PLAT_SOC}/drivers/m0 \
+ BUILD_PLAT=$(abspath ${BUILD_PLAT}/m0)