Merge changes from topic "xlnx_smcc_soc_id" into integration
* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid
diff --git a/Makefile b/Makefile
index 2c5748f..98f47a7 100644
--- a/Makefile
+++ b/Makefile
@@ -152,7 +152,7 @@
ARM_ARCH_MINOR := 5
ENABLE_FEAT_ECV = 1
ENABLE_FEAT_FGT = 1
-
+CTX_INCLUDE_PAUTH_REGS := 1
# RME enables CSV2_2 extension by default.
ENABLE_FEAT_CSV2_2 = 1
diff --git a/docs/components/rmm-el3-comms-spec.rst b/docs/components/rmm-el3-comms-spec.rst
index 6b57c0e..009ac28 100644
--- a/docs/components/rmm-el3-comms-spec.rst
+++ b/docs/components/rmm-el3-comms-spec.rst
@@ -52,7 +52,7 @@
- ``RES0``: Bit 31 of the version number is reserved 0 as to maintain
consistency with the versioning schemes used in other parts of RMM.
-This document specifies the 0.1 version of Boot Interface ABI and RMM-EL3
+This document specifies the 0.2 version of Boot Interface ABI and RMM-EL3
services specification and the 0.2 version of the Boot Manifest.
.. _rmm_el3_boot_interface:
@@ -503,6 +503,10 @@
and it is the responsibility of RMM to preserve this or use this as a return argument.
EL3 will always copy x0-x4 from Realm context to NS Context.
+EL3 must save and restore the following as part of world switch:
+ #. EL2 system registers with the exception of ``zcr_el2`` register.
+ #. PAuth key registers (APIA, APIB, APDA, APDB, APGA).
+
EL3 will not save some registers as mentioned in the below list. It is the
responsibility of RMM to ensure that these are appropriately saved if the
Realm World makes use of them:
@@ -510,10 +514,11 @@
#. FP/SIMD registers
#. SVE registers
#. SME registers
- #. EL1/0 registers
+ #. EL1/0 registers with the exception of PAuth key registers as mentioned above.
+ #. zcr_el2 register.
-It is the responsibility of EL3 that any other registers other than the ones mentioned above
-will not be leaked to the NS Host and to maintain the confidentiality of the Realm World.
+It is essential that EL3 honors this contract to maintain the Confidentiality and integrity
+of the Realm world.
SMCCC v1.3 allows NS world to specify whether SVE context is in use. In this
case, RMM could choose to not save the incoming SVE context but must ensure
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index de7181c..55d778e 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -152,7 +152,7 @@
* Increase this when a bug is fixed, or a feature is added without
* breaking compatibility.
*/
-#define RMM_EL3_IFC_VERSION_MINOR (U(1))
+#define RMM_EL3_IFC_VERSION_MINOR (U(2))
#define RMM_EL3_INTERFACE_VERSION \
(((RMM_EL3_IFC_VERSION_MAJOR << 16) & 0x7FFFF) | \
diff --git a/plat/brcm/board/stingray/include/scp_cmd.h b/plat/brcm/board/stingray/include/scp_cmd.h
index 806ef56..a7ab0e5 100644
--- a/plat/brcm/board/stingray/include/scp_cmd.h
+++ b/plat/brcm/board/stingray/include/scp_cmd.h
@@ -5,7 +5,7 @@
*/
#ifndef SCP_CMD_H
-#define SCP_SMD_H
+#define SCP_CMD_H
#include <stdint.h>
diff --git a/plat/xilinx/versal/include/plat_ipi.h b/plat/xilinx/versal/include/plat_ipi.h
index 9143dc6..e4922e4 100644
--- a/plat/xilinx/versal/include/plat_ipi.h
+++ b/plat/xilinx/versal/include/plat_ipi.h
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,16 +29,14 @@
********************************************************************/
#define IPI_BUFFER_BASEADDR 0xFF3F0000U
-#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
-#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U)
+#define IPI_LOCAL_ID IPI_ID_APU
+#define IPI_REMOTE_ID IPI_ID_PMC
-#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
-#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U
+#define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
+#define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
-#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE
-
-#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET
-#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET
+#define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U)
+#define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U)
#define IPI_BUFFER_MAX_WORDS 8
@@ -51,4 +50,20 @@
/* Configure IPI table for versal */
void versal_ipi_config_table_init(void);
+/* IPI registers and bitfields */
+#define PMC_REG_BASE U(0xFF320000)
+#define PMC_IPI_TRIG_BIT (1U << 1U)
+#define IPI0_REG_BASE U(0xFF330000)
+#define IPI0_TRIG_BIT (1U << 2U)
+#define IPI1_REG_BASE U(0xFF340000)
+#define IPI1_TRIG_BIT (1U << 3U)
+#define IPI2_REG_BASE U(0xFF350000)
+#define IPI2_TRIG_BIT (1U << 4U)
+#define IPI3_REG_BASE U(0xFF360000)
+#define IPI3_TRIG_BIT (1U << 5U)
+#define IPI4_REG_BASE U(0xFF370000)
+#define IPI4_TRIG_BIT (1U << 5U)
+#define IPI5_REG_BASE U(0xFF380000)
+#define IPI5_TRIG_BIT (1U << 6U)
+
#endif /* PLAT_IPI_H */
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 34b43bb..a8cf0df 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -129,20 +129,4 @@
#define PMC_GLOBAL_BASE 0xF1110000U
#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
-/* IPI registers and bitfields */
-#define PMC_REG_BASE U(0xFF320000)
-#define PMC_IPI_TRIG_BIT (1U << 1U)
-#define IPI0_REG_BASE U(0xFF330000)
-#define IPI0_TRIG_BIT (1U << 2U)
-#define IPI1_REG_BASE U(0xFF340000)
-#define IPI1_TRIG_BIT (1U << 3U)
-#define IPI2_REG_BASE U(0xFF350000)
-#define IPI2_TRIG_BIT (1U << 4U)
-#define IPI3_REG_BASE U(0xFF360000)
-#define IPI3_TRIG_BIT (1U << 5U)
-#define IPI4_REG_BASE U(0xFF370000)
-#define IPI4_TRIG_BIT (1U << 5U)
-#define IPI5_REG_BASE U(0xFF380000)
-#define IPI5_TRIG_BIT (1U << 6U)
-
#endif /* VERSAL_DEF_H */
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index ecec405..81a5445 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -29,9 +29,9 @@
DEFINE_BAKERY_LOCK(pm_client_secure_lock);
static const struct pm_ipi apu_ipi = {
- .local_ipi_id = IPI_ID_APU,
- .remote_ipi_id = IPI_ID_PMC,
- .buffer_base = IPI_BUFFER_APU_BASE,
+ .local_ipi_id = IPI_LOCAL_ID,
+ .remote_ipi_id = IPI_REMOTE_ID,
+ .buffer_base = IPI_BUFFER_LOCAL_BASE,
};
/* Order in pm_procs_all array must match cpu ids */
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index 67915f4..51eb759 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -1,5 +1,6 @@
/*
- * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,15 +9,9 @@
* Versal IPI agent registers access management
*/
-#include <errno.h>
+#include <lib/utils_def.h>
#include <ipi.h>
#include <plat_ipi.h>
-#include <plat_private.h>
-#include <string.h>
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
/* versal ipi configuration table */
static const struct ipi_config versal_ipi_table[] = {
diff --git a/plat/xilinx/versal_net/include/plat_ipi.h b/plat/xilinx/versal_net/include/plat_ipi.h
index 30c51b5..9f9947e 100644
--- a/plat/xilinx/versal_net/include/plat_ipi.h
+++ b/plat/xilinx/versal_net/include/plat_ipi.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,16 +31,14 @@
********************************************************************/
#define IPI_BUFFER_BASEADDR (0xEB3F0000U)
-#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
-#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U)
+#define IPI_LOCAL_ID IPI_ID_APU
+#define IPI_REMOTE_ID IPI_ID_PMC
-#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
-#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U
+#define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
+#define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
-#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMC_BASE
-
-#define IPI_BUFFER_TARGET_LOCAL_OFFSET IPI_BUFFER_TARGET_APU_OFFSET
-#define IPI_BUFFER_TARGET_REMOTE_OFFSET IPI_BUFFER_TARGET_PMC_OFFSET
+#define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U)
+#define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U)
#define IPI_BUFFER_MAX_WORDS 8
@@ -54,4 +52,21 @@
/* Configure IPI table for versal_net */
void versal_net_ipi_config_table_init(void);
+/*******************************************************************************
+ * IPI registers and bitfields
+ ******************************************************************************/
+#define IPI0_REG_BASE (0xEB330000U)
+#define IPI0_TRIG_BIT (1 << 2)
+#define PMC_IPI_TRIG_BIT (1 << 1)
+#define IPI1_REG_BASE (0xEB340000U)
+#define IPI1_TRIG_BIT (1 << 3)
+#define IPI2_REG_BASE (0xEB350000U)
+#define IPI2_TRIG_BIT (1 << 4)
+#define IPI3_REG_BASE (0xEB360000U)
+#define IPI3_TRIG_BIT (1 << 5)
+#define IPI4_REG_BASE (0xEB370000U)
+#define IPI4_TRIG_BIT (1 << 6)
+#define IPI5_REG_BASE (0xEB380000U)
+#define IPI5_TRIG_BIT (1 << 7)
+
#endif /* PLAT_IPI_H */
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index e650637..758882c 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -148,23 +148,6 @@
#define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK
#define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE
-/*******************************************************************************
- * IPI registers and bitfields
- ******************************************************************************/
-#define IPI0_REG_BASE (0xEB330000U)
-#define IPI0_TRIG_BIT (1 << 2)
-#define PMC_IPI_TRIG_BIT (1 << 1)
-#define IPI1_REG_BASE (0xEB340000U)
-#define IPI1_TRIG_BIT (1 << 3)
-#define IPI2_REG_BASE (0xEB350000U)
-#define IPI2_TRIG_BIT (1 << 4)
-#define IPI3_REG_BASE (0xEB360000U)
-#define IPI3_TRIG_BIT (1 << 5)
-#define IPI4_REG_BASE (0xEB370000U)
-#define IPI4_TRIG_BIT (1 << 6)
-#define IPI5_REG_BASE (0xEB380000U)
-#define IPI5_TRIG_BIT (1 << 7)
-
/* Processor core device IDs */
#define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU)
#define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U)
diff --git a/plat/xilinx/versal_net/platform.mk b/plat/xilinx/versal_net/platform.mk
index da83c3a..398ef85 100644
--- a/plat/xilinx/versal_net/platform.mk
+++ b/plat/xilinx/versal_net/platform.mk
@@ -17,6 +17,7 @@
SEPARATE_CODE_AND_RODATA := 1
override RESET_TO_BL31 := 1
PL011_GENERIC_UART := 1
+IPI_CRC_CHECK := 0
GIC_ENABLE_V4_EXTN := 0
GICV3_SUPPORT_GIC600 := 1
TFA_NO_PM := 0
@@ -49,6 +50,10 @@
$(eval $(call add_define,VERSAL_NET_BL32_MEM_SIZE))
endif
+ifdef IPI_CRC_CHECK
+ $(eval $(call add_define,IPI_CRC_CHECK))
+endif
+
USE_COHERENT_MEM := 0
HW_ASSISTED_COHERENCY := 1
diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c
index 2741d47..3387891 100644
--- a/plat/xilinx/versal_net/pm_service/pm_client.c
+++ b/plat/xilinx/versal_net/pm_service/pm_client.c
@@ -60,9 +60,9 @@
#endif
static const struct pm_ipi apu_ipi = {
- .local_ipi_id = IPI_ID_APU,
- .remote_ipi_id = IPI_ID_PMC,
- .buffer_base = IPI_BUFFER_APU_BASE,
+ .local_ipi_id = IPI_LOCAL_ID,
+ .remote_ipi_id = IPI_REMOTE_ID,
+ .buffer_base = IPI_BUFFER_LOCAL_BASE,
};
/* Order in pm_procs_all array must match cpu ids */
diff --git a/plat/xilinx/versal_net/versal_net_ipi.c b/plat/xilinx/versal_net/versal_net_ipi.c
index cf897e3..ed3f2bb 100644
--- a/plat/xilinx/versal_net/versal_net_ipi.c
+++ b/plat/xilinx/versal_net/versal_net_ipi.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,17 +9,9 @@
* Versal NET IPI agent registers access management
*/
-#include <errno.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
-
+#include <lib/utils_def.h>
#include <ipi.h>
#include <plat_ipi.h>
-#include <plat_private.h>
/* versal_net ipi configuration table */
static const struct ipi_config versal_net_ipi_table[IPI_ID_MAX] = {
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index 8d83c3e..18ccafd 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -60,11 +60,11 @@
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
static const struct {
- uint32_t id;
- uint32_t ver;
- char *name;
+ uint8_t id;
bool evexists;
-} zynqmp_devices[] = {
+ uint16_t ver;
+ char *name;
+} __packed zynqmp_devices[] = {
{
.id = 0x10,
.name = "XCZU3EG",
diff --git a/plat/xilinx/zynqmp/include/plat_ipi.h b/plat/xilinx/zynqmp/include/plat_ipi.h
index dc39d32..4007b91 100644
--- a/plat/xilinx/zynqmp/include/plat_ipi.h
+++ b/plat/xilinx/zynqmp/include/plat_ipi.h
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,10 +34,11 @@
********************************************************************/
#define IPI_BUFFER_BASEADDR 0xFF990000U
-#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
-#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
+#define IPI_LOCAL_ID IPI_ID_APU
+#define IPI_REMOTE_ID IPI_ID_PMU0
-#define IPI_BUFFER_REMOTE_BASE IPI_BUFFER_PMU_BASE
+#define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + 0x400U)
+#define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + 0xE00U)
#define IPI_BUFFER_TARGET_LOCAL_OFFSET 0x80U
#define IPI_BUFFER_TARGET_REMOTE_OFFSET 0x1C0U
diff --git a/plat/xilinx/zynqmp/pm_service/pm_client.c b/plat/xilinx/zynqmp/pm_service/pm_client.c
index 2c7834d..853e9e1 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_client.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_client.c
@@ -35,12 +35,10 @@
DEFINE_BAKERY_LOCK(pm_client_secure_lock);
-extern const struct pm_ipi apu_ipi;
-
-const struct pm_ipi apu_ipi = {
- .local_ipi_id = IPI_ID_APU,
- .remote_ipi_id = IPI_ID_PMU0,
- .buffer_base = IPI_BUFFER_APU_BASE,
+static const struct pm_ipi apu_ipi = {
+ .local_ipi_id = IPI_LOCAL_ID,
+ .remote_ipi_id = IPI_REMOTE_ID,
+ .buffer_base = IPI_BUFFER_LOCAL_BASE,
};
static uint32_t suspend_mode = PM_SUSPEND_MODE_STD;
diff --git a/plat/xilinx/zynqmp/zynqmp_ipi.c b/plat/xilinx/zynqmp/zynqmp_ipi.c
index b14e3fd..c7d2c08 100644
--- a/plat/xilinx/zynqmp/zynqmp_ipi.c
+++ b/plat/xilinx/zynqmp/zynqmp_ipi.c
@@ -1,5 +1,7 @@
/*
* Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,17 +10,9 @@
* Zynq UltraScale+ MPSoC IPI agent registers access management
*/
-#include <errno.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <common/runtime_svc.h>
-#include <lib/bakery_lock.h>
-#include <lib/mmio.h>
-
+#include <lib/utils_def.h>
#include <ipi.h>
#include <plat_ipi.h>
-#include <plat_private.h>
/* Zynqmp ipi configuration table */
static const struct ipi_config zynqmp_ipi_table[] = {