fix(intel): update HPS bridges for Agilex5 SoC FPGA
This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC
Change-Id: Ia539ff289e83303ae3b4d78b9ac1d50c9f9558da
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/common/include/socfpga_reset_manager.h b/plat/intel/soc/common/include/socfpga_reset_manager.h
index 9d06a3d..93cc945 100644
--- a/plat/intel/soc/common/include/socfpga_reset_manager.h
+++ b/plat/intel/soc/common/include/socfpga_reset_manager.h
@@ -155,6 +155,8 @@
#define RSTMGR_HDSKACK_F2SDRAM0ACK 0x00000800
#define RSTMGR_HDSKACK_FPGA2SOCACK 0x00001000
#define RSTMGR_HDSKACK_FPGAHSACK_DASRT 0x00000000
+#define RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT 0x00000000
+#define RSTMGR_HDSKACK_SOC2FPGAACK_DASRT 0x00000000
#define RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT 0x00000000
#define RSTMGR_HDSKACK_FPGA2SOCACK_DASRT 0x00000000