Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into integration
* changes:
feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked
feat(plat/rcar3): add a DRAM size setting for M3N
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0
feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB
feat(drivers/rcar3): ddr: add function to judge a DDR rank
fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N
fix(drivers/rcar3): i2c_dvfs: fix I2C operation
fix(drivers/rcar3): fix CPG registers redefinition
fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition
fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0
refactor(plat/rcar3): factor out DT memory node generation
feat(plat/rcar3): add optional support for gzip-compressed BL33
diff --git a/drivers/renesas/common/common.c b/drivers/renesas/common/common.c
index 9b7c1eb..a0aa480 100644
--- a/drivers/renesas/common/common.c
+++ b/drivers/renesas/common/common.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
+#include "cpg_registers.h"
#include "rcar_private.h"
#if IMAGE_BL31
@@ -16,7 +17,7 @@
{
uint32_t value = regval;
- mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
+ mmio_write_32(CPG_CPGWPR, ~value);
mmio_write_32(regadr, value);
}
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
index aa3bc24..8d002de 100644
--- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
@@ -4147,7 +4147,13 @@
}
/* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
- data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
+ data_l = mmio_read_32(THS1_THCTR);
+ if (data_l & 0x00000040U) {
+ data_l = data_l & 0xFFFFFFBEU;
+ } else {
+ data_l = data_l | BIT(1);
+ }
+
mmio_write_32(THS1_THCTR, data_l);
/* Judge product and cut */
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
index 45b6b08..bbb0200 100644
--- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
@@ -12,6 +12,9 @@
#if (RZG_SOC == 1)
#define BOARDNUM 4
#else
+
+#include <board.h>
+
#define BOARDNUM 22
#endif /* RZG_SOC == 1 */
#define BOARD_JUDGE_AUTO
@@ -1967,6 +1970,44 @@
}
#endif /* RZG_SOC == 1 */
+#if (RZG_SOC == 0) && (RCAR_DRAM_LPDDR4_MEMCONF != 0)
+static uint32_t ddr_rank_judge(void)
+{
+ uint32_t brd;
+
+#if (RCAR_DRAM_MEMRANK == 0)
+ int32_t ret;
+ uint32_t type = 0U;
+ uint32_t rev = 0U;
+
+ brd = 99U;
+ ret = rcar_get_board_type(&type, &rev);
+ if ((ret == 0) && (rev != 0xFFU)) {
+ if (type == (uint32_t)BOARD_SALVATOR_XS) {
+ if (rev == 0x11U) {
+ brd = 14U;
+ } else {
+ brd = 8U;
+ }
+ } else if (type == (uint32_t)BOARD_STARTER_KIT_PRE) {
+ if (rev == 0x21U) {
+ brd = 14U;
+ } else {
+ brd = 8U;
+ }
+ }
+ }
+#elif (RCAR_DRAM_MEMRANK == 1)
+ brd = 14U;
+#elif (RCAR_DRAM_MEMRANK == 2)
+ brd = 8U;
+#else
+#error Invalid value was set to RCAR_DRAM_MEMRANK
+#endif /* (RCAR_DRAM_MEMRANK == 0) */
+ return brd;
+}
+#endif /* (RCAR_DRAM_LPDDR4_MEMCONF != 0) */
+
static uint32_t _board_judge(void)
{
uint32_t brd;
@@ -1985,7 +2026,7 @@
#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
brd = 7;
#else
- brd = 8;
+ brd = ddr_rank_judge();
#endif
}
} else if (prr_product == PRR_PRODUCT_M3) {
@@ -2039,7 +2080,7 @@
#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
brd = 7;
#else
- brd = 8;
+ brd = ddr_rank_judge();
#endif
}
} else if (prr_product == PRR_PRODUCT_M3N) {
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
index 56363eb..3cb1975 100644
--- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#define RCAR_DDR_VERSION "rev.0.40"
+#define RCAR_DDR_VERSION "rev.0.41"
#define DRAM_CH_CNT 0x04
#define SLICE_CNT 0x04
#define CS_CNT 0x02
diff --git a/drivers/renesas/common/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c
index 354aa3c..c0ec600 100644
--- a/drivers/renesas/common/emmc/emmc_init.c
+++ b/drivers/renesas/common/emmc/emmc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include "emmc_registers.h"
#include "emmc_def.h"
#include "rcar_private.h"
+#include "cpg_registers.h"
st_mmc_base mmc_drv_obj;
@@ -87,11 +88,11 @@
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */
- dataL = mmio_read_32(CPG_SMSTPCR3);
+ dataL = mmio_read_32(SMSTPCR3);
if ((dataL & CPG_MSTP_MMC) == 0U) {
dataL |= (CPG_MSTP_MMC);
mmio_write_32(CPG_CPGWPR, (~dataL));
- mmio_write_32(CPG_SMSTPCR3, dataL);
+ mmio_write_32(SMSTPCR3, dataL);
}
return result;
@@ -100,7 +101,7 @@
static EMMC_ERROR_CODE emmc_dev_init(void)
{
/* Enable clock supply to eMMC. */
- mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
+ mstpcr_write(SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
/* Set SD clock */
mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */
diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
index 7fae5e4..67d285d 100644
--- a/drivers/renesas/common/emmc/emmc_registers.h
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -50,19 +50,6 @@
#define BIT30 (0x40000000U)
#define BIT31 (0x80000000U)
-/* Clock Pulse Generator (CPG) registers */
-#define CPG_BASE (0xE6150000U)
-/* Module stop status register 3 */
-#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
-/* System module stop control register 3 */
-#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
-/* SDHI2 clock frequency control register */
-#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
-/* SDHI3 clock frequency control register */
-#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
-/* CPG Write Protect Register */
-#define CPG_CPGWPR (CPG_BASE + 0x0900U)
-
#if USE_MMC_CH == MMC_CH0
#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
#else /* USE_MMC_CH == MMC_CH0 */
diff --git a/drivers/renesas/common/iic_dvfs/iic_dvfs.c b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
index e1c9a5b..bf80697 100644
--- a/drivers/renesas/common/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
@@ -517,7 +517,7 @@
uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 1U);
again:
switch (state) {
case DVFS_START:
@@ -557,7 +557,7 @@
uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 1U);
again:
switch (state) {
case DVFS_START:
diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c
index c0f015f..3f60fe6 100644
--- a/drivers/renesas/common/pwrc/pwrc.c
+++ b/drivers/renesas/common/pwrc/pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +20,7 @@
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
+#include "cpg_registers.h"
/*
* Someday there will be a generic power controller api. At the moment each
@@ -238,7 +239,7 @@
scu_power_up(mpidr);
cpu = mpidr & MPIDR_CPU_MASK;
on_data = 1 << cpu;
- mmio_write_32(RCAR_CPGWPR, ~on_data);
+ mmio_write_32(CPG_CPGWPR, ~on_data);
mmio_write_32(on_reg, on_data);
mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
@@ -260,7 +261,7 @@
if (read_mpidr_el1() != mpidr)
panic();
- mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
+ mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF);
mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
rcar_lock_release();
diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c
index cd194ff..dbbaed6 100644
--- a/drivers/renesas/rcar/board/board.c
+++ b/drivers/renesas/rcar/board/board.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -30,9 +30,9 @@
#define BOARD_CODE_SHIFT (0x03)
#define BOARD_ID_UNKNOWN (0xFF)
-#define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SXS_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
-#define SKP_ID { 0x10U, 0x10U, 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SKP_ID { 0x10U, 0x10U, 0x20U, 0x21U, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SK_ID { 0x10U, 0x30U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
diff --git a/plat/renesas/common/include/platform_def.h b/plat/renesas/common/include/platform_def.h
index 7378714..72c7688 100644
--- a/plat/renesas/common/include/platform_def.h
+++ b/plat/renesas/common/include/platform_def.h
@@ -151,7 +151,8 @@
* BL33
******************************************************************************/
#define BL33_BASE DRAM1_NS_BASE
-
+#define BL33_COMP_SIZE U(0x200000)
+#define BL33_COMP_BASE (BL33_BASE - BL33_COMP_SIZE)
/*******************************************************************************
* Platform specific page table and MMU setup constants
diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h
index 6c5b295..93a65f1 100644
--- a/plat/renesas/common/include/rcar_def.h
+++ b/plat/renesas/common/include/rcar_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -120,7 +120,6 @@
/* Timer control */
#define RCAR_CNTC_BASE U(0xE6080000)
/* Reset */
-#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
diff --git a/plat/renesas/common/include/rcar_version.h b/plat/renesas/common/include/rcar_version.h
index 67cbd71..173111d 100644
--- a/plat/renesas/common/include/rcar_version.h
+++ b/plat/renesas/common/include/rcar_version.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,7 @@
#include <arch_helpers.h>
-#define VERSION_OF_RENESAS "2.0.6"
+#define VERSION_OF_RENESAS "3.0.0"
#define VERSION_OF_RENESAS_MAXLEN 128
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
diff --git a/plat/renesas/common/include/registers/cpg_registers.h b/plat/renesas/common/include/registers/cpg_registers.h
index 0d698d9..5d2bb9e 100644
--- a/plat/renesas/common/include/registers/cpg_registers.h
+++ b/plat/renesas/common/include/registers/cpg_registers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +16,8 @@
#define CPG_SRCR2 (CPG_BASE + 0x00B0U)
/* CPG module stop status 2 */
#define CPG_MSTPSR2 (CPG_BASE + 0x0040U)
+/* CPG module stop status 2 */
+#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
/* CPG write protect */
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
/* CPG write protect control */
@@ -24,6 +26,10 @@
#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U)
/* CPG module stop status 9 */
#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U)
+/* SDHI2 clock frequency control register */
+#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
+/* SDHI3 clock frequency control register */
+#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
/* CPG (SECURITY) registers */
diff --git a/plat/renesas/common/rcar_common.c b/plat/renesas/common/rcar_common.c
index dec7229..95e1f61 100644
--- a/plat/renesas/common/rcar_common.c
+++ b/plat/renesas/common/rcar_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2019-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,9 +12,8 @@
#include <plat/common/platform.h>
#include <lib/mmio.h>
+#include <cpg_registers.h>
-#define CPG_BASE 0xE6150000
-#define CPG_MSTPSR3 0x0048
#define MSTP318 (1 << 18)
#define MSTP319 (1 << 19)
#define PMSR 0x5c
@@ -31,7 +30,7 @@
int ret = 0;
/* Test if PCIECx is enabled */
- cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3);
+ cpg = mmio_read_32(CPG_MSTPSR3);
if (cpg & (MSTP318 << !controller))
return ret;
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index add2a4f..41b2d11 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -15,12 +15,16 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
+#include <common/image_decompress.h>
#include <drivers/console.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/common/platform.h>
+#if RCAR_GEN3_BL33_GZIP == 1
+#include <tf_gunzip.h>
+#endif
#include "avs_driver.h"
#include "boot_init_dram.h"
@@ -357,16 +361,29 @@
#endif
}
+#if RCAR_GEN3_BL33_GZIP == 1
+void bl2_plat_preload_setup(void)
+{
+ image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
+}
+#endif
+
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
bl_mem_params_node_t *bl_mem_params;
+ bl_mem_params = get_bl_mem_params_node(image_id);
+
+#if RCAR_GEN3_BL33_GZIP == 1
+ if (image_id == BL33_IMAGE_ID) {
+ image_decompress_prepare(&bl_mem_params->image_info);
+ }
+#endif
+
if (image_id != BL31_IMAGE_ID)
return 0;
- bl_mem_params = get_bl_mem_params_node(image_id);
-
if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
goto cold_boot;
@@ -433,6 +450,19 @@
sizeof(entry_point_info_t));
break;
case BL33_IMAGE_ID:
+#if RCAR_GEN3_BL33_GZIP == 1
+ if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
+ /* decompress gzip-compressed image */
+ ret = image_decompress(&bl_mem_params->image_info);
+ if (ret != 0) {
+ return ret;
+ }
+ } else {
+ /* plain image, copy it in place */
+ memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
+ bl_mem_params->image_info.image_size);
+ }
+#endif
memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
sizeof(entry_point_info_t));
break;
@@ -535,12 +565,75 @@
}
}
-static void bl2_advertise_dram_entries(uint64_t dram_config[8])
+static void bl2_add_rpc_node(void)
+{
+#if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
+ int ret, node;
+
+ node = ret = fdt_add_subnode(fdt, 0, "soc");
+ if (ret < 0) {
+ goto err;
+ }
+
+ node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000");
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_string(fdt, node, "status", "okay");
+ if (ret < 0) {
+ goto err;
+ }
+
+ return;
+err:
+ NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
+ panic();
+#endif
+}
+
+static void bl2_add_dram_entry(uint64_t start, uint64_t size)
{
char nodename[32] = { 0 };
- uint64_t start, size;
uint64_t fdtsize;
- int ret, node, chan;
+ int ret, node;
+
+ fdtsize = cpu_to_fdt64(size);
+
+ snprintf(nodename, sizeof(nodename), "memory@");
+ unsigned_num_print(start, 16, nodename + strlen(nodename));
+ node = ret = fdt_add_subnode(fdt, 0, nodename);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_string(fdt, node, "device_type", "memory");
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_u64(fdt, node, "reg", start);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
+ sizeof(fdtsize));
+ if (ret < 0) {
+ goto err;
+ }
+
+ return;
+err:
+ NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n",
+ start, start + size - 1, ret);
+ panic();
+}
+
+static void bl2_advertise_dram_entries(uint64_t dram_config[8])
+{
+ uint64_t start, size, size32;
+ int chan;
for (chan = 0; chan < 4; chan++) {
start = dram_config[2 * chan];
@@ -568,39 +661,43 @@
/*
* Channel 0 is mapped in 32bit space and the first
- * 128 MiB are reserved
+ * 128 MiB are reserved and the maximum size is 2GiB.
*/
if (chan == 0) {
- start = 0x48000000;
- size -= 0x8000000;
- }
-
- fdtsize = cpu_to_fdt64(size);
+ /* Limit the 32bit entry to 2 GiB - 128 MiB */
+ size32 = size - 0x8000000U;
+ if (size32 >= 0x78000000U) {
+ size32 = 0x78000000U;
+ }
- snprintf(nodename, sizeof(nodename), "memory@");
- unsigned_num_print(start, 16, nodename + strlen(nodename));
- node = ret = fdt_add_subnode(fdt, 0, nodename);
- if (ret < 0)
- goto err;
+ /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
+ bl2_add_dram_entry(0x48000000, size32);
- ret = fdt_setprop_string(fdt, node, "device_type", "memory");
- if (ret < 0)
- goto err;
+ /*
+ * If channel 0 is less than 2 GiB long, the
+ * entire memory fits into the 32bit space entry,
+ * so move on to the next channel.
+ */
+ if (size <= 0x80000000U) {
+ continue;
+ }
- ret = fdt_setprop_u64(fdt, node, "reg", start);
- if (ret < 0)
- goto err;
+ /*
+ * If channel 0 is more than 2 GiB long, emit
+ * another entry which covers the rest of the
+ * memory in channel 0, in the 64bit space.
+ *
+ * Start of this new entry is at 2 GiB offset
+ * from the beginning of the 64bit channel 0
+ * address, size is 2 GiB shorter than total
+ * size of the channel.
+ */
+ start += 0x80000000U;
+ size -= 0x80000000U;
+ }
- ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
- sizeof(fdtsize));
- if (ret < 0)
- goto err;
+ bl2_add_dram_entry(start, size);
}
-
- return;
-err:
- NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret);
- panic();
}
static void bl2_advertise_dram_size(uint32_t product)
@@ -648,8 +745,13 @@
break;
case PRR_PRODUCT_M3N:
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
+ /* 4GB(4GBx1) */
+ dram_config[1] = 0x100000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
/* 2GB(1GBx2) */
dram_config[1] = 0x80000000ULL;
+#endif
break;
case PRR_PRODUCT_V3M:
@@ -935,6 +1037,9 @@
/* Add platform compatible string */
bl2_populate_compatible_string(fdt);
+ /* Enable RPC if unlocked */
+ bl2_add_rpc_node();
+
/* Print DRAM layout */
bl2_advertise_dram_size(product);
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 7a7a56c..670d499 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -245,6 +245,12 @@
endif
$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF))
+# Process RCAR_DRAM_MEMRANK flag
+ifndef RCAR_DRAM_MEMRANK
+RCAR_DRAM_MEMRANK :=0
+endif
+$(eval $(call add_define,RCAR_DRAM_MEMRANK))
+
# Process RCAR_DRAM_DDR3L_MEMCONF flag
ifndef RCAR_DRAM_DDR3L_MEMCONF
RCAR_DRAM_DDR3L_MEMCONF :=1
@@ -280,6 +286,11 @@
endif
$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
+ifndef RCAR_GEN3_BL33_GZIP
+RCAR_GEN3_BL33_GZIP := 0
+endif
+$(eval $(call add_define,RCAR_GEN3_BL33_GZIP))
+
# RCAR_SYSTEM_RESET_KEEPON_DDR requires power control of PMIC etc.
# When executing SYSTEM_SUSPEND other than Salvator-X, Salvator-XS and Ebisu,
# processing equivalent to that implemented in PMIC_ROHM_BD9571 is necessary.
@@ -315,6 +326,13 @@
BL2_SOURCES += plat/renesas/rcar/bl2_plat_setup.c \
drivers/renesas/rcar/board/board.c
+ifeq (${RCAR_GEN3_BL33_GZIP},1)
+include lib/zlib/zlib.mk
+
+BL2_SOURCES += common/image_decompress.c \
+ $(ZLIB_SOURCES)
+endif
+
ifeq (${RCAR_GEN3_ULCB},1)
BL31_SOURCES += drivers/renesas/rcar/cpld/ulcb_cpld.c
endif