feat(plat/mediatek/mt8195): add support for PTP3
Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.
Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
new file mode 100644
index 0000000..341cf86
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_PTP3_COMMON_H
+#define MTK_PTP3_COMMON_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+/************************************************
+ * CPU info
+ ************************************************/
+#define NR_PTP3_CFG_CPU U(8)
+#define PTP3_CFG_CPU_START_ID_L U(0)
+#define PTP3_CFG_CPU_START_ID_B U(4)
+#define PTP3_CFG_CPU_END_ID U(7)
+
+#define NR_PTP3_CFG1_DATA U(2)
+#define PTP3_CFG1_MASK 0x3000
+
+#define NR_PTP3_CFG2_DATA U(5)
+
+#define PTP3_CFG3_MASK1 0x1180
+#define PTP3_CFG3_MASK2 0x35C0
+#define PTP3_CFG3_MASK3 0x3DC0
+
+/************************************************
+ * register read/write
+ ************************************************/
+#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val)
+#define ptp3_clrsetbits(addr, clear, set) \
+ mmio_clrsetbits_32((uintptr_t)addr, clear, set)
+
+/************************************************
+ * config enum
+ ************************************************/
+enum PTP3_CFG {
+ PTP3_CFG_ADDR,
+ PTP3_CFG_VALUE,
+ NR_PTP3_CFG,
+};
+
+/************************************
+ * prototype
+ ************************************/
+extern void ptp3_core_init(unsigned int core);
+extern void ptp3_core_unInit(unsigned int core);
+
+#endif /* MTK_PTP3_COMMON_H */
diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
new file mode 100644
index 0000000..540cb33
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved. \
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <mtk_ptp3_common.h>
+
+#define PTP3_CORE_OFT(core) (0x800 * (core))
+
+/************************************************
+ * Central control
+ ************************************************/
+static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
+ {0x0C53A2A0, 0x1000},
+ {0x0C53A2A4, 0x1000}
+};
+
+static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
+ {0x0C530404, 0x3A1000},
+ {0x0C530428, 0x13E0408},
+ {0x0C530434, 0xB22800},
+ {0x0C53043C, 0x750},
+ {0x0C530440, 0x0222c4cc}
+};
+
+static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80};
+static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
+
+static void ptp3_init(unsigned int core)
+{
+ unsigned int i, addr, value;
+
+ if (core < PTP3_CFG_CPU_START_ID_B) {
+ ptp3_clrsetbits(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
+ ptp3_cfg1[0][PTP3_CFG_VALUE]);
+ } else {
+ ptp3_clrsetbits(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
+ ptp3_cfg1[1][PTP3_CFG_VALUE]);
+ }
+
+ if (core < PTP3_CFG_CPU_START_ID_B) {
+ for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
+ addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
+ PTP3_CORE_OFT(core);
+ value = ptp3_cfg2[i][PTP3_CFG_VALUE];
+
+ ptp3_write(addr, value);
+ }
+ } else {
+ for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
+ addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
+ PTP3_CORE_OFT(core);
+
+ if (i == 2) {
+ value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0;
+ } else {
+ value = ptp3_cfg2[i][PTP3_CFG_VALUE];
+ }
+ ptp3_write(addr, value);
+ }
+ }
+
+ if (core < PTP3_CFG_CPU_START_ID_B) {
+ addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
+ value = ptp3_cfg3[PTP3_CFG_VALUE];
+
+ ptp3_write(addr, value & PTP3_CFG3_MASK1);
+ ptp3_write(addr, value & PTP3_CFG3_MASK2);
+ ptp3_write(addr, value & PTP3_CFG3_MASK3);
+ } else {
+ addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
+ value = ptp3_cfg3_ext[PTP3_CFG_VALUE];
+
+ ptp3_write(addr, value & PTP3_CFG3_MASK1);
+ ptp3_write(addr, value & PTP3_CFG3_MASK2);
+ ptp3_write(addr, value & PTP3_CFG3_MASK3);
+ }
+}
+
+void pdp_proc_ARM_write(unsigned int pdp_n)
+{
+ unsigned long v = 0;
+
+ dsb();
+ __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
+ v |= (UL(0x0) << 52);
+ v |= (UL(0x1) << 53);
+ v |= (UL(0x0) << 54);
+ v |= (UL(0x0) << 48);
+ v |= (UL(0x1) << 49);
+ __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
+ dsb();
+}
+
+void pdp_init(unsigned int pdp_cpu, unsigned int en)
+{
+ if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) &&
+ (pdp_cpu < NR_PTP3_CFG_CPU)) {
+ pdp_proc_ARM_write(pdp_cpu);
+ }
+}
+
+static void dt_proc_ARM_write(unsigned int dt_n)
+{
+ unsigned long v = 0;
+
+ dsb();
+ __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
+ v |= (UL(0x0) << 33);
+ v |= (UL(0x0) << 32);
+ __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
+ dsb();
+}
+
+void dt_init(unsigned int dt_cpu, unsigned int en)
+{
+ if ((dt_cpu >= PTP3_CFG_CPU_START_ID_B) &&
+ (dt_cpu < NR_PTP3_CFG_CPU)) {
+ dt_proc_ARM_write(dt_cpu);
+ }
+}
+void ptp3_core_init(unsigned int core)
+{
+ /* init for ptp3 */
+ ptp3_init(core);
+ /* init for pdp */
+ pdp_init(core, 1);
+ /* init for dt */
+ dt_init(core, 1);
+}
+
+void ptp3_core_unInit(unsigned int core)
+{
+ /* TBD */
+}
diff --git a/plat/mediatek/mt8195/plat_pm.c b/plat/mediatek/mt8195/plat_pm.c
index 522d443..631bba9 100644
--- a/plat/mediatek/mt8195/plat_pm.c
+++ b/plat/mediatek/mt8195/plat_pm.c
@@ -14,6 +14,7 @@
/* platform specific headers */
#include <mt_gic_v3.h>
+#include <mtk_ptp3_common.h>
#include <mtspmc.h>
#include <plat/common/platform.h>
#include <plat_mtk_lpm.h>
@@ -84,6 +85,9 @@
coordinate_cluster_pwron();
+ /* PTP3 config */
+ ptp3_core_init(cpu);
+
/* Enable the GIC CPU interface */
gicv3_rdistif_on(cpu);
gicv3_cpuif_enable(cpu);
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 026cf41..de797c7 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -17,6 +17,7 @@
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \
+ -I${MTK_PLAT_SOC}/drivers/ptp3/ \
-I${MTK_PLAT_SOC}/include/
GICV3_SUPPORT_GIC600 := 1
@@ -58,6 +59,7 @@
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
+ ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \