tree d63c232445b8948dc6e9f0eebd2525d8e8c6cd50
parent 4b73a48f579d56a756245ad04137576494703d9d
parent bfab8eb3819be584144912a0a2895fe317a584b6
author Manish V Badarkhe <manish.badarkhe@arm.com> 1721830075 +0200
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1721830075 +0200

Merge changes from topic "us_dsu_pmu" into integration

* changes:
  feat(tc): enable Last-level cache (LLC)
  feat(cpus): add sysreg_bitfield_insert_from_gpr macro
  feat(tc): add DSU PMU node for tc3
  feat(tc): enable el1 access to DSU PMU registers
  style(tc): remove comment for plat_reset_handler
  fix(context-mgmt): keep actlr_el2 value in the init context