tree 9b65ed64df3530d3d33aca4274df3da604fb2d81
parent 035d6d632486e5a9c4ae6b68a4dfdf804b139fbf
author Derek Basehore <dbasehore@chromium.org> 1486706562 -0800
committer Xing Zheng <zhengxing@rock-chips.com> 1487938065 +0800

rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>