rockchip: rk3399: Fix CAS latency setting
The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 37f666a..98ecd51 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1254,7 +1254,7 @@
mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY);
/* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
- pdram_timing->cl * 2);
+ (pdram_timing->cl * 2) << 8);
/* PI_47 PI_TREF_F1:RW:16:16 */
mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
pdram_timing->trefi << 16);