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git01.mediatek.com / filogic / atf / b015dc4acf7b5a6d4f67e6e807d7e580fdb07191 / . / plat / xilinx / versal_net
tree: 9ad1115e416a13720fdd6cc5647aecb114366e62 [path history] [tgz]
  1. aarch64/
  2. include/
  3. pm_service/
  4. bl31_versal_net_setup.c
  5. plat_psci.c
  6. plat_psci_pm.c
  7. plat_topology.c
  8. platform.mk
  9. sip_svc_setup.c
  10. versal_net_gicv3.c
  11. versal_net_ipi.c