drivers: Add emmc driver for Broadcom platforms
Add emmc driver for Broadcom platforms
Change-Id: I126a6dfccd41062cb0b856f2c2fb1f724730b95e
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
diff --git a/drivers/brcm/emmc/emmc_chal_sd.c b/drivers/brcm/emmc/emmc_chal_sd.c
new file mode 100644
index 0000000..34d761c
--- /dev/null
+++ b/drivers/brcm/emmc/emmc_chal_sd.c
@@ -0,0 +1,1017 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#include "bcm_emmc.h"
+#include "emmc_chal_types.h"
+#include "emmc_chal_sd.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+extern void emmc_soft_reset(void);
+
+#define SD_VDD_WINDOW_1_6_TO_1_7 0x00000010 // 1.6 V to 1.7 Volts
+#define SD_VDD_WINDOW_1_7_TO_1_8 0x00000020 // 1.7 V to 1.8 Volts
+#define SD_VDD_WINDOW_1_8_TO_1_9 0x00000040 // 1.8 V to 1.9 Volts
+#define SD_VDD_WINDOW_1_9_TO_2_0 0x00000080 // 1.9 V to 2.0 Volts
+#define SD_VDD_WINDOW_2_0_TO_2_1 0x00000100 // 2.0 V to 2.1 Volts
+#define SD_VDD_WINDOW_2_1_TO_2_2 0x00000200 // 2.1 V to 2.2 Volts
+#define SD_VDD_WINDOW_2_2_TO_2_3 0x00000400 // 2.2 V to 2.3 Volts
+#define SD_VDD_WINDOW_2_3_TO_2_4 0x00000800 // 2.3 V to 2.4 Volts
+#define SD_VDD_WINDOW_2_4_TO_2_5 0x00001000 // 2.4 V to 2.5 Volts
+#define SD_VDD_WINDOW_2_5_TO_2_6 0x00002000 // 2.5 V to 2.6 Volts
+#define SD_VDD_WINDOW_2_6_TO_2_7 0x00004000 // 2.6 V to 2.7 Volts
+#define SD_VDD_WINDOW_2_7_TO_2_8 0x00008000 // 2.7 V to 2.8 Volts
+#define SD_VDD_WINDOW_2_8_TO_2_9 0x00010000 // 2.8 V to 2.9 Volts
+#define SD_VDD_WINDOW_2_9_TO_3_0 0x00020000 // 2.9 V to 3.0 Volts
+#define SD_VDD_WINDOW_3_0_TO_3_1 0x00040000 // 3.0 V to 3.1 Volts
+#define SD_VDD_WINDOW_3_1_TO_3_2 0x00080000 // 3.1 V to 3.2 Volts
+#define SD_VDD_WINDOW_3_2_TO_3_3 0x00100000 // 3.2 V to 3.3 Volts
+#define SD_VDD_WINDOW_3_3_TO_3_4 0x00200000 // 3.3 V to 3.4 Volts
+#define SD_VDD_WINDOW_3_4_TO_3_5 0x00400000 // 3.4 V to 3.5 Volts
+#define SD_VDD_WINDOW_3_5_TO_3_6 0x00800000 // 3.5 V to 3.6 Volts
+
+#define SD_VDD_WINDOW_1_6_TO_2_6 (SD_VDD_WINDOW_1_6_TO_1_7 | \
+ SD_VDD_WINDOW_1_7_TO_1_8 | \
+ SD_VDD_WINDOW_1_8_TO_1_9 | \
+ SD_VDD_WINDOW_1_9_TO_2_0 | \
+ SD_VDD_WINDOW_2_0_TO_2_1 | \
+ SD_VDD_WINDOW_2_1_TO_2_2 | \
+ SD_VDD_WINDOW_2_2_TO_2_3 | \
+ SD_VDD_WINDOW_2_3_TO_2_4 | \
+ SD_VDD_WINDOW_2_4_TO_2_5 | \
+ SD_VDD_WINDOW_2_5_TO_2_6)
+
+#define SD_VDD_WINDOW_2_6_TO_3_2 (SD_VDD_WINDOW_2_6_TO_2_7 | \
+ SD_VDD_WINDOW_2_7_TO_2_8 | \
+ SD_VDD_WINDOW_2_8_TO_2_9 | \
+ SD_VDD_WINDOW_2_9_TO_3_0 | \
+ SD_VDD_WINDOW_3_0_TO_3_1 | \
+ SD_VDD_WINDOW_3_1_TO_3_2)
+
+#define SD_VDD_WINDOW_3_2_TO_3_6 (SD_VDD_WINDOW_3_2_TO_3_3 | \
+ SD_VDD_WINDOW_3_3_TO_3_4 | \
+ SD_VDD_WINDOW_3_4_TO_3_5 | \
+ SD_VDD_WINDOW_3_5_TO_3_6)
+
+
+static int32_t chal_sd_set_power(struct sd_dev *handle,
+ uint32_t voltage, uint32_t state);
+
+static void chal_sd_set_dma_boundary(struct sd_dev *handle, uint32_t boundary);
+
+static int32_t chal_sd_setup_handler(struct sd_dev *handle,
+ uint32_t sdBbase, uint32_t hostBase);
+
+/*
+ * Configure host controller pwr settings,
+ * to match voltage requirements by SD Card
+ */
+static int32_t chal_sd_set_power(struct sd_dev *handle,
+ uint32_t voltage, uint32_t state)
+{
+ int32_t rc, rval = SD_FAIL;
+ uint32_t time = 0;
+
+ if (handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL_OFFSET,
+ (SD4_EMMC_TOP_CTRL_SDVSELVDD1_MASK |
+ SD4_EMMC_TOP_CTRL_SDPWR_MASK),
+ (voltage << 9));
+
+ /*
+ * Long delay is required here in emulation. Without this, the initial
+ * commands sent to the eMMC card timeout. We don't know if this
+ * delay is necessary with silicon, leaving in for safety.
+ * It is observed that 403ms on emulation system and as per the clock
+ * calculations it is expected to complete with in 1ms on chip
+ */
+ do {
+ rc = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET);
+
+ if ((rc & SD4_EMMC_TOP_INTR_CRDINS_MASK) ==
+ SD4_EMMC_TOP_INTR_CRDINS_MASK)
+ break;
+
+ mdelay(1);
+ } while (time++ < EMMC_CARD_DETECT_TIMEOUT_MS);
+
+ if (time >= EMMC_CARD_DETECT_TIMEOUT_MS) {
+ ERROR("EMMC: Card insert event detection timeout\n");
+ return rval;
+ }
+
+ VERBOSE("EMMC: Card detection delay: %dms\n", time);
+
+ if (state)
+ mmio_setbits_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET,
+ SD4_EMMC_TOP_CTRL_SDPWR_MASK);
+
+ /* dummy write & ack to verify if the sdio is ready to send commads */
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET, 0);
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET, 0);
+
+ /*
+ * 63ms observed on emulation system, As per clock calculations
+ * it will complete < 1ms on chip.
+ */
+ time = 0;
+ do {
+ rc = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET);
+
+ if (rc & SD4_EMMC_TOP_INTR_ERRIRQ_MASK)
+ break;
+
+ if ((rc & SD4_EMMC_TOP_INTR_CMDDONE_MASK) ==
+ SD4_EMMC_TOP_INTR_CMDDONE_MASK)
+ break;
+
+ mdelay(1);
+ } while (time++ < EMMC_CMD_TIMEOUT_MS);
+
+ if (time >= EMMC_CMD_TIMEOUT_MS) {
+ WARN("%s %d Initial dummy command timeout is happened\n",
+ __func__, __LINE__);
+ return rval;
+ }
+
+ VERBOSE("EMMC: Dummy Command delay: %dms\n", time);
+
+ return SD_OK;
+}
+
+/*
+ * Configure DMA Boundaries
+ */
+static void chal_sd_set_dma_boundary(struct sd_dev *handle, uint32_t boundary)
+{
+ if (handle == NULL)
+ return;
+
+ mmio_clrsetbits_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_BLOCK_OFFSET,
+ SD4_EMMC_TOP_BLOCK_HSBS_MASK, boundary);
+}
+
+static int32_t chal_sd_setup_handler(struct sd_dev *handle, uint32_t sdBase,
+ uint32_t hostBase)
+{
+ if (handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle->ctrl.sdRegBaseAddr = sdBase;
+ handle->ctrl.hostRegBaseAddr = hostBase;
+ handle->ctrl.present = 0;
+ handle->ctrl.rca = 0;
+ handle->ctrl.blkGapEnable = 0;
+ handle->ctrl.cmdStatus = 0;
+
+ return SD_OK;
+}
+
+/*
+ * Initialize SD Host controller
+ */
+int32_t chal_sd_init(CHAL_HANDLE *sd_handle)
+{
+ uint32_t cap_val_l = 0;
+ uint32_t ctl_val, voltage;
+ uint32_t timeout_val;
+ struct sd_dev *handle;
+ uint32_t reg_val;
+ int32_t rval = SD_FAIL;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ /*
+ * Set SDIO Host Controller capabilities register
+ */
+ EMMC_TRACE("Set Host Controller Capabilities register\n");
+
+ reg_val = 0;
+ reg_val |= (1 << ICFG_SDIO0_CAP0__SLOT_TYPE_R);
+ reg_val |= (0 << ICFG_SDIO0_CAP0__INT_MODE_R);
+ reg_val |= (0 << ICFG_SDIO0_CAP0__SYS_BUS_64BIT_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_1P8V_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P0V_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__VOLTAGE_3P3V_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__SUSPEND_RESUME_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__SDMA_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__HIGH_SPEED_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__ADMA2_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__EXTENDED_MEDIA_R);
+ reg_val |= (2 << ICFG_SDIO0_CAP0__MAX_BLOCK_LEN_R);
+ reg_val |= (0xd0 << ICFG_SDIO0_CAP0__BASE_CLK_FREQ_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP0__TIMEOUT_UNIT_R);
+ reg_val |= (0x30 << ICFG_SDIO0_CAP0__TIMEOUT_CLK_FREQ_R);
+
+ mmio_write_32(ICFG_SDIO0_CAP0, reg_val);
+
+ reg_val = 0;
+ reg_val |= (1 << ICFG_SDIO0_CAP1__SPI_BLOCK_MODE_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__SPI_MODE_R);
+ reg_val |= (0 << ICFG_SDIO0_CAP1__CLK_MULT_R);
+ reg_val |= (0 << ICFG_SDIO0_CAP1__RETUNING_MODE_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__TUNE_SDR50_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__TIME_RETUNE_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_D_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_C_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__DRIVER_A_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__DDR50_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__SDR104_R);
+ reg_val |= (1 << ICFG_SDIO0_CAP1__SDR50_R);
+
+ mmio_write_32(ICFG_SDIO0_CAP1, reg_val);
+
+ /* Reset the SDIO controller */
+ chal_sd_stop();
+
+ /* Turn on SD clock */
+ chal_sd_set_clock(sd_handle,
+ chal_sd_freq_2_div_ctrl_setting(INIT_CLK_FREQ), 1);
+
+ /* program data time out value to the max */
+ timeout_val = SD_HOST_CORE_TIMEOUT;
+
+ ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL1_OFFSET);
+ ctl_val |= ((timeout_val & 0xf) << SD4_EMMC_TOP_CTRL1_DTCNT_SHIFT);
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
+ ctl_val);
+
+ /* enable all interrupt status */
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET,
+ 0);
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET,
+ 0);
+
+ SD_US_DELAY(100);
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN1_OFFSET,
+ SD_NOR_INTERRUPTS | SD_ERR_INTERRUPTS);
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_INTREN2_OFFSET,
+ SD_NOR_INTERRUPTS | SD_ERR_INTERRUPTS);
+
+ /* Select SD bus voltage */
+ cap_val_l = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CAPABILITIES1_OFFSET);
+ handle->cfg.voltage = 0;
+ voltage = 0x7;
+
+ if (cap_val_l & SD4_EMMC_TOP_CAPABILITIES1_V33_MASK) {
+ handle->cfg.voltage |= SD_VDD_WINDOW_3_3_TO_3_4;
+ voltage = 0x7;
+ } else if (cap_val_l & SD4_EMMC_TOP_CAPABILITIES1_V3_MASK) {
+ handle->cfg.voltage |= SD_VDD_WINDOW_3_0_TO_3_1;
+ voltage = 0x6;
+ } else if (cap_val_l & SD4_EMMC_TOP_CAPABILITIES1_V18_MASK) {
+ handle->cfg.voltage |= SD_VDD_WINDOW_1_8_TO_1_9;
+ voltage = 0x5;
+ }
+
+ rval = chal_sd_set_power(handle, voltage, SD4_EMMC_TOP_CTRL_SDPWR_MASK);
+
+ ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_HCVERSIRQ_OFFSET);
+ handle->ctrl.version = ((ctl_val >> 16) & 0xFF);
+
+ return rval;
+}
+
+void chal_sd_set_speed(CHAL_HANDLE *sd_handle, uint32_t speed)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ if (speed) {
+ EMMC_TRACE("enable HighSpeed\n");
+ mmio_setbits_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL_OFFSET,
+ SD4_EMMC_TOP_CTRL_HSEN_MASK);
+ } else {
+ EMMC_TRACE("disable HighSpeed\n");
+ mmio_clrbits_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL_OFFSET,
+ SD4_EMMC_TOP_CTRL_HSEN_MASK);
+ }
+}
+
+int32_t chal_sd_stop(void)
+{
+ uintptr_t idm_rst_ctrl_addr = EMMC_IDM_RESET_CTRL_ADDR;
+
+ /* Configure IO pins */
+ emmc_soft_reset();
+
+ /* Reset the SDIO controller */
+ mmio_write_32(idm_rst_ctrl_addr, 1);
+ SD_US_DELAY(100);
+ mmio_write_32(idm_rst_ctrl_addr, 0);
+ SD_US_DELAY(100);
+
+ return SD_OK;
+}
+
+/*
+ * Check if host supports specified capability
+ * returns -ve val on error, 0 if capability not supported else 1.
+ */
+int32_t chal_sd_check_cap(CHAL_HANDLE *sd_handle, uint32_t caps)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ if (caps & mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CAPABILITIES1_OFFSET))
+ return 1;
+ else
+ return 0;
+}
+
+int32_t chal_sd_start(CHAL_HANDLE *sd_handle,
+ uint32_t mode, uint32_t sd_base, uint32_t host_base)
+{
+
+ struct sd_dev *handle;
+ int32_t rval = SD_FAIL;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ handle->cfg.mode = SD_PIO_MODE; /* set to PIO mode first for init */
+ handle->cfg.dma = SD_DMA_OFF;
+
+ chal_sd_setup_handler(handle, sd_base, host_base);
+
+ /* init and start hw */
+ rval = chal_sd_init(sd_handle);
+ if (rval != SD_OK)
+ return rval;
+
+ chal_sd_clear_pending_irq(sd_handle);
+
+ handle->ctrl.eventList = 0;
+ handle->cfg.mode = mode;
+
+ return SD_OK;
+}
+
+/*
+ * Function to check 8bits of err generated from auto CMD12
+ */
+int32_t chal_sd_get_atuo12_error(CHAL_HANDLE *sd_handle)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ return (mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_ERRSTAT_OFFSET) & 0xFF);
+}
+
+/*
+ * Read present state register
+ */
+uint32_t chal_sd_get_present_status(CHAL_HANDLE *sd_handle)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ return mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_PSTATE_OFFSET);
+}
+
+/*
+ * Set SD bus width
+ */
+int32_t chal_sd_config_bus_width(CHAL_HANDLE *sd_handle, int32_t width)
+{
+ uint32_t ctl_val;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ ctl_val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL_OFFSET);
+
+ switch (width) {
+#ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
+ case SD_BUS_DATA_WIDTH_8BIT:
+ ctl_val &= ~SD_BUS_DATA_WIDTH_4BIT;
+ ctl_val |= SD_BUS_DATA_WIDTH_8BIT;
+ break;
+#endif
+ case SD_BUS_DATA_WIDTH_4BIT:
+ ctl_val &= ~SD_BUS_DATA_WIDTH_8BIT;
+ ctl_val |= SD_BUS_DATA_WIDTH_4BIT;
+ break;
+ case SD_BUS_DATA_WIDTH_1BIT:
+ ctl_val &= ~(SD_BUS_DATA_WIDTH_4BIT | SD_BUS_DATA_WIDTH_8BIT);
+ break;
+ default:
+ return SD_INV_DATA_WIDTH;
+ };
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL_OFFSET,
+ ctl_val);
+
+ return SD_OK;
+}
+
+/*
+ * Function to enable or disable DMA control.
+ */
+int32_t chal_sd_set_dma(CHAL_HANDLE *sd_handle, uint32_t mode)
+{
+ uint32_t val;
+ struct sd_dev *handle;
+ int32_t rc;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ if (mode) {
+ rc = chal_sd_check_cap(sd_handle,
+ SD4_EMMC_TOP_CAPABILITIES1_SDMA_MASK |
+ SD4_EMMC_TOP_CAPABILITIES1_ADMA2_MASK);
+ if (rc < 0)
+ return rc;
+
+ if (rc) {
+
+ handle->cfg.dma = mode;
+ val = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL_OFFSET);
+ val &= ~(SD4_EMMC_TOP_CTRL_DMASEL_MASK);
+ val |= handle->cfg.dma - 1;
+ mmio_write_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL_OFFSET, val);
+ return SD_OK;
+ }
+ }
+ handle->cfg.dma = 0;
+
+ return SD_FAIL;
+}
+
+/*
+ * Get current DMA address.
+ * Called only when there is no data transaction activity.
+ */
+uintptr_t chal_sd_get_dma_addr(CHAL_HANDLE *sd_handle)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ if (handle->cfg.dma == SD_DMA_OFF)
+ return 0;
+
+ return (uintptr_t)mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_SYSADDR_OFFSET);
+}
+
+int32_t chal_sd_send_cmd(CHAL_HANDLE *sd_handle, uint32_t cmd_idx,
+ uint32_t argument, uint32_t options)
+{
+ uint32_t cmd_mode_reg = 0;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ EMMC_TRACE("%s %d cmd:%d argReg:%x options:%x\n",
+ __func__, __LINE__, cmd_idx, argument, options);
+
+ /* Configure the value for command and mode registers */
+ cmd_mode_reg = (cmd_idx << 24) | options;
+
+ /*
+ * 1. Write block size reg & block count reg,
+ * this is done in the tx or rx setup
+ */
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_BLOCK_OFFSET,
+ handle->ctrl.blkReg);
+
+ /* 2. Write argument reg */
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_ARG_OFFSET,
+ argument);
+ handle->ctrl.argReg = argument;
+
+ /*
+ * 3. Write transfer mode reg & command reg, check the DMA bit which is
+ * set before this function call if it is selected.
+ */
+ if (cmd_idx == 24 || cmd_idx == 25 || cmd_idx == 18 || cmd_idx == 17 ||
+ cmd_idx == 42 || cmd_idx == 51 || cmd_idx == 53)
+ cmd_mode_reg |= ((handle->cfg.dma) ? 1 : 0);
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CMD_OFFSET,
+ cmd_mode_reg);
+
+ handle->ctrl.cmdIndex = cmd_idx;
+
+ return SD_OK;
+}
+
+int32_t chal_sd_set_dma_addr(CHAL_HANDLE *sd_handle, uintptr_t address)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ if (handle->cfg.dma == SD_DMA_OFF)
+ return SD_FAIL;
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET,
+ address);
+ return SD_OK;
+}
+
+uint32_t chal_sd_freq_2_div_ctrl_setting(uint32_t desired_freq)
+{
+ /*
+ * Divider control setting represents 1/2 of the actual divider value.
+ *
+ * DesiredFreq = BaseClockFreq / (2 * div_ctrl_setting)
+ *
+ * ==> div_ctrl_setting = BaseClockFreq / (2 * DesiredFreq)
+ */
+ uint32_t div_ctrl_setting;
+ uint32_t actual_freq;
+
+ assert(desired_freq != 0);
+
+ /* Special case, 0 = divider of 1. */
+ if (desired_freq >= BASE_CLK_FREQ)
+ return 0;
+
+ /* Normal case, desired_freq < BASE_CLK_FREQ */
+ div_ctrl_setting = BASE_CLK_FREQ / (2 * desired_freq);
+
+ actual_freq = BASE_CLK_FREQ / (2 * div_ctrl_setting);
+
+ if (actual_freq > desired_freq) {
+ /*
+ * Division does not result in exact freqency match.
+ * Make sure resulting frequency does not exceed requested freq.
+ */
+ div_ctrl_setting++;
+ }
+
+ return div_ctrl_setting;
+}
+
+int32_t chal_sd_set_clock(CHAL_HANDLE *sd_handle, uint32_t div_ctrl_setting,
+ uint32_t on)
+{
+ uint32_t value;
+ struct sd_dev *handle;
+ uint32_t time;
+ uint32_t clk_sel_high_byte = 0xFF & (div_ctrl_setting >> 8);
+ uint32_t clk_sel_low_byte = 0xFF & div_ctrl_setting;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ EMMC_TRACE("set_clock(div_ctrl_setting=%d,on=%d)\n",
+ div_ctrl_setting, on);
+
+ handle = (struct sd_dev *) sd_handle;
+
+ /* Read control register content. */
+ value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL1_OFFSET);
+
+ /* Disable Clock */
+ value &= ~(SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK);
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
+ value);
+
+ /* Clear bits of interest. */
+ value &= ~(SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK |
+ SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK);
+
+ /* Set bits of interest to new value. */
+ value |= (SD4_EMMC_TOP_CTRL1_SDCLKSEL_MASK &
+ (clk_sel_low_byte << SD4_EMMC_TOP_CTRL1_SDCLKSEL_SHIFT));
+ value |= (SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_MASK &
+ (clk_sel_high_byte << SD4_EMMC_TOP_CTRL1_SDCLKSEL_UP_SHIFT));
+ value |= SD4_EMMC_TOP_CTRL1_ICLKEN_MASK;
+
+ /* Write updated value back to control register. */
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
+ value);
+
+ time = 0;
+ do {
+ value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL1_OFFSET);
+
+ if ((value & SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK) ==
+ SD4_EMMC_TOP_CTRL1_ICLKSTB_MASK)
+ break;
+
+ mdelay(1);
+ } while (time++ < EMMC_CLOCK_SETTING_TIMEOUT_MS);
+
+ if (time >= EMMC_CLOCK_SETTING_TIMEOUT_MS)
+ WARN("%s %d clock settings timeout happenedi (%dms)\n",
+ __func__, __LINE__, time);
+
+ VERBOSE("EMMC: clock settings delay: %dms\n", time);
+
+ value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL1_OFFSET);
+
+ if (on)
+ value |= SD4_EMMC_TOP_CTRL1_SDCLKEN_MASK;
+
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
+ value);
+
+ return SD_OK;
+}
+
+/*
+ * function to setup DMA buffer and data length, calculates block
+ * size and the number of blocks to be transferred and return
+ * the DMA buffer address.
+ */
+int32_t chal_sd_setup_xfer(CHAL_HANDLE *sd_handle,
+ uint8_t *data, uint32_t length, int32_t dir)
+{
+ uint32_t blocks = 0;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ if (length <= handle->cfg.blockSize) {
+ handle->ctrl.blkReg = length | handle->cfg.dmaBoundary;
+ } else {
+ blocks = length / handle->cfg.blockSize;
+ handle->ctrl.blkReg = (blocks << 16) | handle->cfg.blockSize |
+ handle->cfg.dmaBoundary;
+ }
+
+ if (handle->cfg.dma != SD_DMA_OFF) {
+ /* For DMA target address setting, physical address should be used */
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_SYSADDR_OFFSET,
+ (uintptr_t)data);
+ }
+
+ return SD_OK;
+}
+
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+/*
+ * function to write one block data directly to the
+ * host controller's FIFO which is 1K uint8_t or
+ * 2K uint8_t in size.
+ * It is used in Non-DMA mode for data transmission.
+ */
+int32_t chal_sd_write_buffer(CHAL_HANDLE *sd_handle, uint32_t length,
+ uint8_t *data)
+{
+ uint32_t i, leftOver = 0, blockSize, size, value = 0;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ blockSize = handle->cfg.blockSize;
+
+ if (length == 0)
+ return SD_OK;
+
+ /* PIO mode, push into fifo word by word */
+ if (length >= blockSize) {
+ size = blockSize;
+ } else {
+ size = ((length >> 2) << 2);
+ leftOver = length % 4;
+ }
+
+ for (i = 0; i < size; i += 4) {
+ value = *(uint32_t *)(data + i);
+ mmio_write_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_BUFDAT_OFFSET, value);
+ }
+/*
+ * BUG ALERT:
+ * This implementation has TWO issues that must be addressed before you
+ * can safely INCLUDE_EMMC_DRIVER_WRITE_CODE.
+ *
+ * (1) For the last leftOver bytes, driver writes full word, which means
+ * some of the eMMC content (i.e. "4 - leftOver" will be erroneously
+ * overwritten).
+ * (2) eMMC is a block device. What happens when less than a full block of
+ * data is submitted???
+ */
+ if (leftOver > 0) {
+ value = ((*(uint32_t *)(data + i)) << (4 - leftOver));
+ mmio_write_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_BUFDAT_OFFSET, value);
+ }
+
+ return SD_OK;
+}
+#endif /* INCLUDE_EMMC_DRIVER_WRITE_CODE */
+
+/*
+ * Function to read maximal one block data directly
+ * from the data port of the host controller (FIFO). It is used
+ * in Non-DMA mode for data transmission.
+ */
+int32_t chal_sd_read_buffer(CHAL_HANDLE *sd_handle, uint32_t length,
+ uint8_t *data)
+{
+ uint32_t i, size, leftOver, blockSize, value;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ value = 0;
+
+ blockSize = handle->cfg.blockSize;
+
+ /* PIO mode, extract fifo word by word */
+ if (length >= blockSize) {
+ size = blockSize;
+ leftOver = 0;
+ } else {
+ leftOver = length % 4;
+ size = ((length >> 2) << 2);
+ }
+
+ for (i = 0; i < size; i += 4) {
+ value =
+ mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_BUFDAT_OFFSET);
+ memcpy((void *)(data + i), &value, sizeof(uint32_t));
+ }
+
+ if (leftOver > 0) {
+ value = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_BUFDAT_OFFSET);
+
+ /*
+ * Copy remaining non-full word bytes.
+ * (We run ARM as Little Endian)
+ */
+ uint8_t j = 0;
+
+ for (j = 0; j < leftOver; j++) {
+ data[i + j] = (value >> (j * 8)) & 0xFF;
+ }
+ }
+
+ return SD_OK;
+}
+
+/*
+ * Resets both DAT or CMD line.
+ */
+int32_t chal_sd_reset_line(CHAL_HANDLE *sd_handle, uint32_t line)
+{
+ uint32_t control, flag;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ flag = SD4_EMMC_TOP_CTRL1_CMDRST_MASK | SD4_EMMC_TOP_CTRL1_DATRST_MASK;
+
+ if (flag != (line | flag))
+ return SD_FAIL;
+
+ control = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL1_OFFSET);
+ control |= line;
+ mmio_write_32(handle->ctrl.sdRegBaseAddr + SD4_EMMC_TOP_CTRL1_OFFSET,
+ control);
+
+ /* reset CMD and DATA line should always work, no need to timed out */
+ do {
+ control = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_CTRL1_OFFSET);
+ } while (control & line);
+
+ return SD_OK;
+}
+
+/*
+ * Function to be called once a SD command is done to read
+ * back it's response data.
+ */
+int32_t chal_sd_get_response(CHAL_HANDLE *sd_handle, uint32_t *resp)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+ resp[0] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_RESP0_OFFSET);
+ resp[1] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_RESP2_OFFSET);
+ resp[2] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_RESP4_OFFSET);
+ resp[3] = mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_RESP6_OFFSET);
+
+ return SD_OK;
+}
+
+/*
+ * The function is called to clean all the pending interrupts.
+ */
+int32_t chal_sd_clear_pending_irq(CHAL_HANDLE *sd_handle)
+{
+ uint32_t status = SD_OK;
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ /* Make sure clean all interrupts */
+ do {
+ mmio_write_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET, 0xFFFFFFFF);
+ SD_US_DELAY(10);
+ } while (mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET));
+
+ return status;
+}
+
+/*
+ * The function returns interrupt status register value.
+ */
+int32_t chal_sd_get_irq_status(CHAL_HANDLE *sd_handle)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ return (mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET));
+}
+
+/*
+ * The function clears interrupt(s) specified in the mask.
+ */
+int32_t chal_sd_clear_irq(CHAL_HANDLE *sd_handle, uint32_t mask)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ /* Make sure clean masked interrupts */
+ do {
+ mmio_write_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET, mask);
+ SD_US_DELAY(10);
+ } while (mask &
+ mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTR_OFFSET));
+
+ return SD_OK;
+}
+
+/*
+ * Description: The function configures the SD host controller.
+ */
+int32_t chal_sd_config(CHAL_HANDLE *sd_handle, uint32_t speed, uint32_t retry,
+ uint32_t boundary, uint32_t blkSize, uint32_t dma)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return SD_INVALID_HANDLE;
+
+ handle = (struct sd_dev *) sd_handle;
+
+ handle->cfg.speedMode = speed;
+ handle->cfg.retryLimit = retry;
+ handle->cfg.dmaBoundary = boundary;
+ handle->cfg.blockSize = blkSize;
+
+ chal_sd_set_dma(sd_handle, dma);
+ SD_US_DELAY(100);
+ chal_sd_set_dma_boundary(handle, boundary);
+ SD_US_DELAY(100);
+
+ chal_sd_set_speed(sd_handle, speed);
+
+ SD_US_DELAY(100);
+ return SD_OK;
+}
+
+/*
+ * Cleans up HC FIFO.
+ */
+void chal_sd_dump_fifo(CHAL_HANDLE *sd_handle)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ /* in case there still data in the host buffer */
+ while (mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_PSTATE_OFFSET) & 0x800) {
+ mmio_read_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_BUFDAT_OFFSET);
+ };
+}
+
+/*
+ * Enable or disable a SD interrupt signal.
+ */
+void chal_sd_set_irq_signal(CHAL_HANDLE *sd_handle, uint32_t mask,
+ uint32_t state)
+{
+ struct sd_dev *handle;
+
+ if (sd_handle == NULL)
+ return;
+
+ handle = (struct sd_dev *)sd_handle;
+
+ if (state)
+ mmio_setbits_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTREN2_OFFSET, mask);
+ else
+ mmio_clrbits_32(handle->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_INTREN2_OFFSET, mask);
+}
diff --git a/drivers/brcm/emmc/emmc_csl_sdcard.c b/drivers/brcm/emmc/emmc_csl_sdcard.c
new file mode 100644
index 0000000..d6ad4bc
--- /dev/null
+++ b/drivers/brcm/emmc/emmc_csl_sdcard.c
@@ -0,0 +1,1087 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <stddef.h>
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+
+#include "bcm_emmc.h"
+#include "emmc_chal_types.h"
+#include "emmc_csl_sdprot.h"
+#include "emmc_chal_sd.h"
+#include "emmc_csl_sdcmd.h"
+#include "emmc_csl_sd.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+#define SD_CARD_BUSY 0x80000000
+#define SD_CARD_RETRY_LIMIT 1000
+#define SD_CARD_HIGH_SPEED_PS 13
+#define SD_CHK_HIGH_SPEED_MODE 0x00FFFFF1
+#define SD_SET_HIGH_SPEED_MODE 0x80FFFFF1
+#define SD_MMC_ENABLE_HIGH_SPEED 0x03b90100 //0x03b90103
+#define SD_MMC_8BIT_MODE 0x03b70200
+#define SD_MMC_4BIT_MODE 0x03b70100
+#define SD_MMC_1BIT_MODE 0x03b70000
+
+#define SD_MMC_BOOT_8BIT_MODE 0x03b10200
+#define SD_MMC_BOOT_4BIT_MODE 0x03b10100
+#define SD_MMC_BOOT_1BIT_MODE 0x03b10000
+#define SDIO_HW_EMMC_EXT_CSD_BOOT_CNF 0X03B30000
+
+#ifdef USE_EMMC_FIP_TOC_CACHE
+/*
+ * Cache size mirrors the size of the global eMMC temp buffer
+ * which is used for non-image body reads such as headers, ToC etc.
+ */
+#define CACHE_SIZE ((EMMC_BLOCK_SIZE) * 2)
+#define PARTITION_BLOCK_ADDR ((PLAT_FIP_ATTEMPT_OFFSET)/(EMMC_BLOCK_SIZE))
+
+static uint32_t cached_partition_block;
+static uint8_t cached_block[CACHE_SIZE];
+#endif
+
+static int set_card_data_width(struct sd_handle *handle, int width);
+static int abort_err(struct sd_handle *handle);
+static int err_recovery(struct sd_handle *handle, uint32_t errors);
+static int xfer_data(struct sd_handle *handle, uint32_t mode, uint32_t addr,
+ uint32_t length, uint8_t *base);
+
+int set_boot_config(struct sd_handle *handle, uint32_t config)
+{
+ return mmc_cmd6(handle, SDIO_HW_EMMC_EXT_CSD_BOOT_CNF | config);
+}
+
+void process_csd_mmc_speed(struct sd_handle *handle, uint32_t csd_mmc_speed)
+{
+ uint32_t div_ctrl_setting;
+
+ /* CSD field TRAN_SPEED:
+ * Bits [2:0] 0 = 100 KHz
+ * 1 = 1 MHz
+ * 2 = 10 MHz
+ * 3 = 100 MHz
+ * 4...7 Reserved.
+ * Bits [6:3] 0 = Reserved
+ * 1 = 1.0
+ * 2 = 1.2
+ * 3 = 1.3
+ * 4 = 1.5
+ * 5 = 2.0
+ * 6 = 2.6
+ * 7 = 3.0
+ * 8 = 3.5
+ * 9 = 4.0
+ * A = 4.5
+ * B = 5.2
+ * C = 5.5
+ * D = 6.0
+ * E = 7.0
+ * F = 8.0
+ * For cards supporting version 4.0, 4.1, and 4.2 of the standard,
+ * the value shall be 20 MHz (0x2A).
+ * For cards supporting version 4.3 , the value shall be 26 MHz (0x32)
+ */
+
+ switch (csd_mmc_speed & 0x7F) {
+ case 0x2A:
+ EMMC_TRACE("Speeding up eMMC clock to 20MHz\n");
+ div_ctrl_setting =
+ chal_sd_freq_2_div_ctrl_setting(20 * 1000 * 1000);
+ break;
+ case 0x32:
+ EMMC_TRACE("Speeding up eMMC clock to 26MHz\n");
+ div_ctrl_setting =
+ chal_sd_freq_2_div_ctrl_setting(26 * 1000 * 1000);
+ break;
+ default:
+ /* Unknown */
+ return;
+ }
+
+ chal_sd_set_clock((CHAL_HANDLE *) handle->device, div_ctrl_setting, 0);
+
+ chal_sd_set_clock((CHAL_HANDLE *) handle->device, div_ctrl_setting, 1);
+
+ SD_US_DELAY(1000);
+}
+
+
+/*
+ * The function changes SD/SDIO/MMC card data width if
+ * the card support configurable data width. The host controller
+ * and the card has to be in the same bus data width.
+ */
+int set_card_data_width(struct sd_handle *handle, int width)
+{
+ uint32_t data_width = 0;
+ int is_valid_arg = 1;
+ int rc = SD_FAIL;
+ char *bitwidth_str = " ";
+ char *result_str = "failed";
+
+ switch (width) {
+#ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
+ case SD_BUS_DATA_WIDTH_8BIT:
+ data_width = SD_MMC_8BIT_MODE;
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ bitwidth_str = "8_BIT";
+#endif
+ break;
+#endif
+ case SD_BUS_DATA_WIDTH_4BIT:
+ data_width = SD_MMC_4BIT_MODE;
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ bitwidth_str = "4_BIT";
+#endif
+ break;
+
+ case SD_BUS_DATA_WIDTH_1BIT:
+ data_width = SD_MMC_1BIT_MODE;
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ bitwidth_str = "1_BIT";
+#endif
+ break;
+
+ default:
+ is_valid_arg = 0;
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ bitwidth_str = "unknown";
+#endif
+ break;
+ }
+
+ if (is_valid_arg) {
+ rc = mmc_cmd6(handle, data_width);
+ if (rc == SD_OK) {
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ result_str = "succeeded";
+#endif
+ chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
+ width);
+ } else {
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ result_str = "failed";
+#endif
+ }
+ } else {
+ rc = SD_FAIL;
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+ result_str = "ignored";
+#endif
+ }
+
+ VERBOSE("SDIO Data Width(%s) %s.\n", bitwidth_str, result_str);
+
+ return rc;
+}
+
+
+/*
+ * Error handling routine. Does abort data
+ * transmission if error is found.
+ */
+static int abort_err(struct sd_handle *handle)
+{
+ uint32_t present, options, event, rel = 0;
+ struct sd_resp cmdRsp;
+
+ handle->device->ctrl.argReg = 0;
+ handle->device->ctrl.cmdIndex = SD_CMD_STOP_TRANSMISSION;
+
+ options = (SD_CMD_STOP_TRANSMISSION << 24) |
+ (SD_CMDR_RSP_TYPE_R1b_5b << SD_CMDR_RSP_TYPE_S) |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ chal_sd_send_cmd((CHAL_HANDLE *) handle->device,
+ handle->device->ctrl.cmdIndex,
+ handle->device->ctrl.argReg, options);
+
+ event = wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_CMDDONE_MASK |
+ SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (event & SD_CMD_ERROR_INT) {
+ rel = SD_ERROR_NON_RECOVERABLE;
+ } else {
+ if (event & SD_DAT_TIMEOUT) {
+ return SD_ERROR_NON_RECOVERABLE;
+ }
+
+ chal_sd_get_response((CHAL_HANDLE *) handle->device,
+ (uint32_t *)&cmdRsp);
+
+ process_cmd_response(handle, handle->device->ctrl.cmdIndex,
+ cmdRsp.data.r2.rsp1, cmdRsp.data.r2.rsp2,
+ cmdRsp.data.r2.rsp3, cmdRsp.data.r2.rsp4,
+ &cmdRsp);
+
+ SD_US_DELAY(2000);
+
+ present =
+ chal_sd_get_present_status((CHAL_HANDLE *) handle->device);
+
+ if ((present & 0x00F00000) == 0x00F00000)
+ rel = SD_ERROR_RECOVERABLE;
+ else
+ rel = SD_ERROR_NON_RECOVERABLE;
+ }
+
+ return rel;
+}
+
+
+/*
+ * The function handles real data transmission on both DMA and
+ * none DMA mode, In None DMA mode the data transfer starts
+ * when the command is sent to the card, data has to be written
+ * into the host contollers buffer at this time one block
+ * at a time.
+ * In DMA mode, the real data transfer is done by the DMA engine
+ * and this functions just waits for the data transfer to complete.
+ *
+ */
+int process_data_xfer(struct sd_handle *handle, uint8_t *buffer, uint32_t addr,
+ uint32_t length, int dir)
+{
+ if (dir == SD_XFER_HOST_TO_CARD) {
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+ if (handle->device->cfg.dma == SD_DMA_OFF) {
+ /*
+ * In NON DMA mode, the real data xfer starts from here
+ */
+ if (write_buffer(handle, length, buffer))
+ return SD_WRITE_ERROR;
+ } else {
+ wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_TXDONE_MASK |
+ SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus == SD_OK)
+ return SD_OK;
+
+ check_error(handle, handle->device->ctrl.cmdStatus);
+ return SD_WRITE_ERROR;
+ }
+#else
+ return SD_WRITE_ERROR;
+#endif
+ } else { /* SD_XFER_CARD_TO_HOST */
+
+ if (handle->device->cfg.dma == SD_DMA_OFF) {
+ /* In NON DMA mode, the real data
+ * transfer starts from here
+ */
+ if (read_buffer(handle, length, buffer))
+ return SD_READ_ERROR;
+
+ } else { /* for DMA mode */
+
+ /*
+ * once the data transmission is done
+ * copy data to the host buffer.
+ */
+ wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_TXDONE_MASK |
+ SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus == SD_OK)
+ return SD_OK;
+
+ check_error(handle, handle->device->ctrl.cmdStatus);
+ return SD_READ_ERROR;
+ }
+ }
+ return SD_OK;
+}
+
+
+/*
+ * The function sets block size for the next SD/SDIO/MMC
+ * card read/write command.
+ */
+int select_blk_sz(struct sd_handle *handle, uint16_t size)
+{
+ return sd_cmd16(handle, size);
+}
+
+
+/*
+ * The function initalizes the SD/SDIO/MMC/CEATA and detects
+ * the card according to the flag of detection.
+ * Once this function is called, the card is put into ready state
+ * so application can do data transfer to and from the card.
+ */
+int init_card(struct sd_handle *handle, int detection)
+{
+ /*
+ * After Reset, eMMC comes up in 1 Bit Data Width by default.
+ * Set host side to match.
+ */
+ chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
+ SD_BUS_DATA_WIDTH_1BIT);
+
+#ifdef USE_EMMC_FIP_TOC_CACHE
+ cached_partition_block = 0;
+#endif
+ handle->device->ctrl.present = 0; /* init card present to be no card */
+
+ init_mmc_card(handle);
+
+ handle->device->ctrl.present = 1; /* card is detected */
+
+ /* switch the data width back */
+ if (handle->card->type != SD_CARD_MMC)
+ return SD_FAIL;
+
+ /*
+ * Dynamically set Data Width to highest supported value.
+ * Try different data width settings (highest to lowest).
+ * Verify each setting by reading EXT_CSD and comparing
+ * against the EXT_CSD contents previously read in call to
+ * init_mmc_card() earlier. Stop at first verified data width
+ * setting.
+ */
+ {
+#define EXT_CSD_PROPERTIES_SECTION_START_INDEX 192
+#define EXT_CSD_PROPERTIES_SECTION_END_INDEX 511
+ uint8_t buffer[EXT_CSD_SIZE];
+#ifdef DRIVER_EMMC_ENABLE_DATA_WIDTH_8BIT
+ /* Try 8 Bit Data Width */
+ chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
+ SD_BUS_DATA_WIDTH_8BIT);
+ if ((!set_card_data_width(handle, SD_BUS_DATA_WIDTH_8BIT)) &&
+ (!mmc_cmd8(handle, buffer)) &&
+ (!memcmp(&buffer[EXT_CSD_PROPERTIES_SECTION_START_INDEX],
+ &(emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_PROPERTIES_SECTION_START_INDEX]),
+ EXT_CSD_PROPERTIES_SECTION_END_INDEX - EXT_CSD_PROPERTIES_SECTION_START_INDEX + 1)))
+
+ return SD_OK;
+#endif
+ /* Fall back to 4 Bit Data Width */
+ chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
+ SD_BUS_DATA_WIDTH_4BIT);
+ if ((!set_card_data_width(handle, SD_BUS_DATA_WIDTH_4BIT)) &&
+ (!mmc_cmd8(handle, buffer)) &&
+ (!memcmp(&buffer[EXT_CSD_PROPERTIES_SECTION_START_INDEX],
+ &(emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_PROPERTIES_SECTION_START_INDEX]),
+ EXT_CSD_PROPERTIES_SECTION_END_INDEX - EXT_CSD_PROPERTIES_SECTION_START_INDEX + 1)))
+
+ return SD_OK;
+
+ /* Fall back to 1 Bit Data Width */
+ chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
+ SD_BUS_DATA_WIDTH_1BIT);
+ /* Just use 1 Bit Data Width then. */
+ if (!set_card_data_width(handle, SD_BUS_DATA_WIDTH_1BIT))
+ return SD_OK;
+
+ }
+ return SD_CARD_INIT_ERROR;
+}
+
+
+/*
+ * The function handles MMC/CEATA card initalization.
+ */
+int init_mmc_card(struct sd_handle *handle)
+{
+ uint32_t ocr = 0, newOcr, rc, limit = 0;
+ uint32_t cmd1_option = 0x40300000;
+ uint32_t sec_count;
+
+ handle->card->type = SD_CARD_MMC;
+
+ do {
+ SD_US_DELAY(1000);
+ newOcr = 0;
+ ocr = 0;
+ rc = sd_cmd1(handle, cmd1_option, &newOcr);
+ limit++;
+
+ if (rc == SD_OK)
+ ocr = newOcr;
+
+ } while (((ocr & SD_CARD_BUSY) == 0) && (limit < SD_CARD_RETRY_LIMIT));
+
+ if (limit >= SD_CARD_RETRY_LIMIT) {
+ handle->card->type = SD_CARD_UNKNOWN;
+ EMMC_TRACE("CMD1 Timeout: Device is not ready\n");
+ return SD_CARD_UNKNOWN;
+ }
+
+ /* Save the ocr register */
+ handle->device->ctrl.ocr = ocr;
+
+ /* Ready State */
+ rc = sd_cmd2(handle);
+ if (rc != SD_OK) {
+ handle->card->type = SD_CARD_UNKNOWN;
+ return SD_CARD_UNKNOWN;
+ }
+
+ rc = sd_cmd3(handle);
+ if (rc != SD_OK) {
+ handle->card->type = SD_CARD_UNKNOWN;
+ return SD_CARD_UNKNOWN;
+ }
+ /* read CSD */
+ rc = sd_cmd9(handle, &emmc_global_vars_ptr->cardData);
+ if (rc != SD_OK) {
+ handle->card->type = SD_CARD_UNKNOWN;
+ return SD_CARD_UNKNOWN;
+ }
+
+ /* Increase clock frequency according to what the card advertises */
+ EMMC_TRACE("From CSD... cardData.csd.mmc.speed = 0x%X\n",
+ emmc_global_vars_ptr->cardData.csd.mmc.speed);
+ process_csd_mmc_speed(handle,
+ emmc_global_vars_ptr->cardData.csd.mmc.speed);
+
+ /* goto transfer mode */
+ rc = sd_cmd7(handle, handle->device->ctrl.rca);
+ if (rc != SD_OK) {
+ handle->card->type = SD_CARD_UNKNOWN;
+ return SD_CARD_UNKNOWN;
+ }
+
+ rc = mmc_cmd8(handle, emmc_global_buf_ptr->u.Ext_CSD_storage);
+ if (rc == SD_OK) {
+ /* calcul real capacity */
+ sec_count = emmc_global_buf_ptr->u.Ext_CSD_storage[212] |
+ emmc_global_buf_ptr->u.Ext_CSD_storage[213] << 8 |
+ emmc_global_buf_ptr->u.Ext_CSD_storage[214] << 16 |
+ emmc_global_buf_ptr->u.Ext_CSD_storage[215] << 24;
+
+ EMMC_TRACE("Device density = %ldMBytes\n",
+ handle->card->size / (1024 * 1024));
+
+ if (sec_count > 0) {
+ handle->card->size = (uint64_t)sec_count * 512;
+
+ EMMC_TRACE("Updated Device density = %ldMBytes\n",
+ handle->card->size / (1024 * 1024));
+ }
+
+ if (sec_count > (2u * 1024 * 1024 * 1024) / 512) {
+ handle->device->ctrl.ocr |= SD_CARD_HIGH_CAPACITY;
+ handle->device->cfg.blockSize = 512;
+ }
+
+ if (handle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ EMMC_TRACE("Sector addressing\n");
+ else
+ EMMC_TRACE("Byte addressing\n");
+
+ EMMC_TRACE("Ext_CSD_storage[162]: 0x%02X Ext_CSD_storage[179]: 0x%02X\n",
+ emmc_global_buf_ptr->u.Ext_CSD_storage[162],
+ emmc_global_buf_ptr->u.Ext_CSD_storage[179]);
+ }
+
+ return handle->card->type;
+}
+
+
+/*
+ * The function send reset command to the card.
+ * The card will be in ready status after the reset.
+ */
+int reset_card(struct sd_handle *handle)
+{
+ int res = SD_OK;
+
+ /* on reset, card's RCA should return to 0 */
+ handle->device->ctrl.rca = 0;
+
+ res = sd_cmd0(handle);
+
+ if (res != SD_OK)
+ return SD_RESET_ERROR;
+
+ return res;
+}
+
+
+/*
+ * The function sends command to the card and starts
+ * data transmission.
+ */
+static int xfer_data(struct sd_handle *handle,
+ uint32_t mode,
+ uint32_t addr, uint32_t length, uint8_t *base)
+{
+ int rc = SD_OK;
+
+ VERBOSE("XFER: dest: 0x%llx, addr: 0x%x, size: 0x%x bytes\n",
+ (uint64_t)base, addr, length);
+
+ if ((length / handle->device->cfg.blockSize) > 1) {
+ if (mode == SD_OP_READ) {
+ inv_dcache_range((uintptr_t)base, (uint64_t)length);
+ rc = sd_cmd18(handle, addr, length, base);
+ } else {
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+ flush_dcache_range((uintptr_t)base, (uint64_t)length);
+ rc = sd_cmd25(handle, addr, length, base);
+#else
+ rc = SD_DATA_XFER_ERROR;
+#endif
+ }
+ } else {
+ if (mode == SD_OP_READ) {
+ inv_dcache_range((uintptr_t)base, (uint64_t)length);
+ rc = sd_cmd17(handle, addr,
+ handle->device->cfg.blockSize, base);
+ } else {
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+ flush_dcache_range((uintptr_t)base, (uint64_t)length);
+ rc = sd_cmd24(handle, addr,
+ handle->device->cfg.blockSize, base);
+#else
+ rc = SD_DATA_XFER_ERROR;
+#endif
+ }
+ }
+
+ if (rc != SD_OK)
+ return SD_DATA_XFER_ERROR;
+
+ return SD_OK;
+}
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+int erase_card(struct sd_handle *handle, uint32_t addr, uint32_t blocks)
+{
+ uint32_t end_addr;
+
+ INFO("ERASE: addr: 0x%x, num of sectors: 0x%x\n", addr, blocks);
+
+ if (sd_cmd35(handle, addr) != SD_OK)
+ return SD_FAIL;
+
+ end_addr = addr + blocks - 1;
+ if (sd_cmd36(handle, end_addr) != SD_OK)
+ return SD_FAIL;
+
+ if (sd_cmd38(handle) != SD_OK)
+ return SD_FAIL;
+
+ return SD_OK;
+}
+#endif
+
+/*
+ * The function reads block data from a card.
+ */
+#ifdef USE_EMMC_FIP_TOC_CACHE
+int read_block(struct sd_handle *handle,
+ uint8_t *dst, uint32_t addr, uint32_t len)
+{
+ int rel = SD_OK;
+
+ /*
+ * Avoid doing repeated reads of the partition block
+ * by caching.
+ */
+ if (cached_partition_block &&
+ addr == PARTITION_BLOCK_ADDR &&
+ len == CACHE_SIZE) {
+ memcpy(dst, cached_block, len);
+ } else {
+ rel = xfer_data(handle, SD_OP_READ, addr, len, dst);
+
+ if (len == CACHE_SIZE && addr == PARTITION_BLOCK_ADDR) {
+ cached_partition_block = 1;
+ memcpy(cached_block, dst, len);
+ }
+ }
+
+ return rel;
+}
+#else
+int read_block(struct sd_handle *handle,
+ uint8_t *dst, uint32_t addr, uint32_t len)
+{
+ return xfer_data(handle, SD_OP_READ, addr, len, dst);
+}
+#endif
+
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+
+/*
+ * The function writes block data to a card.
+ */
+int write_block(struct sd_handle *handle,
+ uint8_t *src, uint32_t addr, uint32_t len)
+{
+ int rel = SD_OK;
+
+ /*
+ * Current HC has problem to get response of cmd16 after cmd12,
+ * the delay is necessary to sure the next cmd16 will not be timed out.
+ * The delay has to be at least 4 ms.
+ * The code removed cmd16 and use cmd13 to get card status before
+ * sending cmd18 or cmd25 to make sure the card is ready and thus
+ * no need to have delay here.
+ */
+
+ rel = xfer_data(handle, SD_OP_WRITE, addr, len, src);
+
+ EMMC_TRACE("wr_blk addr:0x%08X src:0x%08X len:0x%08X result:%d\n",
+ addr, src, len, rel);
+
+ return rel;
+}
+
+
+/*
+ * The function is called to write one block data directly to
+ * a card's data buffer.
+ * it is used in Non-DMA mode for card data transmission.
+ */
+int write_buffer(struct sd_handle *handle, uint32_t length, uint8_t *data)
+{
+ uint32_t rem, blockSize, event;
+ uint8_t *pData = data;
+
+ blockSize = handle->device->cfg.blockSize;
+ rem = length;
+
+ if (rem == 0)
+ return SD_OK;
+
+ while (rem > 0) {
+
+ event = wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_BWRDY_MASK |
+ SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus) {
+ check_error(handle, handle->device->ctrl.cmdStatus);
+ return SD_WRITE_ERROR;
+ }
+
+ if (rem >= blockSize)
+ chal_sd_write_buffer((CHAL_HANDLE *) handle->device,
+ blockSize, pData);
+ else
+ chal_sd_write_buffer((CHAL_HANDLE *) handle->device,
+ rem, pData);
+
+ if (rem > blockSize) {
+ rem -= blockSize;
+ pData += blockSize;
+ } else {
+ pData += rem;
+ rem = 0;
+ }
+ }
+
+ if ((event & SD4_EMMC_TOP_INTR_TXDONE_MASK) !=
+ SD4_EMMC_TOP_INTR_TXDONE_MASK) {
+ event = wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_TXDONE_MASK |
+ SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus != SD_OK) {
+ check_error(handle, handle->device->ctrl.cmdStatus);
+ return SD_WRITE_ERROR;
+ }
+ } else {
+ handle->device->ctrl.eventList &= ~SD4_EMMC_TOP_INTR_TXDONE_MASK;
+ }
+
+ return SD_OK;
+}
+#endif /* INCLUDE_EMMC_DRIVER_WRITE_CODE */
+
+
+/*
+ * The function is called to read maximal one block data
+ * directly from a card
+ * It is used in Non-DMA mode for card data transmission.
+ */
+int read_buffer(struct sd_handle *handle, uint32_t length, uint8_t *data)
+{
+ uint32_t rem, blockSize, event = 0;
+ uint8_t *pData = data;
+
+ blockSize = handle->device->cfg.blockSize;
+ rem = length;
+
+ if (rem == 0)
+ return SD_OK;
+
+ while (rem > 0) {
+ event = wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_BRRDY_MASK |
+ SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus) {
+ check_error(handle, handle->device->ctrl.cmdStatus);
+ return SD_READ_ERROR;
+ }
+
+ if (rem >= blockSize)
+ chal_sd_read_buffer((CHAL_HANDLE *) handle->device,
+ blockSize, pData);
+ else
+ chal_sd_read_buffer((CHAL_HANDLE *) handle->device, rem,
+ pData);
+
+ if (rem > blockSize) {
+ rem -= blockSize;
+ pData += blockSize;
+ } else {
+ pData += rem;
+ rem = 0;
+ }
+ }
+
+ /* In case, there are extra data in the SD FIFO, just dump them. */
+ chal_sd_dump_fifo((CHAL_HANDLE *) handle->device);
+
+ if ((event & SD4_EMMC_TOP_INTR_TXDONE_MASK) !=
+ SD4_EMMC_TOP_INTR_TXDONE_MASK) {
+ event = wait_for_event(handle, SD4_EMMC_TOP_INTR_TXDONE_MASK,
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus) {
+ check_error(handle, handle->device->ctrl.cmdStatus);
+ return SD_READ_ERROR;
+ }
+ } else {
+ handle->device->ctrl.eventList &= ~SD4_EMMC_TOP_INTR_TXDONE_MASK;
+ }
+
+ return SD_OK;
+}
+
+
+/*
+ * Error handling routine.
+ * The function just reset the DAT
+ * and CMD line if an error occures during data transmission.
+ */
+int check_error(struct sd_handle *handle, uint32_t ints)
+{
+ uint32_t rel;
+
+ chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
+ SD_ERR_INTERRUPTS, 0);
+
+ if (ints & SD4_EMMC_TOP_INTR_CMDERROR_MASK) {
+
+ chal_sd_reset_line((CHAL_HANDLE *) handle->device,
+ SD4_EMMC_TOP_CTRL1_CMDRST_MASK);
+ rel = abort_err(handle);
+
+ chal_sd_reset_line((CHAL_HANDLE *) handle->device,
+ SD4_EMMC_TOP_CTRL1_DATRST_MASK);
+ chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
+ SD_ERR_INTERRUPTS, 1);
+
+ return (rel == SD_ERROR_NON_RECOVERABLE) ?
+ SD_ERROR_NON_RECOVERABLE : SD_ERROR_RECOVERABLE;
+ } else {
+ rel = err_recovery(handle, ints);
+ }
+
+ chal_sd_set_irq_signal((CHAL_HANDLE *) handle->device,
+ SD_ERR_INTERRUPTS, 1);
+
+ return rel;
+}
+
+
+/*
+ * Error recovery routine.
+ * Try to recover from the error.
+ */
+static int err_recovery(struct sd_handle *handle, uint32_t errors)
+{
+ uint32_t rel = 0;
+
+ /*
+ * In case of timeout error, the cmd line and data line maybe
+ * still active or stuck at atcitve so it is needed to reset
+ * either data line or cmd line to make sure a new cmd can be sent.
+ */
+
+ if (errors & SD_CMD_ERROR_INT)
+ chal_sd_reset_line((CHAL_HANDLE *) handle->device,
+ SD4_EMMC_TOP_CTRL1_CMDRST_MASK);
+
+ if (errors & SD_DAT_ERROR_INT)
+ chal_sd_reset_line((CHAL_HANDLE *) handle->device,
+ SD4_EMMC_TOP_CTRL1_DATRST_MASK);
+
+ /* Abort transaction by sending out stop command */
+ if ((handle->device->ctrl.cmdIndex == 18) ||
+ (handle->device->ctrl.cmdIndex == 25))
+ rel = abort_err(handle);
+
+ return rel;
+}
+
+
+/*
+ * The function is called to read one block data directly from a card.
+ * It is used in Non-DMA mode for card data transmission.
+ */
+int process_cmd_response(struct sd_handle *handle,
+ uint32_t cmdIndex,
+ uint32_t rsp0,
+ uint32_t rsp1,
+ uint32_t rsp2, uint32_t rsp3, struct sd_resp *resp)
+{
+ int result = SD_OK;
+
+ /* R6 */
+ uint32_t rca = (rsp0 >> 16) & 0xffff;
+ uint32_t cardStatus = rsp0;
+
+ /* R4 */
+ uint32_t cBit = (rsp0 >> 31) & 0x1;
+ uint32_t funcs = (rsp0 >> 28) & 0x7;
+ uint32_t memPresent = (rsp0 >> 27) & 0x1;
+
+ resp->r1 = 0x3f;
+ resp->cardStatus = cardStatus;
+
+ if (cmdIndex == SD_CMD_IO_SEND_OP_COND) {
+ resp->data.r4.cardReady = cBit;
+ resp->data.r4.funcs = funcs;
+ resp->data.r4.memPresent = memPresent;
+ resp->data.r4.ocr = cardStatus;
+ }
+
+ if (cmdIndex == SD_CMD_MMC_SET_RCA) {
+ resp->data.r6.rca = rca;
+ resp->data.r6.cardStatus = cardStatus & 0xFFFF;
+ }
+
+ if (cmdIndex == SD_CMD_SELECT_DESELECT_CARD) {
+ resp->data.r7.rca = rca;
+ }
+
+ if (cmdIndex == SD_CMD_IO_RW_DIRECT) {
+ if (((rsp0 >> 16) & 0xffff) != 0)
+ result = SD_CMD_ERR_INVALID_RESPONSE;
+
+ resp->data.r5.data = rsp0 & 0xff;
+ }
+
+ if (cmdIndex == SD_CMD_IO_RW_EXTENDED) {
+ if (((rsp0 >> 16) & 0xffff) != 0)
+ result = SD_CMD_ERR_INVALID_RESPONSE;
+
+ resp->data.r5.data = rsp0 & 0xff;
+ }
+
+ if (cmdIndex == SD_ACMD_SD_SEND_OP_COND ||
+ cmdIndex == SD_CMD_SEND_OPCOND)
+ resp->data.r3.ocr = cardStatus;
+
+ if (cmdIndex == SD_CMD_SEND_CSD ||
+ cmdIndex == SD_CMD_SEND_CID ||
+ cmdIndex == SD_CMD_ALL_SEND_CID) {
+ resp->data.r2.rsp4 = rsp3;
+ resp->data.r2.rsp3 = rsp2;
+ resp->data.r2.rsp2 = rsp1;
+ resp->data.r2.rsp1 = rsp0;
+ }
+
+ if ((cmdIndex == SD_CMD_READ_EXT_CSD) &&
+ (handle->card->type == SD_CARD_SD)) {
+ if ((resp->cardStatus & 0xAA) != 0xAA) {
+ result = SD_CMD_ERR_INVALID_RESPONSE;
+ }
+ }
+
+ return result;
+}
+
+
+/*
+ * The function sets DMA buffer and data length, process
+ * block size and the number of blocks to be transferred.
+ * It returns the DMA buffer address.
+ * It copies dma data from user buffer to the DMA buffer
+ * if the operation is to write data to the SD card.
+ */
+void data_xfer_setup(struct sd_handle *handle, uint8_t *data, uint32_t length,
+ int dir)
+{
+ chal_sd_setup_xfer((CHAL_HANDLE *)handle->device, data, length, dir);
+}
+
+
+/*
+ * The function does soft reset the host SD controller. After
+ * the function call all host controller's register are reset
+ * to default vallue;
+ *
+ * Note This function only resets the host controller it does not
+ * reset the controller's handler.
+ */
+int reset_host_ctrl(struct sd_handle *handle)
+{
+ chal_sd_stop();
+
+ return SD_OK;
+}
+
+static void pstate_log(struct sd_handle *handle)
+{
+ ERROR("PSTATE: 0x%x\n", mmio_read_32
+ (handle->device->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_PSTATE_SD4_OFFSET));
+ ERROR("ERRSTAT: 0x%x\n", mmio_read_32
+ (handle->device->ctrl.sdRegBaseAddr +
+ SD4_EMMC_TOP_ERRSTAT_OFFSET));
+}
+
+/*
+ * The function waits for one or a group of interrupts specified
+ * by mask. The function returns if any one the interrupt status
+ * is set. If interrupt mode is not enabled then it will poll
+ * the interrupt status register until a interrupt status is set
+ * an error interrupt happens. If interrupt mode is enabled then
+ * this function should be called after the interrupt
+ * is received by ISR routine.
+ */
+uint32_t wait_for_event(struct sd_handle *handle,
+ uint32_t mask, uint32_t retry)
+{
+ uint32_t regval, cmd12, time = 0;
+
+ handle->device->ctrl.cmdStatus = 0; /* no error */
+ EMMC_TRACE("%s %d mask:0x%x timeout:%d irq_status:0x%x\n",
+ __func__, __LINE__, mask, retry,
+ chal_sd_get_irq_status((CHAL_HANDLE *)handle->device));
+
+ /* Polling mode */
+ do {
+ regval = chal_sd_get_irq_status((CHAL_HANDLE *)handle->device);
+
+ if (regval & SD4_EMMC_TOP_INTR_DMAIRQ_MASK) {
+ chal_sd_set_dma_addr((CHAL_HANDLE *)handle->device,
+ (uintptr_t)
+ chal_sd_get_dma_addr((CHAL_HANDLE *)
+ handle->device));
+ chal_sd_clear_irq((CHAL_HANDLE *)handle->device,
+ SD4_EMMC_TOP_INTR_DMAIRQ_MASK);
+ }
+
+ if (time++ > retry) {
+ ERROR("EMMC: No response (cmd%d) after %dus.\n",
+ handle->device->ctrl.cmdIndex,
+ time * EMMC_WFE_RETRY_DELAY_US);
+ handle->device->ctrl.cmdStatus = SD_CMD_MISSING;
+ pstate_log(handle);
+ ERROR("EMMC: INT[0x%x]\n", regval);
+ break;
+ }
+
+ if (regval & SD4_EMMC_TOP_INTR_CTOERR_MASK) {
+ ERROR("EMMC: Cmd%d timeout INT[0x%x]\n",
+ handle->device->ctrl.cmdIndex, regval);
+ handle->device->ctrl.cmdStatus =
+ SD4_EMMC_TOP_INTR_CTOERR_MASK;
+ pstate_log(handle);
+ break;
+ }
+ if (regval & SD_CMD_ERROR_FLAGS) {
+ ERROR("EMMC: Cmd%d error INT[0x%x]\n",
+ handle->device->ctrl.cmdIndex, regval);
+ handle->device->ctrl.cmdStatus = SD_CMD_ERROR_FLAGS;
+ pstate_log(handle);
+ break;
+ }
+
+ cmd12 = chal_sd_get_atuo12_error((CHAL_HANDLE *)handle->device);
+ if (cmd12) {
+ ERROR("EMMC: Cmd%d auto cmd12 err:0x%x\n",
+ handle->device->ctrl.cmdIndex, cmd12);
+ handle->device->ctrl.cmdStatus = cmd12;
+ pstate_log(handle);
+ break;
+ }
+
+ if (SD_DATA_ERROR_FLAGS & regval) {
+ ERROR("EMMC: Data for cmd%d error, INT[0x%x]\n",
+ handle->device->ctrl.cmdIndex, regval);
+ handle->device->ctrl.cmdStatus =
+ (SD_DATA_ERROR_FLAGS & regval);
+ pstate_log(handle);
+ break;
+ }
+
+ if ((regval & mask) == 0)
+ udelay(EMMC_WFE_RETRY_DELAY_US);
+
+ } while ((regval & mask) == 0);
+
+ /* clear the interrupt since it is processed */
+ chal_sd_clear_irq((CHAL_HANDLE *)handle->device, (regval & mask));
+
+ return (regval & mask);
+}
+
+int32_t set_config(struct sd_handle *handle, uint32_t speed, uint32_t retry,
+ uint32_t dma, uint32_t dmaBound, uint32_t blkSize,
+ uint32_t wfe_retry)
+{
+ int32_t rel = 0;
+
+ if (handle == NULL)
+ return SD_FAIL;
+
+ handle->device->cfg.wfe_retry = wfe_retry;
+
+ rel = chal_sd_config((CHAL_HANDLE *)handle->device, speed, retry,
+ dmaBound, blkSize, dma);
+ return rel;
+
+}
+
+int mmc_cmd1(struct sd_handle *handle)
+{
+ uint32_t newOcr, res;
+ uint32_t cmd1_option = MMC_OCR_OP_VOLT | MMC_OCR_SECTOR_ACCESS_MODE;
+
+ /*
+ * After Reset, eMMC comes up in 1 Bit Data Width by default.
+ * Set host side to match.
+ */
+ chal_sd_config_bus_width((CHAL_HANDLE *) handle->device,
+ SD_BUS_DATA_WIDTH_1BIT);
+
+#ifdef USE_EMMC_FIP_TOC_CACHE
+ cached_partition_block = 0;
+#endif
+ handle->device->ctrl.present = 0; /* init card present to be no card */
+
+ handle->card->type = SD_CARD_MMC;
+
+ res = sd_cmd1(handle, cmd1_option, &newOcr);
+
+ if (res != SD_OK) {
+ EMMC_TRACE("CMD1 Timeout: Device is not ready\n");
+ res = SD_CARD_UNKNOWN;
+ }
+ return res;
+}
diff --git a/drivers/brcm/emmc/emmc_csl_sdcmd.c b/drivers/brcm/emmc/emmc_csl_sdcmd.c
new file mode 100644
index 0000000..c62886c
--- /dev/null
+++ b/drivers/brcm/emmc/emmc_csl_sdcmd.c
@@ -0,0 +1,842 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <stddef.h>
+
+#include "bcm_emmc.h"
+#include "emmc_chal_types.h"
+#include "emmc_chal_sd.h"
+#include "emmc_csl_sdprot.h"
+#include "emmc_csl_sdcmd.h"
+#include "emmc_csl_sd.h"
+#include "emmc_chal_sd.h"
+#include "emmc_pboot_hal_memory_drv.h"
+
+int sd_cmd0(struct sd_handle *handle)
+{
+ int res;
+ uint32_t argument = 0x0; /* Go to IDLE state. */
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_GO_IDLE_STATE, argument, 0, NULL);
+
+ if (res == SD_OK) {
+ /* Clear all other interrupts */
+ chal_sd_clear_irq((void *)handle->device, 0xffffffff);
+ }
+
+ return res;
+}
+
+int sd_cmd1(struct sd_handle *handle, uint32_t ocr, uint32_t *ocr_output)
+{
+ int res;
+ uint32_t options;
+ struct sd_resp resp;
+
+ options = SD_CMDR_RSP_TYPE_R3_4 << SD_CMDR_RSP_TYPE_S;
+
+ if (ocr_output == NULL) {
+ EMMC_TRACE("Invalid args\n");
+ return SD_FAIL;
+ }
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_SEND_OPCOND, ocr, options, &resp);
+
+ if (res == SD_OK)
+ *ocr_output = resp.data.r3.ocr;
+
+ return res;
+}
+
+int sd_cmd2(struct sd_handle *handle)
+{
+ uint32_t options;
+ struct sd_resp resp;
+
+ /* send cmd and parse result */
+ options = SD_CMDR_RSP_TYPE_R2 << SD_CMDR_RSP_TYPE_S;
+
+ return send_cmd(handle, SD_CMD_ALL_SEND_CID, 0, options, &resp);
+}
+
+int sd_cmd3(struct sd_handle *handle)
+{
+ int res;
+ uint32_t options = 0;
+ uint32_t argument;
+ struct sd_resp resp;
+
+ /* use non zero and non 0x1 value for rca */
+ handle->device->ctrl.rca = 0x5;
+ argument = handle->device->ctrl.rca << SD_CMD7_ARG_RCA_SHIFT;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_MMC_SET_RCA, argument, options, &resp);
+
+ if (res != SD_OK)
+ handle->device->ctrl.rca = 0;
+
+ return res;
+}
+
+int sd_cmd7(struct sd_handle *handle, uint32_t rca)
+{
+ int res;
+ uint32_t argument, options;
+ struct sd_resp resp;
+
+ argument = (rca << SD_CMD7_ARG_RCA_SHIFT);
+
+ /*
+ * Response to CMD7 is:
+ * R1 while selectiing from Stand-By State to Transfer State
+ * R1b while selecting from Disconnected State to Programming State.
+ *
+ * In this driver, we only issue a CMD7 once, to go to transfer mode
+ * during init_mmc_card().
+ */
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_SELECT_DESELECT_CARD, argument, options,
+ &resp);
+
+ if (res == SD_OK)
+ /* Clear all other interrupts */
+ chal_sd_clear_irq((void *)handle->device, 0xffffffff);
+
+ return res;
+}
+
+
+/*
+ * CMD8 Get CSD_EXT
+ */
+int mmc_cmd8(struct sd_handle *handle, uint8_t *extCsdReg)
+{
+ uint32_t res, options;
+ struct sd_resp resp;
+
+ data_xfer_setup(handle, extCsdReg, CEATA_EXT_CSDBLOCK_SIZE,
+ SD_XFER_CARD_TO_HOST);
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_DPS_MASK | SD4_EMMC_TOP_CMD_DTDS_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK | SD4_EMMC_TOP_CMD_CRC_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_READ_EXT_CSD, 0, options, &resp);
+
+ if (res == SD_OK)
+ res = process_data_xfer(handle, extCsdReg, 0,
+ CEATA_EXT_CSDBLOCK_SIZE,
+ SD_XFER_CARD_TO_HOST);
+
+ return res;
+}
+
+int sd_cmd9(struct sd_handle *handle, struct sd_card_data *card)
+{
+ int res;
+ uint32_t argument, options, iBlkNum, multiFactor = 1;
+ uint32_t maxReadBlockLen = 1, maxWriteBlockLen = 1;
+ struct sd_resp resp;
+
+ argument = handle->device->ctrl.rca << SD_CMD7_ARG_RCA_SHIFT;
+
+ options = SD_CMDR_RSP_TYPE_R2 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_SEND_CSD, argument, options, &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ if (handle->card->type == SD_CARD_MMC) {
+ card->csd.mmc.structure = (resp.data.r2.rsp4 >> 22) & 0x3;
+ card->csd.mmc.csdSpecVer = (resp.data.r2.rsp4 >> 18) & 0x0f;
+ card->csd.mmc.taac = (resp.data.r2.rsp4 >> 8) & 0xff;
+ card->csd.mmc.nsac = resp.data.r2.rsp4 & 0xff;
+ card->csd.mmc.speed = resp.data.r2.rsp3 >> 24;
+ card->csd.mmc.classes = (resp.data.r2.rsp3 >> 12) & 0xfff;
+ card->csd.mmc.rdBlkLen = (resp.data.r2.rsp3 >> 8) & 0xf;
+ card->csd.mmc.rdBlkPartial = (resp.data.r2.rsp3 >> 7) & 0x01;
+ card->csd.mmc.wrBlkMisalign = (resp.data.r2.rsp3 >> 6) & 0x1;
+ card->csd.mmc.rdBlkMisalign = (resp.data.r2.rsp3 >> 5) & 0x1;
+ card->csd.mmc.dsr = (resp.data.r2.rsp2 >> 4) & 0x01;
+ card->csd.mmc.size =
+ ((resp.data.r2.rsp3 & 0x3) << 10) +
+ ((resp.data.r2.rsp2 >> 22) & 0x3ff);
+ card->csd.mmc.vddRdCurrMin = (resp.data.r2.rsp2 >> 19) & 0x7;
+ card->csd.mmc.vddRdCurrMax = (resp.data.r2.rsp2 >> 16) & 0x7;
+ card->csd.mmc.vddWrCurrMin = (resp.data.r2.rsp2 >> 13) & 0x7;
+ card->csd.mmc.vddWrCurrMax = (resp.data.r2.rsp2 >> 10) & 0x7;
+ card->csd.mmc.devSizeMulti = (resp.data.r2.rsp2 >> 7) & 0x7;
+ card->csd.mmc.eraseGrpSize = (resp.data.r2.rsp2 >> 2) & 0x1f;
+ card->csd.mmc.eraseGrpSizeMulti =
+ ((resp.data.r2.rsp2 & 0x3) << 3) +
+ ((resp.data.r2.rsp1 >> 29) & 0x7);
+ card->csd.mmc.wrProtGroupSize =
+ ((resp.data.r2.rsp1 >> 24) & 0x1f);
+ card->csd.mmc.wrProtGroupEnable =
+ (resp.data.r2.rsp1 >> 23) & 0x1;
+ card->csd.mmc.manuDefEcc = (resp.data.r2.rsp1 >> 21) & 0x3;
+ card->csd.mmc.wrSpeedFactor = (resp.data.r2.rsp1 >> 18) & 0x7;
+ card->csd.mmc.wrBlkLen = (resp.data.r2.rsp1 >> 14) & 0xf;
+ card->csd.mmc.wrBlkPartial = (resp.data.r2.rsp1 >> 13) & 0x1;
+ card->csd.mmc.protAppl = (resp.data.r2.rsp1 >> 8) & 0x1;
+ card->csd.mmc.copyFlag = (resp.data.r2.rsp1 >> 7) & 0x1;
+ card->csd.mmc.permWrProt = (resp.data.r2.rsp1 >> 6) & 0x1;
+ card->csd.mmc.tmpWrProt = (resp.data.r2.rsp1 >> 5) & 0x1;
+ card->csd.mmc.fileFormat = (resp.data.r2.rsp1 >> 4) & 0x03;
+ card->csd.mmc.eccCode = resp.data.r2.rsp1 & 0x03;
+ maxReadBlockLen <<= card->csd.mmc.rdBlkLen;
+ maxWriteBlockLen <<= card->csd.mmc.wrBlkLen;
+
+ iBlkNum = card->csd.mmc.size + 1;
+ multiFactor = (1 << (card->csd.mmc.devSizeMulti + 2));
+
+ handle->card->size =
+ iBlkNum * multiFactor * (1 << card->csd.mmc.rdBlkLen);
+ }
+
+ handle->card->maxRdBlkLen = maxReadBlockLen;
+ handle->card->maxWtBlkLen = maxWriteBlockLen;
+
+ if (handle->card->size < 0xA00000) {
+ /*
+ * 10MB Too small size mean, cmd9 response is wrong,
+ * Use default value 1G
+ */
+ handle->card->size = 0x40000000;
+ handle->card->maxRdBlkLen = 512;
+ handle->card->maxWtBlkLen = 512;
+ }
+
+ if ((handle->card->maxRdBlkLen > 512) ||
+ (handle->card->maxWtBlkLen > 512)) {
+ handle->card->maxRdBlkLen = 512;
+ handle->card->maxWtBlkLen = 512;
+ } else if ((handle->card->maxRdBlkLen == 0) ||
+ (handle->card->maxWtBlkLen == 0)) {
+ handle->card->maxRdBlkLen = 512;
+ handle->card->maxWtBlkLen = 512;
+ }
+
+ handle->device->cfg.blockSize = handle->card->maxRdBlkLen;
+
+ return res;
+}
+
+int sd_cmd13(struct sd_handle *handle, uint32_t *status)
+{
+ int res;
+ uint32_t argument, options;
+ struct sd_resp resp;
+
+ argument = handle->device->ctrl.rca << SD_CMD7_ARG_RCA_SHIFT;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_SEND_STATUS, argument, options, &resp);
+
+ if (res == SD_OK) {
+ *status = resp.cardStatus;
+ }
+
+ return res;
+}
+
+int sd_cmd16(struct sd_handle *handle, uint32_t length)
+{
+ int res;
+ uint32_t argument, options, ntry;
+ struct sd_resp resp;
+
+ argument = length;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ ntry = 0;
+ do {
+ res = sd_cmd13(handle, &resp.cardStatus);
+ if (res != SD_OK) {
+ EMMC_TRACE(
+ "cmd13 failed before cmd16: rca 0x%0x, return %d, response 0x%0x\n",
+ handle->device->ctrl.rca, res, resp.cardStatus);
+ return res;
+ }
+
+ if (resp.cardStatus & 0x100)
+ break;
+
+ EMMC_TRACE("cmd13 rsp:0x%08x before cmd16\n", resp.cardStatus);
+
+ if (ntry > handle->device->cfg.retryLimit) {
+ EMMC_TRACE("cmd13 retry reach limit %d\n",
+ handle->device->cfg.retryLimit);
+ return SD_CMD_TIMEOUT;
+ }
+
+ ntry++;
+ EMMC_TRACE("cmd13 retry %d\n", ntry);
+
+ SD_US_DELAY(1000);
+
+ } while (1);
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_SET_BLOCKLEN, argument, options, &resp);
+
+ return res;
+}
+
+int sd_cmd17(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer)
+{
+ int res;
+ uint32_t argument, options, ntry;
+ struct sd_resp resp;
+
+ ntry = 0;
+ do {
+ res = sd_cmd13(handle, &resp.cardStatus);
+ if (res != SD_OK) {
+ EMMC_TRACE(
+ "cmd 13 failed before cmd17: rca 0x%0x, return %d, response 0x%0x\n",
+ handle->device->ctrl.rca, res, resp.cardStatus);
+ return res;
+ }
+
+ if (resp.cardStatus & 0x100)
+ break;
+
+ EMMC_TRACE("cmd13 rsp:0x%08x before cmd17\n", resp.cardStatus);
+
+ if (ntry > handle->device->cfg.retryLimit) {
+ EMMC_TRACE("cmd13 retry reach limit %d\n",
+ handle->device->cfg.retryLimit);
+ return SD_CMD_TIMEOUT;
+ }
+
+ ntry++;
+ EMMC_TRACE("cmd13 retry %d\n", ntry);
+
+ SD_US_DELAY(1000);
+
+ } while (1);
+
+ data_xfer_setup(handle, buffer, len, SD_XFER_CARD_TO_HOST);
+
+ /* send cmd and parse result */
+ argument = addr;
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_DPS_MASK | SD4_EMMC_TOP_CMD_DTDS_MASK |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK | SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ res = send_cmd(handle, SD_CMD_READ_SINGLE_BLOCK, argument, options,
+ &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ res = process_data_xfer(handle, buffer, addr, len, SD_XFER_CARD_TO_HOST);
+
+ return res;
+}
+
+int sd_cmd18(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer)
+{
+ int res;
+ uint32_t argument, options, ntry;
+ struct sd_resp resp;
+
+ ntry = 0;
+ do {
+ res = sd_cmd13(handle, &resp.cardStatus);
+ if (res != SD_OK) {
+ EMMC_TRACE(
+ "cmd 13 failed before cmd18: rca 0x%0x, return %d, response 0x%0x\n",
+ handle->device->ctrl.rca, res, resp.cardStatus);
+ return res;
+ }
+
+ if (resp.cardStatus & 0x100)
+ break;
+
+ EMMC_TRACE("cmd13 rsp:0x%08x before cmd18\n", resp.cardStatus);
+
+ if (ntry > handle->device->cfg.retryLimit) {
+ EMMC_TRACE("cmd13 retry reach limit %d\n",
+ handle->device->cfg.retryLimit);
+ return SD_CMD_TIMEOUT;
+ }
+
+ ntry++;
+ EMMC_TRACE("cmd13 retry %d\n", ntry);
+
+ SD_US_DELAY(1000);
+ } while (1);
+
+ data_xfer_setup(handle, buffer, len, SD_XFER_CARD_TO_HOST);
+
+ argument = addr;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_DPS_MASK | SD4_EMMC_TOP_CMD_DTDS_MASK |
+ SD4_EMMC_TOP_CMD_MSBS_MASK | SD4_EMMC_TOP_CMD_CCHK_EN_MASK |
+ SD4_EMMC_TOP_CMD_BCEN_MASK | SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ BIT(SD4_EMMC_TOP_CMD_ACMDEN_SHIFT);
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_READ_MULTIPLE_BLOCK, argument, options,
+ &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ res = process_data_xfer(handle, buffer, addr, len, SD_XFER_CARD_TO_HOST);
+
+ return res;
+}
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+static int card_sts_resp(struct sd_handle *handle, uint32_t *status)
+{
+ int res;
+ uint32_t ntry = 0;
+
+ do {
+ res = sd_cmd13(handle, status);
+ if (res != SD_OK) {
+ EMMC_TRACE(
+ "cmd 13 failed before cmd35: rca 0x%0x, return %d\n",
+ handle->device->ctrl.rca, res);
+ return res;
+ }
+
+ if (*status & 0x100)
+ break;
+
+ EMMC_TRACE("cmd13 rsp:0x%08x before cmd35\n", resp.cardStatus);
+
+ if (ntry > handle->device->cfg.retryLimit) {
+ EMMC_TRACE("cmd13 retry reach limit %d\n",
+ handle->device->cfg.retryLimit);
+ return SD_CMD_TIMEOUT;
+ }
+
+ ntry++;
+ EMMC_TRACE("cmd13 retry %d\n", ntry);
+
+ SD_US_DELAY(1000);
+ } while (1);
+
+ return SD_OK;
+}
+
+int sd_cmd35(struct sd_handle *handle, uint32_t start)
+{
+ int res;
+ uint32_t argument, options;
+ struct sd_resp resp;
+
+ res = card_sts_resp(handle, &resp.cardStatus);
+ if (res != SD_OK)
+ return res;
+
+ argument = start;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_ERASE_GROUP_START,
+ argument, options, &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ return res;
+}
+
+int sd_cmd36(struct sd_handle *handle, uint32_t end)
+{
+ int res;
+ uint32_t argument, options;
+ struct sd_resp resp;
+
+ res = card_sts_resp(handle, &resp.cardStatus);
+ if (res != SD_OK)
+ return res;
+
+ argument = end;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_ERASE_GROUP_END,
+ argument, options, &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ return res;
+}
+
+int sd_cmd38(struct sd_handle *handle)
+{
+ int res;
+ uint32_t argument, options;
+ struct sd_resp resp;
+
+ res = card_sts_resp(handle, &resp.cardStatus);
+ if (res != SD_OK)
+ return res;
+
+ argument = 0;
+
+ options = (SD_CMDR_RSP_TYPE_R1b_5b << SD_CMDR_RSP_TYPE_S) |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_ERASE, argument, options, &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ return res;
+}
+#endif
+
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+
+int sd_cmd24(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer)
+{
+ int res;
+ uint32_t argument, options, ntry;
+ struct sd_resp resp;
+
+ ntry = 0;
+ do {
+ res = sd_cmd13(handle, &resp.cardStatus);
+ if (res != SD_OK) {
+ EMMC_TRACE(
+ "cmd 13 failed before cmd24: rca 0x%0x, return %d, response 0x%0x\n",
+ handle->device->ctrl.rca, res, &resp.cardStatus);
+ return res;
+ }
+
+ if (resp.cardStatus & 0x100)
+ break;
+
+ EMMC_TRACE("cmd13 rsp:0x%08x before cmd24\n", resp.cardStatus);
+
+ if (ntry > handle->device->cfg.retryLimit) {
+ EMMC_TRACE("cmd13 retry reach limit %d\n",
+ handle->device->cfg.retryLimit);
+ return SD_CMD_TIMEOUT;
+ }
+
+ ntry++;
+ EMMC_TRACE("cmd13 retry %d\n", ntry);
+
+ SD_US_DELAY(1000);
+
+ } while (1);
+
+ data_xfer_setup(handle, buffer, len, SD_XFER_HOST_TO_CARD);
+
+ argument = addr;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_DPS_MASK | SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK;
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_WRITE_BLOCK, argument, options, &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ res = process_data_xfer(handle, buffer, addr, len, SD_XFER_HOST_TO_CARD);
+
+ return res;
+}
+
+int sd_cmd25(struct sd_handle *handle,
+ uint32_t addr, uint32_t len, uint8_t *buffer)
+{
+ int res = SD_OK;
+ uint32_t argument, options, ntry;
+ struct sd_resp resp;
+
+ ntry = 0;
+ do {
+ res = sd_cmd13(handle, &resp.cardStatus);
+ if (res != SD_OK) {
+ EMMC_TRACE(
+ "cmd 13 failed before cmd25: rca 0x%0x, return %d, response 0x%0x\n",
+ handle->device->ctrl.rca, res, &resp.cardStatus);
+ return res;
+ }
+
+ if (resp.cardStatus & 0x100)
+ break;
+
+ EMMC_TRACE("cmd13 rsp:0x%08x before cmd25\n", resp.cardStatus);
+
+ if (ntry > handle->device->cfg.retryLimit) {
+ EMMC_TRACE("cmd13 retry reach limit %d\n",
+ handle->device->cfg.retryLimit);
+ return SD_CMD_TIMEOUT;
+ }
+
+ ntry++;
+ EMMC_TRACE("cmd13 retry %d\n", ntry);
+
+ SD_US_DELAY(1000);
+ } while (1);
+
+ data_xfer_setup(handle, buffer, len, SD_XFER_HOST_TO_CARD);
+
+ argument = addr;
+
+ options = SD_CMDR_RSP_TYPE_R1_5_6 << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_DPS_MASK | SD4_EMMC_TOP_CMD_MSBS_MASK |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK | SD4_EMMC_TOP_CMD_BCEN_MASK |
+ SD4_EMMC_TOP_CMD_CRC_EN_MASK |
+ BIT(SD4_EMMC_TOP_CMD_ACMDEN_SHIFT);
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_CMD_WRITE_MULTIPLE_BLOCK,
+ argument, options, &resp);
+
+ if (res != SD_OK)
+ return res;
+
+ res = process_data_xfer(handle, buffer, addr, len, SD_XFER_HOST_TO_CARD);
+
+ return res;
+}
+#endif /* INCLUDE_EMMC_DRIVER_WRITE_CODE */
+
+int mmc_cmd6(struct sd_handle *handle, uint32_t argument)
+{
+ int res;
+ uint32_t options;
+ struct sd_resp resp;
+
+ options = SD_CMDR_RSP_TYPE_R1b_5b << SD_CMDR_RSP_TYPE_S |
+ SD4_EMMC_TOP_CMD_CCHK_EN_MASK | SD4_EMMC_TOP_CMD_CRC_EN_MASK;
+
+ EMMC_TRACE("Sending CMD6 with argument 0x%X\n", argument);
+
+ /* send cmd and parse result */
+ res = send_cmd(handle, SD_ACMD_SET_BUS_WIDTH, argument, options, &resp);
+
+ /*
+ * For R1b type response:
+ * controller issues a COMMAND COMPLETE interrupt when the R1
+ * response is received,
+ * then controller monitors DAT0 for busy status,
+ * controller issues a TRANSFER COMPLETE interrupt when busy signal
+ * clears.
+ */
+ wait_for_event(handle,
+ SD4_EMMC_TOP_INTR_TXDONE_MASK | SD_ERR_INTERRUPTS,
+ handle->device->cfg.wfe_retry);
+
+ if (res == SD_OK) {
+ /* Check result of Cmd6 using Cmd13 to check card status */
+
+ /* Check status using Cmd13 */
+ res = sd_cmd13(handle, &resp.cardStatus);
+
+ if (res == SD_OK) {
+ /* Check bit 7 (SWITCH_ERROR) in card status */
+ if ((resp.cardStatus & 0x80) != 0) {
+ EMMC_TRACE("cmd6 failed: SWITCH_ERROR\n");
+ res = SD_FAIL;
+ }
+ } else {
+ EMMC_TRACE("cmd13 failed after cmd6: ");
+ EMMC_TRACE("rca 0x%0x, return %d, response 0x%0x\n",
+ handle->device->ctrl.rca, res, resp.cardStatus);
+ }
+ }
+
+ return res;
+}
+
+
+#define SD_BUSY_CHECK 0x00203000
+#define DAT0_LEVEL_MASK 0x100000 /* bit20 in PSTATE */
+#define DEV_BUSY_TIMEOUT 600000 /* 60 Sec : 600000 * 100us */
+
+int send_cmd(struct sd_handle *handle, uint32_t cmdIndex, uint32_t argument,
+ uint32_t options, struct sd_resp *resp)
+{
+ int status = SD_OK;
+ uint32_t event = 0, present, timeout = 0, retry = 0, mask = 3;
+ uint32_t temp_resp[4];
+
+ if (handle == NULL) {
+ EMMC_TRACE("Invalid handle for cmd%d\n", cmdIndex);
+ return SD_INVALID_HANDLE;
+ }
+
+ mask = (SD_BUSY_CHECK & options) ? 3 : 1;
+
+RETRY_WRITE_CMD:
+ do {
+ /* Make sure it is ok to send command */
+ present =
+ chal_sd_get_present_status((CHAL_HANDLE *) handle->device);
+ timeout++;
+
+ if (present & mask)
+ SD_US_DELAY(1000);
+ else
+ break;
+
+ } while (timeout < EMMC_BUSY_CMD_TIMEOUT_MS);
+
+ if (timeout >= EMMC_BUSY_CMD_TIMEOUT_MS) {
+ status = SD_CMD_MISSING;
+ EMMC_TRACE("cmd%d timedout %dms\n", cmdIndex, timeout);
+ }
+
+ /* Reset both DAT and CMD line if only of them are stuck */
+ if (present & mask)
+ check_error(handle, SD4_EMMC_TOP_INTR_CMDERROR_MASK);
+
+ handle->device->ctrl.argReg = argument;
+ chal_sd_send_cmd((CHAL_HANDLE *) handle->device, cmdIndex,
+ handle->device->ctrl.argReg, options);
+
+ handle->device->ctrl.cmdIndex = cmdIndex;
+
+ event = wait_for_event(handle,
+ (SD4_EMMC_TOP_INTR_CMDDONE_MASK |
+ SD_ERR_INTERRUPTS),
+ handle->device->cfg.wfe_retry);
+
+ if (handle->device->ctrl.cmdStatus == SD_CMD_MISSING) {
+ retry++;
+
+ if (retry >= handle->device->cfg.retryLimit) {
+ status = SD_CMD_MISSING;
+ EMMC_TRACE("cmd%d retry reaches the limit %d\n",
+ cmdIndex, retry);
+ } else {
+ /* reset both DAT & CMD line if one of them is stuck */
+ present = chal_sd_get_present_status((CHAL_HANDLE *)
+ handle->device);
+
+ if (present & mask)
+ check_error(handle,
+ SD4_EMMC_TOP_INTR_CMDERROR_MASK);
+
+ EMMC_TRACE("cmd%d retry %d PSTATE[0x%08x]\n",
+ cmdIndex, retry,
+ chal_sd_get_present_status((CHAL_HANDLE *)
+ handle->device));
+ goto RETRY_WRITE_CMD;
+ }
+ }
+
+ if (handle->device->ctrl.cmdStatus == SD_OK) {
+ if (resp != NULL) {
+ status =
+ chal_sd_get_response((CHAL_HANDLE *) handle->device,
+ temp_resp);
+ process_cmd_response(handle,
+ handle->device->ctrl.cmdIndex,
+ temp_resp[0], temp_resp[1],
+ temp_resp[2], temp_resp[3], resp);
+ }
+
+ /* Check Device busy after CMD */
+ if ((cmdIndex == 5) || (cmdIndex == 6) || (cmdIndex == 7) ||
+ (cmdIndex == 28) || (cmdIndex == 29) || (cmdIndex == 38)) {
+
+ timeout = 0;
+ do {
+ present =
+ chal_sd_get_present_status((CHAL_HANDLE *)
+ handle->device);
+
+ timeout++;
+
+ /* Dat[0]:bit20 low means device busy */
+ if ((present & DAT0_LEVEL_MASK) == 0) {
+ EMMC_TRACE("Device busy: ");
+ EMMC_TRACE(
+ "cmd%d arg:0x%08x: PSTATE[0x%08x]\n",
+ cmdIndex, argument, present);
+ SD_US_DELAY(100);
+ } else {
+ break;
+ }
+ } while (timeout < DEV_BUSY_TIMEOUT);
+ }
+ } else if (handle->device->ctrl.cmdStatus &&
+ handle->device->ctrl.cmdStatus != SD_CMD_MISSING) {
+ retry++;
+ status = check_error(handle, handle->device->ctrl.cmdStatus);
+
+ EMMC_TRACE(
+ "cmd%d error: cmdStatus:0x%08x error_status:0x%08x\n",
+ cmdIndex, handle->device->ctrl.cmdStatus, status);
+
+ if ((handle->device->ctrl.cmdIndex == 1) ||
+ (handle->device->ctrl.cmdIndex == 5)) {
+ status = event;
+ } else if ((handle->device->ctrl.cmdIndex == 7) ||
+ (handle->device->ctrl.cmdIndex == 41)) {
+ status = event;
+ } else if ((status == SD_ERROR_RECOVERABLE) &&
+ (retry < handle->device->cfg.retryLimit)) {
+ EMMC_TRACE("cmd%d recoverable error ", cmdIndex);
+ EMMC_TRACE("retry %d PSTATE[0x%08x].\n", retry,
+ chal_sd_get_present_status((CHAL_HANDLE *)
+ handle->device));
+ goto RETRY_WRITE_CMD;
+ } else {
+ EMMC_TRACE("cmd%d retry reaches the limit %d\n",
+ cmdIndex, retry);
+ status = event;
+ }
+ }
+
+ handle->device->ctrl.blkReg = 0;
+ /* clear error status for next command */
+ handle->device->ctrl.cmdStatus = 0;
+
+ return status;
+}
diff --git a/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c b/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c
new file mode 100644
index 0000000..68f93e7
--- /dev/null
+++ b/drivers/brcm/emmc/emmc_pboot_hal_memory_drv.c
@@ -0,0 +1,621 @@
+/*
+ * Copyright (c) 2016 - 2020, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <emmc_api.h>
+#include <cmn_plat_util.h>
+
+#define MAX_CMD_RETRY 10
+
+#if EMMC_USE_DMA
+#define USE_DMA 1
+#else
+#define USE_DMA 0
+#endif
+
+struct emmc_global_buffer emmc_global_buf;
+struct emmc_global_buffer *emmc_global_buf_ptr = &emmc_global_buf;
+
+struct emmc_global_vars emmc_global_vars;
+struct emmc_global_vars *emmc_global_vars_ptr = &emmc_global_vars;
+
+static struct sd_handle *sdio_gethandle(void);
+static uint32_t sdio_idle(struct sd_handle *p_sdhandle);
+
+static uint32_t sdio_read(struct sd_handle *p_sdhandle,
+ uintptr_t mem_addr,
+ uintptr_t storage_addr,
+ size_t storage_size,
+ size_t bytes_to_read);
+
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+static uint32_t sdio_write(struct sd_handle *p_sdhandle,
+ uintptr_t mem_addr,
+ uintptr_t data_addr,
+ size_t bytes_to_write);
+#endif
+
+static struct sd_handle *sdio_init(void);
+static int32_t bcm_emmc_card_ready_state(struct sd_handle *p_sdhandle);
+
+static void init_globals(void)
+{
+ memset((void *)emmc_global_buf_ptr, 0, sizeof(*emmc_global_buf_ptr));
+ memset((void *)emmc_global_vars_ptr, 0, sizeof(*emmc_global_vars_ptr));
+}
+
+/*
+ * This function is used to change partition
+ */
+uint32_t emmc_partition_select(uint32_t partition)
+{
+ int rc;
+ struct sd_handle *sd_handle = sdio_gethandle();
+
+ if (sd_handle->device == 0) {
+ EMMC_TRACE("eMMC init is not done");
+ return 0;
+ }
+
+ switch (partition) {
+ case EMMC_BOOT_PARTITION1:
+ rc = set_boot_config(sd_handle,
+ SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT1);
+ EMMC_TRACE(
+ "Change to Boot Partition 1 result:%d (0 means SD_OK)\n",
+ rc);
+ break;
+
+ case EMMC_BOOT_PARTITION2:
+ rc = set_boot_config(sd_handle,
+ SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_BOOT2);
+ EMMC_TRACE(
+ "Change to Boot Partition 2 result:%d (0 means SD_OK)\n",
+ rc);
+ break;
+
+ case EMMC_USE_CURRENT_PARTITION:
+ rc = SD_OK;
+ EMMC_TRACE("Stay on current partition");
+ break;
+
+ case EMMC_USER_AREA:
+ default:
+ rc = set_boot_config(sd_handle,
+ SDIO_HW_EMMC_EXT_CSD_BOOT_ACC_USER);
+ EMMC_TRACE("Change to User area result:%d (0 means SD_OK)\n",
+ rc);
+ break;
+
+ }
+ return (rc == SD_OK);
+}
+
+/*
+ * Initialize emmc controller for eMMC
+ * Returns 0 on fail condition
+ */
+uint32_t bcm_emmc_init(bool card_rdy_only)
+{
+ struct sd_handle *p_sdhandle;
+ uint32_t result = 0;
+
+ EMMC_TRACE("Enter emmc_controller_init()\n");
+
+ /* If eMMC is already initialized, skip init */
+ if (emmc_global_vars_ptr->init_done)
+ return 1;
+
+ init_globals();
+
+ p_sdhandle = sdio_init();
+
+ if (p_sdhandle == NULL) {
+ ERROR("eMMC init failed");
+ return result;
+ }
+
+ if (card_rdy_only) {
+ /* Put the card in Ready state, Not complete init */
+ result = bcm_emmc_card_ready_state(p_sdhandle);
+ return !result;
+ }
+
+ if (sdio_idle(p_sdhandle) == EMMC_BOOT_OK) {
+ set_config(p_sdhandle, SD_NORMAL_SPEED, MAX_CMD_RETRY, USE_DMA,
+ SD_DMA_BOUNDARY_256K, EMMC_BLOCK_SIZE,
+ EMMC_WFE_RETRY);
+
+ if (!select_blk_sz(p_sdhandle,
+ p_sdhandle->device->cfg.blockSize)) {
+ emmc_global_vars_ptr->init_done = 1;
+ result = 1;
+ } else {
+ ERROR("Select Block Size failed\n");
+ }
+ } else {
+ ERROR("eMMC init failed");
+ }
+
+ /* Initialization is failed, so deinit HW setting */
+ if (result == 0)
+ emmc_deinit();
+
+ return result;
+}
+
+/*
+ * Function to de-init SDIO controller for eMMC
+ */
+void emmc_deinit(void)
+{
+ emmc_global_vars_ptr->init_done = 0;
+ emmc_global_vars_ptr->sdHandle.card = 0;
+ emmc_global_vars_ptr->sdHandle.device = 0;
+}
+
+/*
+ * Read eMMC memory
+ * Returns read_size
+ */
+uint32_t emmc_read(uintptr_t mem_addr, uintptr_t storage_addr,
+ size_t storage_size, size_t bytes_to_read)
+{
+ struct sd_handle *sd_handle = sdio_gethandle();
+
+ if (sd_handle->device == 0) {
+ EMMC_TRACE("eMMC init is not done");
+ return 0;
+ }
+
+ return sdio_read(sdio_gethandle(), mem_addr, storage_addr,
+ storage_size, bytes_to_read);
+}
+
+#ifdef INCLUDE_EMMC_DRIVER_ERASE_CODE
+#define EXT_CSD_ERASE_GRP_SIZE 224
+
+static int emmc_block_erase(uintptr_t mem_addr, size_t blocks)
+{
+ struct sd_handle *sd_handle = sdio_gethandle();
+
+ if (sd_handle->device == 0) {
+ ERROR("eMMC init is not done");
+ return -1;
+ }
+
+ return erase_card(sdio_gethandle(), mem_addr, blocks);
+}
+
+int emmc_erase(uintptr_t mem_addr, size_t num_of_blocks, uint32_t partition)
+{
+ int err = 0;
+ size_t block_count = 0, blocks = 0;
+ size_t erase_group = 0;
+
+ erase_group =
+ emmc_global_buf_ptr->u.Ext_CSD_storage[EXT_CSD_ERASE_GRP_SIZE]*1024;
+
+ INFO("eMMC Erase Group Size=0x%lx\n", erase_group);
+
+ emmc_partition_select(partition);
+
+ while (block_count < num_of_blocks) {
+ blocks = ((num_of_blocks - block_count) > erase_group) ?
+ erase_group : (num_of_blocks - block_count);
+ err = emmc_block_erase(mem_addr + block_count, blocks);
+ if (err)
+ break;
+
+ block_count += blocks;
+ }
+
+ if (err == 0)
+ INFO("eMMC Erase of partition %d successful\n", partition);
+ else
+ ERROR("eMMC Erase of partition %d Failed(%i)\n", partition, err);
+
+ return err;
+}
+#endif
+
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+/*
+ * Write to eMMC memory
+ * Returns written_size
+ */
+uint32_t emmc_write(uintptr_t mem_addr, uintptr_t data_addr,
+ size_t bytes_to_write)
+{
+ struct sd_handle *sd_handle = sdio_gethandle();
+
+ if (sd_handle->device == 0) {
+ EMMC_TRACE("eMMC init is not done");
+ return 0;
+ }
+
+ return sdio_write(sd_handle, mem_addr, data_addr, bytes_to_write);
+}
+#endif
+
+/*
+ * Send SDIO Cmd
+ * Return 0 for pass condition
+ */
+uint32_t send_sdio_cmd(uint32_t cmdIndex, uint32_t argument,
+ uint32_t options, struct sd_resp *resp)
+{
+ struct sd_handle *sd_handle = sdio_gethandle();
+
+ if (sd_handle->device == 0) {
+ EMMC_TRACE("eMMC init is not done");
+ return 1;
+ }
+
+ return send_cmd(sd_handle, cmdIndex, argument, options, resp);
+}
+
+
+/*
+ * This function return SDIO handle
+ */
+struct sd_handle *sdio_gethandle(void)
+{
+ return &emmc_global_vars_ptr->sdHandle;
+}
+
+/*
+ * Initialize SDIO controller
+ */
+struct sd_handle *sdio_init(void)
+{
+ uint32_t SDIO_base;
+ struct sd_handle *p_sdhandle = &emmc_global_vars_ptr->sdHandle;
+
+ SDIO_base = EMMC_CTRL_REGS_BASE_ADDR;
+
+ if (SDIO_base == SDIO0_EMMCSDXC_SYSADDR)
+ EMMC_TRACE(" ---> for SDIO 0 Controller\n\n");
+
+ memset(p_sdhandle, 0, sizeof(struct sd_handle));
+
+ p_sdhandle->device = &emmc_global_vars_ptr->sdDevice;
+ p_sdhandle->card = &emmc_global_vars_ptr->sdCard;
+
+ memset(p_sdhandle->device, 0, sizeof(struct sd_dev));
+ memset(p_sdhandle->card, 0, sizeof(struct sd_card_info));
+
+ if (chal_sd_start((CHAL_HANDLE *) p_sdhandle->device,
+ SD_PIO_MODE, SDIO_base, SDIO_base) != SD_OK)
+ return NULL;
+
+ set_config(p_sdhandle, SD_NORMAL_SPEED, MAX_CMD_RETRY, SD_DMA_OFF,
+ SD_DMA_BOUNDARY_4K, EMMC_BLOCK_SIZE, EMMC_WFE_RETRY);
+
+ return &emmc_global_vars_ptr->sdHandle;
+}
+
+uint32_t sdio_idle(struct sd_handle *p_sdhandle)
+{
+ reset_card(p_sdhandle);
+
+ SD_US_DELAY(1000);
+
+ if (init_card(p_sdhandle, SD_CARD_DETECT_MMC) != SD_OK) {
+ reset_card(p_sdhandle);
+ reset_host_ctrl(p_sdhandle);
+ return EMMC_BOOT_NO_CARD;
+ }
+
+ return EMMC_BOOT_OK;
+}
+
+/*
+ * This function read eMMC
+ */
+uint32_t sdio_read(struct sd_handle *p_sdhandle,
+ uintptr_t mem_addr,
+ uintptr_t storage_addr,
+ size_t storage_size, size_t bytes_to_read)
+{
+ uint32_t offset = 0, blockAddr, readLen = 0, rdCount;
+ uint32_t remSize, manual_copy_size;
+ uint8_t *outputBuf = (uint8_t *) storage_addr;
+ const size_t blockSize = p_sdhandle->device->cfg.blockSize;
+
+ VERBOSE("EMMC READ: dst=0x%lx, src=0x%lx, size=0x%lx\n",
+ storage_addr, mem_addr, bytes_to_read);
+
+ if (storage_size < bytes_to_read)
+ /* Don't have sufficient storage to complete the operation */
+ return 0;
+
+ /* Range check non high capacity memory */
+ if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) {
+ if (mem_addr > 0x80000000)
+ return 0;
+ }
+
+ /* High capacity card use block address mode */
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) {
+ blockAddr = (uint32_t) (mem_addr / blockSize);
+ offset = (uint32_t) (mem_addr - (blockAddr * blockSize));
+ } else {
+ blockAddr = (uint32_t) (mem_addr / blockSize) * blockSize;
+ offset = (uint32_t) (mem_addr - blockAddr);
+ }
+
+ remSize = bytes_to_read;
+
+ rdCount = 0;
+
+ /* Process first unaligned block of MAX_READ_LENGTH */
+ if (offset > 0) {
+ if (!read_block(p_sdhandle, emmc_global_buf_ptr->u.tempbuf,
+ blockAddr, SD_MAX_READ_LENGTH)) {
+
+ if (remSize < (blockSize - offset)) {
+ rdCount += remSize;
+ manual_copy_size = remSize;
+ remSize = 0; /* read is done */
+ } else {
+ remSize -= (blockSize - offset);
+ rdCount += (blockSize - offset);
+ manual_copy_size = blockSize - offset;
+ }
+
+ /* Check for overflow */
+ if (manual_copy_size > storage_size ||
+ (((uintptr_t)outputBuf + manual_copy_size) >
+ (storage_addr + storage_size))) {
+ ERROR("EMMC READ: Overflow 1\n");
+ return 0;
+ }
+
+ memcpy(outputBuf,
+ (void *)((uintptr_t)
+ (emmc_global_buf_ptr->u.tempbuf + offset)),
+ manual_copy_size);
+
+ /* Update Physical address */
+ outputBuf += manual_copy_size;
+
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ blockAddr++;
+ else
+ blockAddr += blockSize;
+ } else {
+ return 0;
+ }
+ }
+
+ while (remSize >= blockSize) {
+
+ if (remSize >= SD_MAX_BLK_TRANSFER_LENGTH)
+ readLen = SD_MAX_BLK_TRANSFER_LENGTH;
+ else
+ readLen = (remSize / blockSize) * blockSize;
+
+ /* Check for overflow */
+ if ((rdCount + readLen) > storage_size ||
+ (((uintptr_t) outputBuf + readLen) >
+ (storage_addr + storage_size))) {
+ ERROR("EMMC READ: Overflow\n");
+ return 0;
+ }
+
+ if (!read_block(p_sdhandle, outputBuf, blockAddr, readLen)) {
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ blockAddr += (readLen / blockSize);
+ else
+ blockAddr += readLen;
+
+ remSize -= readLen;
+ rdCount += readLen;
+
+ /* Update Physical address */
+ outputBuf += readLen;
+ } else {
+ return 0;
+ }
+ }
+
+ /* process the last unaligned block reading */
+ if (remSize > 0) {
+ if (!read_block(p_sdhandle, emmc_global_buf_ptr->u.tempbuf,
+ blockAddr, SD_MAX_READ_LENGTH)) {
+
+ rdCount += remSize;
+ /* Check for overflow */
+ if (rdCount > storage_size ||
+ (((uintptr_t) outputBuf + remSize) >
+ (storage_addr + storage_size))) {
+ ERROR("EMMC READ: Overflow\n");
+ return 0;
+ }
+
+ memcpy(outputBuf,
+ emmc_global_buf_ptr->u.tempbuf, remSize);
+
+ /* Update Physical address */
+ outputBuf += remSize;
+ } else {
+ rdCount = 0;
+ }
+ }
+
+ return rdCount;
+}
+
+#ifdef INCLUDE_EMMC_DRIVER_WRITE_CODE
+static uint32_t sdio_write(struct sd_handle *p_sdhandle, uintptr_t mem_addr,
+ uintptr_t data_addr, size_t bytes_to_write)
+{
+
+ uint32_t offset, blockAddr, writeLen, wtCount = 0;
+ uint32_t remSize, manual_copy_size = 0;
+
+ uint8_t *inputBuf = (uint8_t *)data_addr;
+
+ /* range check non high capacity memory */
+ if ((p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) == 0) {
+ if (mem_addr > 0x80000000)
+ return 0;
+ }
+
+ /* the high capacity card use block address mode */
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY) {
+ blockAddr =
+ (uint32_t)(mem_addr / p_sdhandle->device->cfg.blockSize);
+ offset =
+ (uint32_t)(mem_addr -
+ blockAddr * p_sdhandle->device->cfg.blockSize);
+ } else {
+ blockAddr =
+ ((uint32_t)mem_addr / p_sdhandle->device->cfg.blockSize) *
+ p_sdhandle->device->cfg.blockSize;
+ offset = (uint32_t) mem_addr - blockAddr;
+ }
+
+ remSize = bytes_to_write;
+
+ wtCount = 0;
+
+ /* process first unaligned block */
+ if (offset > 0) {
+ if (!read_block(p_sdhandle, emmc_global_buf_ptr->u.tempbuf,
+ blockAddr, p_sdhandle->device->cfg.blockSize)) {
+
+ if (remSize <
+ (p_sdhandle->device->cfg.blockSize - offset))
+ manual_copy_size = remSize;
+ else
+ manual_copy_size =
+ p_sdhandle->device->cfg.blockSize - offset;
+
+ memcpy((void *)((uintptr_t)
+ (emmc_global_buf_ptr->u.tempbuf + offset)),
+ inputBuf,
+ manual_copy_size);
+
+ /* Update Physical address */
+
+ if (!write_block(p_sdhandle,
+ emmc_global_buf_ptr->u.tempbuf,
+ blockAddr,
+ p_sdhandle->device->cfg.blockSize)) {
+
+ if (remSize <
+ (p_sdhandle->device->cfg.blockSize -
+ offset)) {
+ wtCount += remSize;
+ manual_copy_size = remSize;
+ remSize = 0; /* read is done */
+ } else {
+ remSize -=
+ (p_sdhandle->device->cfg.blockSize -
+ offset);
+ wtCount +=
+ (p_sdhandle->device->cfg.blockSize -
+ offset);
+ manual_copy_size =
+ p_sdhandle->device->cfg.blockSize -
+ offset;
+ }
+
+ inputBuf += manual_copy_size;
+
+ if (p_sdhandle->device->ctrl.ocr &
+ SD_CARD_HIGH_CAPACITY)
+ blockAddr++;
+ else
+ blockAddr +=
+ p_sdhandle->device->cfg.blockSize;
+ } else
+ return 0;
+ } else {
+ return 0;
+ }
+ }
+
+ /* process block writing */
+ while (remSize >= p_sdhandle->device->cfg.blockSize) {
+ if (remSize >= SD_MAX_READ_LENGTH) {
+ writeLen = SD_MAX_READ_LENGTH;
+ } else {
+ writeLen =
+ (remSize / p_sdhandle->device->cfg.blockSize) *
+ p_sdhandle->device->cfg.blockSize;
+ }
+
+ if (!write_block(p_sdhandle, inputBuf, blockAddr, writeLen)) {
+ if (p_sdhandle->device->ctrl.ocr & SD_CARD_HIGH_CAPACITY)
+ blockAddr +=
+ (writeLen /
+ p_sdhandle->device->cfg.blockSize);
+ else
+ blockAddr += writeLen;
+
+ remSize -= writeLen;
+ wtCount += writeLen;
+ inputBuf += writeLen;
+ } else {
+ return 0;
+ }
+ }
+
+ /* process the last unaligned block reading */
+ if (remSize > 0) {
+ if (!read_block(p_sdhandle,
+ emmc_global_buf_ptr->u.tempbuf,
+ blockAddr, p_sdhandle->device->cfg.blockSize)) {
+
+ memcpy(emmc_global_buf_ptr->u.tempbuf,
+ inputBuf, remSize);
+
+ /* Update Physical address */
+
+ if (!write_block(p_sdhandle,
+ emmc_global_buf_ptr->u.tempbuf,
+ blockAddr,
+ p_sdhandle->device->cfg.blockSize)) {
+ wtCount += remSize;
+ inputBuf += remSize;
+ } else {
+ return 0;
+ }
+ } else {
+ wtCount = 0;
+ }
+ }
+
+ return wtCount;
+}
+#endif
+
+/*
+ * Function to put the card in Ready state by sending CMD0 and CMD1
+ */
+static int32_t bcm_emmc_card_ready_state(struct sd_handle *p_sdhandle)
+{
+ int32_t result = 0;
+ uint32_t argument = MMC_CMD_IDLE_RESET_ARG; /* Exit from Boot mode */
+
+ if (p_sdhandle) {
+ send_sdio_cmd(SD_CMD_GO_IDLE_STATE, argument, 0, NULL);
+
+ result = reset_card(p_sdhandle);
+ if (result != SD_OK) {
+ EMMC_TRACE("eMMC Reset error\n");
+ return SD_RESET_ERROR;
+ }
+ SD_US_DELAY(2000);
+ result = mmc_cmd1(p_sdhandle);
+ }
+
+ return result;
+}