| commit | afaeb0d0b1c01e1c7e9bab7f85a850f7a29cfdcd | [log] [tgz] |
|---|---|---|
| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | Tue Sep 04 17:49:32 2018 +0530 |
| committer | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | Tue Sep 04 17:49:32 2018 +0530 |
| tree | 9ebef5b241db7c0225781283dc019cbb8fe9beaf | |
| parent | 7c6516a1ebba9e18c300efb8f062285332ab287a [diff] |
zynqmp: pm_service: Ignore enable/disable of PLL type clocks PLL type clock is enabled by FSBL on boot-up. PMUFW enable/disable them based on their user count. So, it should not be handled from ATF. Put PLL type clock into bypass and reset mode only while changing PLL rate (FBDIV). Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>