| commit | ad818161b65405c1b8e67d15a1f5f9daf9a48da6 | [log] [tgz] |
|---|---|---|
| author | Jacky Bai <ping.bai@nxp.com> | Wed Jul 22 16:00:50 2020 +0800 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Wed Aug 19 09:46:11 2020 +0000 |
| tree | b94d263df4f33e46abed97f48a0cb342134a8fb1 | |
| parent | 534563edba2f9754e35c83a15ba68ea7e053d68f [diff] [blame] |
plat: imx8m: Correct the imr mask reg offset The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74
diff --git a/plat/imx/imx8m/imx8mn/include/gpc_reg.h b/plat/imx/imx8m/imx8mn/include/gpc_reg.h index fd10438..8a81368 100644 --- a/plat/imx/imx8m/imx8mn/include/gpc_reg.h +++ b/plat/imx/imx8m/imx8mn/include/gpc_reg.h
@@ -106,4 +106,6 @@ #define GPUMIX_PGC 0xdc0 #define DISPMIX_PGC 0xe80 +#define IRQ_IMR_NUM U(4) + #endif /* GPC_REG_H */