Merge changes from topic "srm/Errata_ABI_El3" into integration
* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface
diff --git a/Makefile b/Makefile
index b54787d..e5063de 100644
--- a/Makefile
+++ b/Makefile
@@ -414,6 +414,10 @@
WARNINGS += -Wunused-but-set-variable -Wmaybe-uninitialized \
-Wpacked-bitfield-compat -Wshift-overflow=2 \
-Wlogical-op
+
+# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105523
+TF_CFLAGS += $(call cc_option, --param=min-pagesize=0)
+
else
# using clang
WARNINGS += -Wshift-overflow -Wshift-sign-overflow \
@@ -912,11 +916,20 @@
endif
endif
+ifneq (${ENABLE_SME_FOR_NS},0)
+ ifeq (${ENABLE_SVE_FOR_NS},0)
+ $(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
+ endif
+endif
+
# Secure SME/SVE requires the non-secure component as well
ifeq (${ENABLE_SME_FOR_SWD},1)
ifeq (${ENABLE_SME_FOR_NS},0)
$(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS")
endif
+ ifeq (${ENABLE_SVE_FOR_SWD},0)
+ $(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD")
+ endif
endif
ifeq (${ENABLE_SVE_FOR_SWD},1)
ifeq (${ENABLE_SVE_FOR_NS},0)
@@ -1058,6 +1071,7 @@
# Variables for use with PRINT_MEMORY_MAP
PRINT_MEMORY_MAP_PATH ?= tools/memory
PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py
+INVERTED_MEMMAP ?= 0
# Variables for use with documentation build using Sphinx tool
DOCS_PATH ?= docs
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index f380a49..d7c9a52 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -105,12 +105,10 @@
ifneq (${ENABLE_SME_FOR_NS},0)
BL31_SOURCES += lib/extensions/sme/sme.c
-BL31_SOURCES += lib/extensions/sve/sve.c
-else
+endif
ifneq (${ENABLE_SVE_FOR_NS},0)
BL31_SOURCES += lib/extensions/sve/sve.c
endif
-endif
ifneq (${ENABLE_MPAM_FOR_LOWER_ELS},0)
BL31_SOURCES += lib/extensions/mpam/mpam.c
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index cd52460..0ba0a7a 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -67,7 +67,7 @@
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
-| plat_convert_pk() function | Nov'22 | 2.9 | Platform conversion to manage specific PK hash |
+| None at this time | | | |
+--------------------------------+-------------+---------+---------------------------------------------------------+
Removal of Deprecated Drivers
@@ -82,8 +82,6 @@
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
-| io_dummy driver | Nov'22 | 2.9 | No more used by any upstream platform |
-+--------------------------------+-------------+---------+---------------------------------------------------------+
| CryptoCell-712 | 2.9 | 3.0 | No longer maintained. |
+--------------------------------+-------------+---------+---------------------------------------------------------+
| CryptoCell-713 | 2.9 | 3.0 | No longer maintained. |
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index 97f3550..2c9b76a 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -1759,6 +1759,10 @@
DRAM
0xffffffff +----------+
+ | EL3 TZC |
+ 0xffe00000 |----------| (secure)
+ | AP TZC |
+ 0xff000000 +----------+
: :
0x82100000 |----------|
|HW_CONFIG |
@@ -1800,6 +1804,10 @@
DRAM
0xffffffff +--------------+
+ | EL3 TZC |
+ 0xffe00000 |--------------| (secure)
+ | AP TZC |
+ 0xff000000 +--------------+
: :
0x82100000 |--------------|
| HW_CONFIG |
@@ -1840,7 +1848,10 @@
DRAM
0xffffffff +----------+
- | BL32 | (secure)
+ | EL3 TZC |
+ 0xffe00000 |----------| (secure)
+ | AP TZC |
+ | (BL32) |
0xff000000 +----------+
| |
0x82100000 |----------|
@@ -1880,6 +1891,20 @@
::
+ DRAM
+ 0xFFFFFFFF +----------+
+ | SCP TZC |
+ 0xFFE00000 |----------|
+ | EL3 TZC |
+ 0xFFC00000 |----------| (secure)
+ | AP TZC |
+ 0xFF000000 +----------+
+ | |
+ : : (non-secure)
+ | |
+ 0x80000000 +----------+
+
+
Flash0
0x0C000000 +----------+
: :
@@ -1909,9 +1934,14 @@
::
DRAM
- 0xFFE00000 +----------+
- | BL32 | (secure)
- 0xFF000000 |----------|
+ 0xFFFFFFFF +----------+
+ | SCP TZC |
+ 0xFFE00000 |----------|
+ | EL3 TZC |
+ 0xFFC00000 |----------| (secure)
+ | AP TZC |
+ | (BL32) |
+ 0xFF000000 +----------+
| |
: : (non-secure)
| |
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 0e3b2fc..6dd4ed2 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -436,7 +436,8 @@
(SME), SVE, and FPU/SIMD for the non-secure world only. These features share
registers so are enabled together. Using this option without
ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
- world to trap to EL3. SME is an optional architectural feature for AArch64
+ world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a
+ superset of SVE. SME is an optional architectural feature for AArch64
and TF-A support is experimental. At this time, this build option cannot be
used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
build with these options will fail. This flag can take the values 0 to 2, to
@@ -450,10 +451,9 @@
align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
- Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS
- must also be set to use this. If enabling this, the secure world MUST
- handle context switching for SME, SVE, and FPU/SIMD registers to ensure that
- no data is leaked to non-secure world. This is experimental. Default is 0.
+ Extension for secure world. Used along with SVE and FPU/SIMD.
+ ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this.
+ This is experimental. Default is 0.
- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
extensions. This is an optional architectural feature for AArch64.
@@ -469,17 +469,15 @@
This is to avoid corruption of the Non-secure world data in the Z-registers
which are aliased by the SIMD and FP registers. The build option is not
compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
- assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled.
- This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
- mechanism. The default is 2 but is automatically disabled when
- ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE.
- At this time, this build option cannot be used on systems that have SPM_MM
- enabled.
+ assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS``
+ enabled. This flag can take the values 0 to 2, to align with the
+ ``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be
+ used on systems that have SPM_MM enabled. The default is 1.
- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
SVE is an optional architectural feature for AArch64. Note that this option
- requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it
- is automatically disabled when the target architecture is AArch32.
+ requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
+ automatically disabled when the target architecture is AArch32.
- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
checks in GCC. Allowed values are "all", "strong", "default" and "none". The
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index bf10ecf..a3f8cc8 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 11.3.Rel1 (from the `Arm Developer website`_)
+- GCC >= 12.2.Rel1 (from the `Arm Developer website`_)
You will need the targets ``arm-none-eabi`` and ``aarch64-none-elf`` for
AArch32 and AArch64 builds respectively.
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 168d0eb..2c74800 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -330,6 +330,8 @@
/* Enable Group1 Secure interrupts */
write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
IGRPEN1_EL3_ENABLE_G1S_BIT);
+ /* and restore the original */
+ write_scr_el3(scr_el3);
isb();
/* Add DSB to ensure visibility of System register writes */
dsb();
diff --git a/drivers/io/io_dummy.c b/drivers/io/io_dummy.c
deleted file mode 100644
index 4f0cda6..0000000
--- a/drivers/io/io_dummy.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_dummy.h>
-#include <drivers/io/io_storage.h>
-
-struct file_state {
- int in_use;
- size_t size;
-};
-
-static struct file_state current_file = {0};
-
-/* Identify the device type as dummy */
-static io_type_t device_type_dummy(void)
-{
- return IO_TYPE_DUMMY;
-}
-
-/* Dummy device functions */
-static int dummy_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info);
-static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
- io_entity_t *entity);
-static int dummy_block_len(io_entity_t *entity, size_t *length);
-static int dummy_block_read(io_entity_t *entity, uintptr_t buffer,
- size_t length, size_t *length_read);
-static int dummy_block_close(io_entity_t *entity);
-static int dummy_dev_close(io_dev_info_t *dev_info);
-
-
-static const io_dev_connector_t dummy_dev_connector = {
- .dev_open = dummy_dev_open
-};
-
-
-static const io_dev_funcs_t dummy_dev_funcs = {
- .type = device_type_dummy,
- .open = dummy_block_open,
- .seek = NULL,
- .size = dummy_block_len,
- .read = dummy_block_read,
- .write = NULL,
- .close = dummy_block_close,
- .dev_init = NULL,
- .dev_close = dummy_dev_close,
-};
-
-
-static const io_dev_info_t dummy_dev_info = {
- .funcs = &dummy_dev_funcs,
- .info = (uintptr_t)NULL
-};
-
-
-/* Open a connection to the dummy device */
-static int dummy_dev_open(const uintptr_t dev_spec __attribute__((unused)),
- io_dev_info_t **dev_info)
-{
- assert(dev_info != NULL);
- *dev_info = (io_dev_info_t *)&dummy_dev_info;
-
- return 0;
-}
-
-
-/* Close a connection to the dummy device */
-static int dummy_dev_close(io_dev_info_t *dev_info)
-{
- return 0;
-}
-
-
-/* Open a file on the dummy device */
-static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec,
- io_entity_t *entity)
-{
- int result;
- const io_block_spec_t *block_spec = (io_block_spec_t *)spec;
-
- if (current_file.in_use == 0) {
- assert(block_spec != NULL);
- assert(entity != NULL);
-
- current_file.in_use = 1;
- current_file.size = block_spec->length;
- entity->info = (uintptr_t)¤t_file;
- result = 0;
- } else {
- WARN("A Dummy device is already active. Close first.\n");
- result = -ENOMEM;
- }
-
- return result;
-}
-
-
-/* Return the size of a file on the dummy device */
-static int dummy_block_len(io_entity_t *entity, size_t *length)
-{
- assert(entity != NULL);
- assert(length != NULL);
-
- *length = ((struct file_state *)entity->info)->size;
-
- return 0;
-}
-
-
-/* Read data from a file on the dummy device */
-static int dummy_block_read(io_entity_t *entity, uintptr_t buffer,
- size_t length, size_t *length_read)
-{
- assert(length_read != NULL);
-
- *length_read = length;
-
- return 0;
-}
-
-
-/* Close a file on the dummy device */
-static int dummy_block_close(io_entity_t *entity)
-{
- assert(entity != NULL);
-
- entity->info = 0;
- current_file.in_use = 0;
-
- return 0;
-}
-
-
-/* Exported functions */
-
-/* Register the dummy driver with the IO abstraction */
-int register_io_dev_dummy(const io_dev_connector_t **dev_con)
-{
- int result;
-
- assert(dev_con != NULL);
-
- result = io_register_device(&dummy_dev_info);
- if (result == 0)
- *dev_con = &dummy_dev_connector;
-
- return result;
-}
diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c
index 2bbb31d..5dfad9a 100644
--- a/drivers/st/crypto/stm32_pka.c
+++ b/drivers/st/crypto/stm32_pka.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,6 +19,11 @@
#include <platform_def.h>
+#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \
+ !PKA_USE_NIST_P521
+#error "At least one ECDSA curve needs to be selected"
+#endif
+
/*
* For our comprehension in this file
* _len are in BITs
diff --git a/include/drivers/io/io_dummy.h b/include/drivers/io/io_dummy.h
deleted file mode 100644
index edfc699..0000000
--- a/include/drivers/io/io_dummy.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef IO_DUMMY_H
-#define IO_DUMMY_H
-
-int register_io_dev_dummy(const struct io_dev_connector **dev_con);
-
-#endif /* IO_DUMMY_H */
diff --git a/include/drivers/io/io_storage.h b/include/drivers/io/io_storage.h
index 8f30ed0..3179383 100644
--- a/include/drivers/io/io_storage.h
+++ b/include/drivers/io/io_storage.h
@@ -19,7 +19,6 @@
IO_TYPE_INVALID,
IO_TYPE_SEMIHOSTING,
IO_TYPE_MEMMAP,
- IO_TYPE_DUMMY,
IO_TYPE_FIRMWARE_IMAGE_PACKAGE,
IO_TYPE_BLOCK,
IO_TYPE_MTD,
diff --git a/include/drivers/st/stm32_pka.h b/include/drivers/st/stm32_pka.h
index ad4690a..34b3f6b 100644
--- a/include/drivers/st/stm32_pka.h
+++ b/include/drivers/st/stm32_pka.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,24 +9,11 @@
#include <stdint.h>
-#if !PKA_USE_NIST_P256 && !PKA_USE_BRAINPOOL_P256R1 && !PKA_USE_BRAINPOOL_P256T1 && \
- !PKA_USE_NIST_P521
-#error "At least one ECDSA curve needs to be selected"
-#endif
-
enum stm32_pka_ecdsa_curve_id {
-#if PKA_USE_NIST_P256
PKA_NIST_P256,
-#endif
-#if PKA_USE_BRAINPOOL_P256R1
PKA_BRAINPOOL_P256R1,
-#endif
-#if PKA_USE_BRAINPOOL_P256T1
PKA_BRAINPOOL_P256T1,
-#endif
-#if PKA_USE_NIST_P521
PKA_NIST_P521,
-#endif
};
struct stm32_pka_platdata {
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index e38b34d..744e4f9 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -517,12 +517,13 @@
amu_enable(el2_unused, ctx);
}
- /* Enable SME, SVE, and FPU/SIMD for non-secure world. */
+ /* Enable SVE and FPU/SIMD */
+ if (is_feat_sve_supported()) {
+ sve_enable(ctx);
+ }
+
if (is_feat_sme_supported()) {
sme_enable(ctx);
- } else if (is_feat_sve_supported()) {
- /* Enable SVE and FPU/SIMD for non-secure world. */
- sve_enable(ctx);
}
if (is_feat_mpam_supported()) {
@@ -553,22 +554,7 @@
static void manage_extensions_secure(cpu_context_t *ctx)
{
#if IMAGE_BL31
-
- if (is_feat_sme_supported()) {
- if (ENABLE_SME_FOR_SWD) {
- /*
- * Enable SME, SVE, FPU/SIMD in secure context, secure manager
- * must ensure SME, SVE, and FPU/SIMD context properly managed.
- */
- sme_enable(ctx);
- } else {
- /*
- * Disable SME, SVE, FPU/SIMD in secure context so non-secure
- * world can safely use the associated registers.
- */
- sme_disable(ctx);
- }
- } else if (is_feat_sve_supported()) {
+ if (is_feat_sve_supported()) {
if (ENABLE_SVE_FOR_SWD) {
/*
* Enable SVE and FPU in secure context, secure manager must
@@ -585,6 +571,21 @@
}
}
+ if (is_feat_sme_supported()) {
+ if (ENABLE_SME_FOR_SWD) {
+ /*
+ * Enable SME, SVE, FPU/SIMD in secure context, secure manager
+ * must ensure SME, SVE, and FPU/SIMD context properly managed.
+ */
+ sme_enable(ctx);
+ } else {
+ /*
+ * Disable SME, SVE, FPU/SIMD in secure context so non-secure
+ * world can safely use the associated registers.
+ */
+ sme_disable(ctx);
+ }
+ }
#endif /* IMAGE_BL31 */
}
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index f888d12..3423dba 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -65,9 +65,6 @@
/* Reset CPTR_EL3 value. */
write_cptr_el3(cptr_el3);
isb();
-
- /* Enable SVE/FPU in addition to SME. */
- sve_enable(context);
}
void sme_disable(cpu_context_t *context)
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 0c82a71..3bce3a5 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -73,6 +73,7 @@
# Convenience function for verifying option has a boolean value
# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
define assert_boolean
+ $(if $($(1)),,$(error $(1) must not be empty))
$(if $(filter-out 0 1,$($1)),$(error $1 must be boolean))
endef
@@ -104,6 +105,12 @@
$(shell if $(LD) $(1) -v >/dev/null 2>&1; then echo $(1); fi )
endef
+# Convenience function to check for a given compiler option. A call to
+# $(call cc_option, --no-XYZ) will return --no-XYZ if supported by the compiler
+define cc_option
+ $(shell if $(CC) $(1) -c -x c /dev/null -o /dev/null >/dev/null 2>&1; then echo $(1); fi )
+endef
+
# CREATE_SEQ is a recursive function to create sequence of numbers from 1 to
# $(2) and assign the sequence to $(1)
define CREATE_SEQ
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 26fd68d..4165470 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -407,14 +407,6 @@
# SME defaults to disabled
ENABLE_SME_FOR_NS := 0
ENABLE_SME_FOR_SWD := 0
-
-# If SME is enabled then force SVE off
-ifneq (${ENABLE_SME_FOR_NS},0)
- override ENABLE_SVE_FOR_NS := 0
- override ENABLE_SVE_FOR_SWD := 0
-endif
-
-# SME2 defaults to disabled
ENABLE_SME2_FOR_NS := 0
SANITIZE_UB := off
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 4f87306..6fcf080 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -100,6 +100,8 @@
MULTI_CONSOLE_API := 1
+ARM_DISABLE_TRUSTED_WDOG := 1
+
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/aarch32/nonlpae_tables.c
# Use translation tables library v1 when using Cortex-A5
diff --git a/plat/arm/board/fvp/aarch64/fvp_ras.c b/plat/arm/board/fvp/aarch64/fvp_ras.c
index 759f6d0..f9b9634 100644
--- a/plat/arm/board/fvp/aarch64/fvp_ras.c
+++ b/plat/arm/board/fvp/aarch64/fvp_ras.c
@@ -4,12 +4,63 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <inttypes.h>
+#include <stdint.h>
+
#include <lib/extensions/ras.h>
+#include <services/sdei.h>
+
+#ifdef PLATFORM_TEST_RAS_FFH
+static int injected_fault_handler(const struct err_record_info *info,
+ int probe_data, const struct err_handler_data *const data)
+{
+ uint64_t status;
+ int ret;
+
+ /*
+ * The faulting error record is already selected by the SER probe
+ * function.
+ */
+ status = read_erxstatus_el1();
+
+ ERROR("Fault reported by system error record %d on 0x%lx: status=0x%" PRIx64 "\n",
+ probe_data, read_mpidr_el1(), status);
+ ERROR(" exception reason=%u syndrome=0x%" PRIx64 "\n", data->ea_reason,
+ data->flags);
+
+ /* Clear error */
+ write_erxstatus_el1(status);
+
+ ret = sdei_dispatch_event(5000);
+ if (ret < 0) {
+ ERROR("Can't dispatch event to SDEI\n");
+ panic();
+ } else {
+ INFO("SDEI event dispatched\n");
+ }
+
+ return 0;
+}
+
+void plat_handle_uncontainable_ea(void)
+{
+ /* Do not change the string, CI expects it. Wait forever */
+ INFO("Injected Uncontainable Error\n");
+ while (true) {
+ wfe();
+ }
+}
+#endif
struct ras_interrupt fvp_ras_interrupts[] = {
};
struct err_record_info fvp_err_records[] = {
+#ifdef PLATFORM_TEST_RAS_FFH
+ /* Record for injected fault */
+ ERR_RECORD_SYSREG_V1(0, 2, ras_err_ser_probe_sysreg,
+ injected_fault_handler, NULL),
+#endif
};
REGISTER_ERR_RECORD_INFO(fvp_err_records);
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 79d7451..9e72ba0 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -397,7 +397,17 @@
#define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT
#define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT
#else
-#define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
+ #if PLATFORM_TEST_RAS_FFH
+ #define PLAT_ARM_PRIVATE_SDEI_EVENTS \
+ ARM_SDEI_PRIVATE_EVENTS, \
+ SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \
+ SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \
+ SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL)
+ #else
+ #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS
+ #endif
#define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS
#endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 363d15d..863eb0e 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -505,6 +505,11 @@
PSCI_OS_INIT_MODE := 1
+ifeq (${SPD},spmd)
+BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
+endif
+
+# Test specific macros, keep them at bottom of this file
$(eval $(call add_define,PLATFORM_TEST_EA_FFH))
ifeq (${PLATFORM_TEST_EA_FFH}, 1)
ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0)
@@ -513,8 +518,11 @@
BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c
endif
-ifeq (${SPD},spmd)
-BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c
+$(eval $(call add_define,PLATFORM_TEST_RAS_FFH))
+ifeq (${PLATFORM_TEST_RAS_FFH}, 1)
+ ifeq (${RAS_EXTENSION}, 0)
+ $(error "PLATFORM_TEST_RAS_FFH expects RAS_EXTENSION to be 1")
+ endif
endif
ifeq (${ERRATA_ABI_SUPPORT}, 1)
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
index 0b792ab..c8a2d4c 100644
--- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_bus26m.c
@@ -53,6 +53,7 @@
static struct mt_irqremain *refer2remain_irq;
static struct mt_spm_cond_tables cond_bus26m = {
+ .name = "bus26m",
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
@@ -175,7 +176,7 @@
(IS_PLAT_SUSPEND_ID(state_id) || (state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
-static int update_rc_condition(const void *val)
+static int update_rc_condition(int state_id, const void *val)
{
const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
const struct mt_spm_cond_tables *tlb_check =
@@ -185,7 +186,7 @@
return MT_RM_STATUS_BAD;
}
- status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_bus26m_res : NULL);
status.all_pll_dump = mt_spm_dump_all_pll(tlb, tlb_check,
@@ -279,7 +280,7 @@
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
- res = update_rc_condition(val);
+ res = update_rc_condition(state_id, val);
break;
case PLAT_RC_UPDATE_REMAIN_IRQS:
update_rc_remain_irqs(val);
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
index d1a2435..82b38ad 100644
--- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_dram.c
@@ -37,6 +37,7 @@
#define CONSTRAINT_DRAM_RESOURCE_REQ (MT_SPM_SYSPLL | MT_SPM_INFRA | MT_SPM_26M)
static struct mt_spm_cond_tables cond_dram = {
+ .name = "dram",
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
@@ -104,7 +105,7 @@
(state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
-static int update_rc_condition(const void *val)
+static int update_rc_condition(int state_id, const void *val)
{
const struct mt_spm_cond_tables *tlb = (const struct mt_spm_cond_tables *)val;
const struct mt_spm_cond_tables *tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
@@ -113,7 +114,7 @@
return MT_RM_STATUS_BAD;
}
- status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_dram_res : NULL);
return MT_RM_STATUS_OK;
@@ -185,7 +186,7 @@
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
- res = update_rc_condition(val);
+ res = update_rc_condition(state_id, val);
break;
case PLAT_RC_CLKBUF_STATUS:
update_rc_clkbuf_status(val);
diff --git a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
index 700f500..5359c7c 100644
--- a/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
+++ b/plat/mediatek/drivers/spm/mt8188/constraints/mt_spm_rc_syspll.c
@@ -49,6 +49,7 @@
static unsigned short ext_status_syspll;
static struct mt_spm_cond_tables cond_syspll = {
+ .name = "syspll",
.table_cg = {
0xFF5DD002, /* MTCMOS1 */
0x0000003C, /* MTCMOS2 */
@@ -113,7 +114,7 @@
(state_id == MT_PLAT_PWR_STATE_SYSTEM_BUS)));
}
-static int update_rc_condition(const void *val)
+static int update_rc_condition(int state_id, const void *val)
{
int res = MT_RM_STATUS_OK;
@@ -126,7 +127,7 @@
return MT_RM_STATUS_BAD;
}
- status.is_cond_block = mt_spm_cond_check(tlb, tlb_check,
+ status.is_cond_block = mt_spm_cond_check(state_id, tlb, tlb_check,
(status.is_valid & MT_SPM_RC_VALID_COND_LATCH) ?
&cond_syspll_res : NULL);
return res;
@@ -228,7 +229,7 @@
switch (type) {
case PLAT_RC_UPDATE_CONDITION:
- res = update_rc_condition(val);
+ res = update_rc_condition(state_id, val);
break;
case PLAT_RC_CLKBUF_STATUS:
update_rc_clkbuf_status(val);
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
index fe6e598..bed55c9 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.c
@@ -126,12 +126,14 @@
#define PLL_APLL4 MT_LP_TZ_APMIXEDSYS(0x404)
#define PLL_APLL5 MT_LP_TZ_APMIXEDSYS(0x418)
-unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res)
{
unsigned int b_res = 0U;
unsigned int i;
+ bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
if ((src == NULL) || (dest == NULL)) {
return SPM_COND_CHECK_FAIL;
@@ -140,6 +142,11 @@
for (i = 0; i < PLAT_SPM_COND_MAX; i++) {
if (res != NULL) {
res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+ if (is_system_suspend && ((res->table_cg[i]) != 0U)) {
+ INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+ dest->name, i, idle_cg_info[i].addr,
+ res->table_cg[i]);
+ }
if ((res->table_cg[i]) != 0U) {
b_res |= BIT(i);
@@ -161,6 +168,10 @@
b_res |= SPM_COND_CHECK_BLOCKED_PLL;
}
+ if (is_system_suspend && ((b_res) != 0U)) {
+ INFO("suspend: %s total blocked = 0x%08x\n", dest->name, b_res);
+ }
+
return b_res;
}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
index 793d5e8..d93df57 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_cond.h
@@ -75,13 +75,15 @@
#define SPM_COND_CHECK_FAIL BIT(31)
struct mt_spm_cond_tables {
+ char *name;
unsigned int table_cg[PLAT_SPM_COND_MAX];
unsigned int table_pll;
unsigned int table_all_pll;
void *priv;
};
-unsigned int mt_spm_cond_check(const struct mt_spm_cond_tables *src,
+unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
const struct mt_spm_cond_tables *dest,
struct mt_spm_cond_tables *res);
unsigned int mt_spm_dump_all_pll(const struct mt_spm_cond_tables *src,
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
index bcb2df6..395448a 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_conservation.c
@@ -61,6 +61,14 @@
__spm_send_cpu_wakeup_event();
+ INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+ cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+ (mmio_read_32(PCM_TIMER_VAL) / 32768));
+ INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+ pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+ mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+ mmio_read_32(PWR_STATUS_2ND));
+
return ret;
}
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
index b38a6d0..5eb16b3 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.c
@@ -24,6 +24,7 @@
wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta)
{
+ uint32_t bk_vtcxo_dur, spm_26m_off_pct;
wake_reason_t wr = WR_UNKNOWN;
if (wakesta == NULL) {
@@ -46,6 +47,33 @@
}
}
+ INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->tr.comm.r12, wakesta->r12_ext, wakesta->tr.comm.r13, wakesta->tr.comm.debug_flag,
+ wakesta->tr.comm.debug_flag1);
+ INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+ wakesta->tr.comm.raw_sta, wakesta->md32pcm_wakeup_sta,
+ wakesta->md32pcm_event_sta, wakesta->idle_sta,
+ wakesta->cg_check_sta);
+ INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+ wakesta->tr.comm.req_sta0, wakesta->tr.comm.req_sta1, wakesta->tr.comm.req_sta2,
+ wakesta->tr.comm.req_sta3, wakesta->tr.comm.req_sta4, wakesta->isr);
+ INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+ wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+ INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+ wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+ INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+ wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+ wakesta->tr.comm.b_sw_flag0, wakesta->tr.comm.b_sw_flag1, wakesta->src_req);
+ INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+ wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+ mmio_read_32(SYS_TIMER_VALUE_H));
+
+ if (wakesta->tr.comm.timer_out != 0U) {
+ bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+ spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->tr.comm.timer_out;
+ INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+ }
+
return wr;
}
@@ -331,6 +359,18 @@
wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7); /* SPM_SW_RSV_7 */
wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8); /* SPM_SW_RSV_8 */
+ /* record below spm info for debug */
+ wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+ /* get HW CG check status */
+ wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+ wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+ wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+ wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+ wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+ wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
/* get ISR status */
wakesta->isr = mmio_read_32(SPM_IRQ_STA);
@@ -338,6 +378,9 @@
wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+ /* get CLK SETTLE */
+ wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
/* check abort */
wakesta->is_abort = wakesta->tr.comm.debug_flag & DEBUG_ABORT_MASK;
wakesta->is_abort |= wakesta->tr.comm.debug_flag1 & DEBUG_ABORT_MASK_1;
diff --git a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
index c719caf..5e3390f 100644
--- a/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
+++ b/plat/mediatek/drivers/spm/mt8188/mt_spm_internal.h
@@ -628,11 +628,19 @@
uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
uint32_t wake_misc; /* SPM_SW_RSV_5 */
uint32_t idle_sta; /* SUBSYS_IDLE_STA */
+ uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
uint32_t isr; /* SPM_IRQ_STA */
+ uint32_t clk_settle; /* SPM_CLK_SETTLE */
+ uint32_t src_req; /* SPM_SRC_REQ */
uint32_t log_index;
uint32_t is_abort;
+ uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
+ uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
+ uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
+ uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
+ uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
};
struct spm_lp_scen {
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 7b3129c..8b8d76b 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -139,3 +139,6 @@
# Later QEMU versions support SME and SVE.
ENABLE_SVE_FOR_NS := 2
ENABLE_SME_FOR_NS := 2
+
+# QEMU 7.2+ has support for FGT and Linux needs it enabled to boot on max
+ENABLE_FEAT_FGT := 2
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 1d93983..55423ae 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -73,6 +73,9 @@
endif
endif
+PKA_USE_NIST_P256 ?= 0
+PKA_USE_BRAINPOOL_P256T1 ?= 0
+
ifeq ($(AARCH32_SP),sp_min)
# Disable Neon support: sp_min runtime may conflict with non-secure world
TF_CFLAGS += -mfloat-abi=soft
@@ -158,7 +161,6 @@
$(sort \
PKA_USE_BRAINPOOL_P256T1 \
PKA_USE_NIST_P256 \
- PLAT_TBBR_IMG_DEF \
STM32MP_CRYPTO_ROM_LIB \
STM32MP_DDR_32BIT_INTERFACE \
STM32MP_DDR_DUAL_AXI_PORT \