Merge "fix(docs): replace "ARM-TF" with "TF-A" in diagrams" into integration
diff --git a/changelog.yaml b/changelog.yaml
index 6f2458e..7d8760e 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -241,6 +241,9 @@
- title: RD-N2
scope: rdn2
+ - title: RD-Fremont
+ scope: rdfremont
+
deprecated:
- board/rdn2
diff --git a/drivers/arm/rse/rse_comms.mk b/drivers/arm/rse/rse_comms.mk
index a1abc6a..3b87fe2 100644
--- a/drivers/arm/rse/rse_comms.mk
+++ b/drivers/arm/rse/rse_comms.mk
@@ -31,4 +31,5 @@
endif
PLAT_INCLUDES += -Idrivers/arm/rse \
- -Idrivers/arm/mhu
+ -Idrivers/arm/mhu \
+ -Iinclude/lib/psa
diff --git a/include/lib/psa/cca_attestation.h b/include/lib/psa/cca_attestation.h
new file mode 100644
index 0000000..4062dde
--- /dev/null
+++ b/include/lib/psa/cca_attestation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CCA_ATTESTATION_H
+#define CCA_ATTESTATION_H
+
+#include <stdint.h>
+#include <psa/crypto_types.h>
+
+psa_status_t
+cca_attestation_get_realm_key(uintptr_t buf, size_t *len, unsigned int type);
+
+psa_status_t
+cca_attestation_get_plat_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size);
+
+#endif /* CCA_ATTESTATION_H */
diff --git a/lib/psa/cca_attestation.c b/lib/psa/cca_attestation.c
new file mode 100644
index 0000000..9e9e0c1
--- /dev/null
+++ b/lib/psa/cca_attestation.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <psa/crypto_sizes.h>
+#include <psa/crypto_types.h>
+#include <psa/crypto_values.h>
+
+#include <cca_attestation.h>
+#include <delegated_attestation.h>
+#include <services/rmmd_svc.h>
+
+psa_status_t
+cca_attestation_get_realm_key(uintptr_t buf, size_t *len, unsigned int type)
+{
+ size_t dak_len;
+ psa_status_t ret = PSA_SUCCESS;
+
+ /*
+ * Current RMM implementations only support the public key size for
+ * ECC-P384, i.e. ATTEST_KEY_CURVE_ECC_SECP384R1 attestation key.
+ *
+ * This ECC key has following properties:
+ * ecc_curve: 0x12 (PSA_ECC_FAMILY_SECP_R1)
+ * key_bits: 384
+ * hash_alg: 0x02000009 (PSA_ALG_SHA_256)
+ */
+ assert(type == ATTEST_KEY_CURVE_ECC_SECP384R1);
+
+ ret = rse_delegated_attest_get_delegated_key(PSA_ECC_FAMILY_SECP_R1,
+ 384, (uint8_t *)buf, *len,
+ &dak_len, PSA_ALG_SHA_256);
+ if (ret != PSA_SUCCESS) {
+ return ret;
+ }
+
+ if (dak_len != PSA_BITS_TO_BYTES(384)) {
+ return PSA_ERROR_INVALID_ARGUMENT;
+ }
+
+ *len = dak_len;
+
+ return ret;
+}
+
+psa_status_t
+cca_attestation_get_plat_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size)
+{
+ size_t token_len = 0;
+ psa_status_t ret = PSA_SUCCESS;
+
+ ret = rse_delegated_attest_get_token((const uint8_t *)hash, hash_size,
+ (uint8_t *)buf, *len, &token_len);
+ if (ret != PSA_SUCCESS) {
+ return ret;
+ }
+
+ *len = token_len;
+
+ return ret;
+}
diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c
index 655a4d2..4a2572f 100644
--- a/plat/arm/board/common/board_arm_trusted_boot.c
+++ b/plat/arm/board/common/board_arm_trusted_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -219,6 +219,15 @@
} else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
nv_ctr_addr = (uint32_t *)FCONF_GET_PROPERTY(cot, nv_cntr_addr,
NON_TRUSTED_NV_CTR_ID);
+#if defined(ARM_COT_cca)
+ } else if (strcmp(oid, CCA_FW_NVCOUNTER_OID) == 0) {
+ /*
+ * Use Trusted NV counter for platforms that don't support
+ * the CCA NV Counter.
+ */
+ nv_ctr_addr = (uint32_t *)FCONF_GET_PROPERTY(cot, nv_cntr_addr,
+ TRUSTED_NV_CTR_ID);
+#endif
} else {
return 1;
}
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
new file mode 100644
index 0000000..bd2e682
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_def3.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS specific definitions for the third generation of
+ * platforms.
+ */
+
+#ifndef NRD_CSS_DEF3_H
+#define NRD_CSS_DEF3_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* Shared RAM */
+#define NRD_CSS_SHARED_SRAM_BASE UL(0x00000000)
+
+/* General Peripherals */
+#define NRD_CSS_PERIPH_BASE UL(0x20000000)
+#define NRD_CSS_PERIPH_SIZE UL(0x20000000)
+
+/* System NCI */
+#define NRD_CSS_SYSTEM_NCI_BASE UL(0x20000000)
+#define NRD_CSS_SYSTEM_NCI_SIZE UL(0x04000000)
+
+/* Debug NIC */
+#define NRD_CSS_DEBUG_NIC_BASE UL(0x28000000)
+#define NRD_CSS_DEBUG_NIC_SIZE UL(0x01000000)
+
+/* NS UART */
+#define NRD_CSS_NS_UART_BASE UL(0x2A400000)
+#define NRD_CSS_NS_UART_SIZE UL(0x00010000)
+
+/* Secure UART */
+#define NRD_CSS_SECURE_UART_BASE UL(0x2A410000)
+#define NRD_CSS_SECURE_UART_SIZE UL(0x00010000)
+
+/* Realm UART */
+#define NRD_CSS_REALM_UART_BASE UL(0x2A420000)
+#define NRD_CSS_REALM_UART_SIZE UL(0x00010000)
+
+/* Generic Refclk */
+#define NRD_CSS_GENERIC_REFCLK_BASE UL(0x2A430000)
+#define NRD_CSS_GENERIC_REFCLK_SIZE UL(0x00010000)
+
+/* NS Watchdog */
+#define NRD_CSS_AP_NS_WDOG_BASE UL(0x2A440000)
+#define NRD_CSS_AP_NS_WDOG_SIZE UL(0x00020000)
+
+/* Root Watchdog */
+#define NRD_CSS_AP_ROOT_WDOG_BASE UL(0x2A460000)
+#define NRD_CSS_AP_ROOT_WDOG_SIZE UL(0x00020000)
+
+/* Secure Watchdog */
+#define NRD_CSS_AP_SECURE_WDOG_BASE UL(0x2A480000)
+#define NRD_CSS_AP_SECURE_WDOG_SIZE UL(0x00020000)
+
+/* SID */
+#define NRD_CSS_SID_BASE UL(0x2A4A0000)
+#define NRD_CSS_SID_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - AP */
+#define NRD_CSS_SECURE_SRAM_ERB_AP_BASE UL(0x2A4B0000)
+#define NRD_CSS_SECURE_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - AP */
+#define NRD_CSS_NS_SRAM_ERB_AP_BASE UL(0x2A4C0000)
+#define NRD_CSS_NS_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - AP */
+#define NRD_CSS_ROOT_SRAM_ERB_AP_BASE UL(0x2A4D0000)
+#define NRD_CSS_ROOT_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - AP */
+#define NRD_CSS_REALM_SRAM_ERB_AP_BASE UL(0x2A4E0000)
+#define NRD_CSS_REALM_SRAM_ERB_AP_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - SCP */
+#define NRD_CSS_SECURE_SRAM_ERB_SCP_BASE UL(0x2A4F0000)
+#define NRD_CSS_SECURE_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - SCP */
+#define NRD_CSS_NS_SRAM_ERB_SCP_BASE UL(0x2A500000)
+#define NRD_CSS_NS_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - SCP */
+#define NRD_CSS_ROOT_SRAM_ERB_SCP_BASE UL(0x2A510000)
+#define NRD_CSS_ROOT_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - SCP */
+#define NRD_CSS_REALM_SRAM_ERB_SCP_BASE UL(0x2A520000)
+#define NRD_CSS_REALM_SRAM_ERB_SCP_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - MCP */
+#define NRD_CSS_SECURE_SRAM_ERB_MCP_BASE UL(0x2A530000)
+#define NRD_CSS_SECURE_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - MCP */
+#define NRD_CSS_NS_SRAM_ERB_MCP_BASE UL(0x2A540000)
+#define NRD_CSS_NS_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - MCP */
+#define NRD_CSS_ROOT_SRAM_ERB_MCP_BASE UL(0x2A550000)
+#define NRD_CSS_ROOT_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - MCP */
+#define NRD_CSS_REALM_SRAM_ERB_MCP_BASE UL(0x2A560000)
+#define NRD_CSS_REALM_SRAM_ERB_MCP_SIZE UL(0x00010000)
+
+/* SRAM Secure Error Record Block - RSE */
+#define NRD_CSS_SECURE_SRAM_ERB_RSE_BASE UL(0x2A570000)
+#define NRD_CSS_SECURE_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* SRAM NS Error Record Block - RSE */
+#define NRD_CSS_NS_SRAM_ERB_RSE_BASE UL(0x2A580000)
+#define NRD_CSS_NS_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* SRAM Root Error Record Block - RSE */
+#define NRD_CSS_ROOT_SRAM_ERB_RSE_BASE UL(0x2A590000)
+#define NRD_CSS_ROOT_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* SRAM Realm Error Record Block - RSE */
+#define NRD_CSS_REALM_SRAM_ERB_RSE_BASE UL(0x2A5A0000)
+#define NRD_CSS_REALM_SRAM_ERB_RSE_SIZE UL(0x00010000)
+
+/* RSE SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5B0000)
+#define NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* RSE SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_RSE_NS_SRAM_ERB_RSM_BASE UL(0x2A5C0000)
+#define NRD_CSS_RSE_NS_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* SCP SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5D0000)
+#define NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* SCP SRAM NS Error Record Block - RSM */
+#define NRD_CSS_SCP_NS_SRAM_ERB_RSM_BASE UL(0x2A5E0000)
+#define NRD_CSS_SCP_NS_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* MCP SRAM Secure Error Record Block - RSM */
+#define NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_BASE UL(0x2A5F0000)
+#define NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* MCP SRAM NS Error Record Block - RSM */
+#define NRD_CSS_MCP_NS_SRAM_ERB_RSM_BASE UL(0x2A600000)
+#define NRD_CSS_MCP_NS_SRAM_ERB_RSM_SIZE UL(0x00010000)
+
+/* CNTCTL Refclk Readframe */
+#define NRD_CSS_CNTCTL_REFCLK_READFRAME_BASE UL(0x2A800000)
+#define NRD_CSS_CNTCTL_REFCLK_READFRAME_SIZE UL(0x00020000)
+
+/* CNTCTL base */
+#define NRD_CSS_SYS_TIMCTL_BASE UL(0x2A810000)
+
+/* Secure Timer */
+#define NRD_CSS_SECURE_TIMER_CTL_BASE UL(0x2A820000)
+#define NRD_CSS_SECURE_TIMER_CTL_SIZE UL(0x00010000)
+
+/* NS Timer */
+#define NRD_CSS_NS_TIMER_CTL_BASE UL(0x2A830000)
+#define NRD_CSS_NS_TIMER_CTL_SIZE UL(0x00010000)
+
+/* AP - SCP NS MHU */
+#define NRD_CSS_AP_SCP_NS_MHU_BASE UL(0x2A900000)
+#define NRD_CSS_AP_SCP_NS_MHU_SIZE UL(0x00020000)
+
+/* AP - SCP Secure MHU */
+#define NRD_CSS_AP_SCP_SECURE_MHU_BASE UL(0x2A920000)
+#define NRD_CSS_AP_SCP_SECURE_MHU_SIZE UL(0x00020000)
+
+/* AP - SCP Root MHU */
+#define NRD_CSS_AP_SCP_ROOT_MHU_BASE UL(0x2A940000)
+#define NRD_CSS_AP_SCP_ROOT_MHU_SIZE UL(0x00020000)
+
+/* AP - MCP NS MHU */
+#define NRD_CSS_AP_MCP_NS_MHU_BASE UL(0x2AA00000)
+#define NRD_CSS_AP_MCP_NS_MHU_SIZE UL(0x00020000)
+
+/* AP - MCP Secure MHU */
+#define NRD_CSS_AP_MCP_SECURE_MHU_BASE UL(0x2AA20000)
+#define NRD_CSS_AP_MCP_SECURE_MHU_SIZE UL(0x00020000)
+
+/* AP - MCP Root MHU */
+#define NRD_CSS_AP_MCP_ROOT_MHU_BASE UL(0x2AA40000)
+#define NRD_CSS_AP_MCP_ROOT_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE NS MHU */
+#define NRD_CSS_AP_RSE_NS_MHU_BASE UL(0x2AB00000)
+#define NRD_CSS_AP_RSE_NS_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE Secure MHU */
+#define NRD_CSS_AP_RSE_SECURE_MHU_BASE UL(0x2AB20000)
+#define NRD_CSS_AP_RSE_SECURE_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE Root MHU */
+#define NRD_CSS_AP_RSE_ROOT_MHU_BASE UL(0x2AB40000)
+#define NRD_CSS_AP_RSE_ROOT_MHU_SIZE UL(0x00020000)
+
+/* AP - RSE Realm MHU */
+#define NRD_CSS_AP_RSE_REALM_MHU_BASE UL(0x2AB60000)
+#define NRD_CSS_AP_RSE_REALM_MHU_SIZE UL(0x00020000)
+
+/* SCP - MCP - RSE Cross chip MHU */
+#define NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_BASE UL(0x2AC00000)
+#define NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_SIZE UL(0x00120000)
+
+/* Synchronization Master Tupdate */
+#define NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_BASE UL(0x2B100000)
+#define NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_SIZE UL(0x00030000)
+
+/* AP - RSE NS MHU */
+#define NRD_CSS_STM_SYSTEM_ITS_BASE UL(0x2CF00000)
+#define NRD_CSS_STM_SYSTEM_ITS_SIZE UL(0x02100000)
+
+/* SCP - MCP - RSE Shared SRAM */
+#define NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_BASE UL(0x2F000000)
+#define NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_SIZE UL(0x00400000)
+
+/* GIC base */
+#define NRD_CSS_GIC_BASE UL(0x30000000)
+#define NRD_CSS_GIC_SIZE UL(0x08000000)
+
+/* CMN */
+#define NRD_CSS_CMN_BASE ULL(0x100000000)
+#define NRD_CSS_CMN_SIZE UL(0x40000000)
+
+/* LCP Peripherals */
+#define NRD_CSS_LCP_PERIPHERAL_BASE ULL(0x200000000)
+#define NRD_CSS_LCP_PERIPHERAL_SIZE UL(0x40000000)
+
+/* DDR IO */
+#define NRD_CSS_DDR_IO_BASE ULL(0x240000000)
+#define NRD_CSS_DDR_IO_SIZE UL(0x40000000)
+
+/* SMMU & NCI IO */
+#define NRD_CSS_SMMU_NCI_IO_BASE ULL(0x280000000)
+#define NRD_CSS_SMMU_NCI_IO_SIZE UL(0x60000000)
+
+/* GPC SMMU */
+#define NRD_CSS_GPC_SMMUV3_BASE UL(0x300000000)
+#define NRD_CSS_GPC_SMMUV3_SIZE UL(0x8000000)
+
+/* DRAM1 */
+#define NRD_CSS_DRAM1_BASE UL(0x80000000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_BASE ULL(0x8080000000)
+
+/*******************************************************************************
+ * MHUv3 related definitions
+ ******************************************************************************/
+
+#define MHU_V3_MBX_FRAME_OFFSET UL(0x10000)
+
+/* MHUv3 Postbox and Mailbox register frame base */
+#define AP_RSE_ROOT_MHU_V3_PBX NRD_CSS_AP_RSE_ROOT_MHU_BASE
+#define AP_RSE_ROOT_MHU_V3_MBX NRD_CSS_AP_RSE_ROOT_MHU_BASE + \
+ MHU_V3_MBX_FRAME_OFFSET
+
+#define AP_RSE_SECURE_MHU_V3_PBX NRD_CSS_AP_RSE_SECURE_MHU_BASE
+#define AP_RSE_SECURE_MHU_V3_MBX NRD_CSS_AP_RSE_SECURE_MHU_BASE + \
+ MHU_V3_MBX_FRAME_OFFSET
+
+#endif /* NRD_CSS_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
new file mode 100644
index 0000000..1b92ec2
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_css_fw_def3.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the CSS-firmware specific definitions for the third
+ * generation of platforms.
+ */
+
+#ifndef NRD_CSS_FW_DEF3_H
+#define NRD_CSS_FW_DEF3_H
+
+#include <nrd_css_def3.h>
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */
+
+#define NRD_CSS_BL1_RO_BASE NRD_CSS_SHARED_SRAM_BASE
+#define NRD_CSS_BL1_RO_SIZE UL(0x00019000)
+
+# define NRD_CSS_BL2_SIZE UL(0x30000)
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
+ * and BL1-RW. NRD_BL31_SIZE - is tuned with respect to the actual BL31
+ * PROGBITS size which is around 64-68KB at the time this change is being made.
+ * A buffer of ~35KB is added to account for future expansion of the image,
+ * making it a total of 100KB.
+ */
+#define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
+
+#define NRD_CSS_DRAM1_CARVEOUT_SIZE UL(0x0C000000) /* 117MB */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
+
+/*******************************************************************************
+ * Watchdog config
+ ******************************************************************************/
+
+#define NRD_CSS_AP_SECURE_WDOG_TIMEOUT UL(100)
+
+/*******************************************************************************
+ * RMM Console Config
+ ******************************************************************************/
+
+#define NRD_CSS_RMM_CONSOLE_BASE NRD_CSS_REALM_UART_BASE
+#define NRD_CSS_RMM_CONSOLE_BAUD ARM_CONSOLE_BAUDRATE
+#define NRD_CSS_RMM_CONSOLE_CLK_IN_HZ UL(14745600)
+#define NRD_CSS_RMM_CONSOLE_NAME "pl011"
+#define NRD_CSS_RMM_CONSOLE_COUNT UL(1)
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_CSS_PERIPH_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_CSS_PERIPH_BASE, \
+ NRD_CSS_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define NRD_CSS_SHARED_RAM_MMAP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ ARM_SHARED_RAM_BASE, \
+ ARM_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define NRD_CSS_GPC_SMMU_SMMUV3_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_CSS_GPC_SMMUV3_BASE, \
+ NRD_CSS_GPC_SMMUV3_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define NRD_CSS_BL1_RW_MMAP \
+ MAP_REGION_FLAT( \
+ BL1_RW_BASE, \
+ BL1_RW_LIMIT - BL1_RW_BASE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define NRD_CSS_NS_DRAM1_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define NRD_CSS_GPT_L1_DRAM_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_L1_GPT_BASE, \
+ ARM_L1_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define NRD_CSS_EL3_RMM_SHARED_MEM_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_EL3_RMM_SHARED_BASE, \
+ ARM_EL3_RMM_SHARED_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#define NRD_CSS_RMM_REGION_MMAP \
+ MAP_REGION_FLAT( \
+ ARM_REALM_BASE, \
+ ARM_REALM_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#endif /* NRD_CSS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
new file mode 100644
index 0000000..f9a62ae
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_pas_def3.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_PAS_DEF3_H
+#define NRD_PAS_DEF3_H
+
+#ifndef __ASSEMBLER__
+#include <stddef.h>
+#include <lib/gpt_rme/gpt_rme.h>
+#endif
+
+#include <nrd_css_def3.h>
+
+/*****************************************************************************
+ * PAS regions used to initialize the Granule Protection Table (GPT)
+ ****************************************************************************/
+
+/*
+ * =====================================================================
+ * Base Addr |Size |L? GPT |PAS |Content |
+ * =====================================================================
+ * 0x00000000 |256MB |L0 GPT |ANY |SHARED RAM |
+ * 0x0FFFFFFF | | | |AP EXPANSION |
+ * ---------------------------------------------------------------------
+ * 0x20000000 |64MB |L1 GPT |ROOT |SYSTEM NCI |
+ * 0x23FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x28000000 |16MB |L1 GPT |SECURE |DEBUG NIC |
+ * 0x28FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A400000 |64KB |L1 GPT |NS |NS UART |
+ * 0x2A40FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A410000 |64KB |L1 GPT |SECURE |SECURE UART |
+ * 0x2A41FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A420000 |64KB |L1 GPT |REALM |REALM UART |
+ * 0x2A42FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A430000 |64KB |L1 GPT |SECURE |GENERIC REFCLK |
+ * 0x2A43FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A440000 |128KB |L1 GPT |NS |AP NS WDOG |
+ * 0x2A45FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A460000 |128KB |L1 GPT |ROOT |AP ROOT WDOG |
+ * 0x2A47FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A480000 |128KB |L1 GPT |SECURE |AP SECURE WDOG |
+ * 0x2A49FFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A4A0000 |64KB |L1 GPT |NS |SID |
+ * 0x2A4AFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2A4B0000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A4BFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4C0000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A4CFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4D0000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A4DFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4E0000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A4EFFFF | | | |RECORD BLOCK - AP |
+ * ---------------------------------------------------------------------
+ * 0x2A4F0000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A4FFFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A500000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A50FFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A510000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A51FFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A520000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A52FFFF | | | |RECORD BLOCK - SCP |
+ * ---------------------------------------------------------------------
+ * 0x2A530000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A53FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A540000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A54FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A550000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A55FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A560000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A56FFFF | | | |RECORD BLOCK - MCP |
+ * ---------------------------------------------------------------------
+ * 0x2A570000 |64KB |L1 GPT |SECURE |SECURE SRAM ERROR |
+ * 0x2A57FFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A580000 |64KB |L1 GPT |NS |NS SRAM ERROR |
+ * 0x2A58FFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A590000 |64KB |L1 GPT |ROOT |ROOT SRAM ERROR |
+ * 0x2A59FFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A5A0000 |64KB |L1 GPT |REALM |REALM SRAM ERROR |
+ * 0x2A5AFFFF | | | |RECORD BLOCK - RSE |
+ * ---------------------------------------------------------------------
+ * 0x2A5B0000 |64KB |L1 GPT |SECURE |RSE SECURE SRAM ERROR |
+ * 0x2A5BFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5C0000 |64KB |L1 GPT |NS |RSE NS SRAM ERROR |
+ * 0x2A5CFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5D0000 |64KB |L1 GPT |SECURE |SCP SECURE SRAM ERROR |
+ * 0x2A5DFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5E0000 |64KB |L1 GPT |NS |SCP NS SRAM ERROR |
+ * 0x2A5EFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A5F0000 |64KB |L1 GPT |SECURE |MCP SECURE SRAM ERROR |
+ * 0x2A5FFFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A600000 |64KB |L1 GPT |NS |MCP NS SRAM ERROR |
+ * 0x2A60FFFF | | | |RECORD BLOCK - RSM |
+ * ---------------------------------------------------------------------
+ * 0x2A800000 |128KB |L1 GPT |NS |CNTCTL REFCLK |
+ * 0x2A81FFFF | | | |READ FRAME |
+ * ---------------------------------------------------------------------
+ * 0x2A820000 |64KB |L1 GPT |SECURE |SECURE TIMER CTL |
+ * 0x2A82FFFF | | | |BASE FRAME |
+ * ---------------------------------------------------------------------
+ * 0x2A830000 |64KB |L1 GPT |NS |NS TIMER CTL |
+ * 0x2A83FFFF | | | |BASE FRAME |
+ * ---------------------------------------------------------------------
+ * 0x2A900000 |128KB |L1 GPT |NS |AP-SCP NS |
+ * 0x2A91FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2A920000 |128KB |L1 GPT |SECURE |AP-SCP SECURE |
+ * 0x2A93FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2A940000 |128KB |L1 GPT |ROOT |AP-SCP ROOT |
+ * 0x2A95FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AA00000 |128KB |L1 GPT |NS |AP-MCP NS |
+ * 0x2AA1FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AA20000 |128KB |L1 GPT |SECURE |AP-MCP SECURE |
+ * 0x2AA3FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AA40000 |128KB |L1 GPT |ROOT |AP-MCP ROOT |
+ * 0x2AA5FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB00000 |128KB |L1 GPT |NS |AP-MCP NS |
+ * 0x2AB1FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB20000 |128KB |L1 GPT |SECURE |AP-RSE SECURE |
+ * 0x2AB3FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB40000 |128KB |L1 GPT |ROOT |AP-RSE ROOT |
+ * 0x2AB5FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AB60000 |128KB |L1 GPT |REALM |AP-RSE REALM |
+ * 0x2AB7FFFF | | | |MHU |
+ * ---------------------------------------------------------------------
+ * 0x2AC00000 |1152KB |L1 GPT |ROOT |SCP MCP RSE |
+ * 0x2ACEFFFF | | | |CROSS CHIP MHU |
+ * ---------------------------------------------------------------------
+ * 0x2B100000 |192KB |L1 GPT |SECURE |SYNCNT |
+ * 0x2B12FFFF | | | |MSTUPDTVAL_ADDR |
+ * ---------------------------------------------------------------------
+ * 0x2CF00000 |~33MB |L1 GPT |NS |STM SYSTEM ITS |
+ * 0x2EFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x2F000000 |4MB |L1 GPT |ANY |SHARED SRAM |
+ * 0x2F3FFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x30000000 |128MB |L1 GPT |ANY |GIC CLAYTON |
+ * 0x37FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x80000000 |2GB - |L1 GPT |NS |NS DRAM |
+ * 0xFFFE2BFF |117MB | | | |
+ * ---------------------------------------------------------------------
+ * 0x80000000 |26MB |L1 GPT |REALM |RMM |
+ * 0x37FFFFFF | | | |TF-A SHARED |
+ * ---------------------------------------------------------------------
+ * 0x80000000 |2MB |L1 GPT |ROOT |L1GPT |
+ * 0x37FFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x100080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 3 |
+ * 0x1000FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x200080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 2 |
+ * 0x2000FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x300080000000 |2GB |L1 GPT |NS |DRAM 1 CHIP 1 |
+ * 0x3000FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x100000000 |1GB |L1 GPT |ANY |CMN |
+ * 0x13FFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x200000000 |1GB |L1 GPT |ANY |LCP PERIPHERALS |
+ * 0x23FFFFFFF | | | |DDR |
+ * ---------------------------------------------------------------------
+ * 0x240000000 |1GB |L1 GPT |ANY |DDR IO |
+ * 0x27FFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x280000000 |1.5GB |L1 GPT |ANY |SMMU & NCI IO |
+ * 0x2DFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x300000000 |128MB |L1 GPT |ROOT |GPC SMMU |
+ * 0x308000000 | | | | |
+ * ---------------------------------------------------------------------
+ * 0x8080000000 |6GB |L1 GPT |ANY |DRAM 2 CHIP 0 |
+ * 0x81FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x108080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 1 |
+ * 0x1081FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x208080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 2 |
+ * 0x2081FFFFFFFF | | | | |
+ * ---------------------------------------------------------------------
+ * 0x308080000000 |6GB |L1 GPT |NS |DRAM 2 CHIP 3 |
+ * 0x3081FFFFFFFF | | | | |
+ * =====================================================================
+ */
+
+/*******************************************************************************
+ * Multichip config
+ ******************************************************************************/
+
+#define NRD_MC_BASE(base, n) (NRD_REMOTE_CHIP_MEM_OFFSET(n) + base)
+
+/*******************************************************************************
+ * PAS mappings
+ ******************************************************************************/
+
+#define NRD_PAS_SHARED_SRAM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SHARED_SRAM_BASE, \
+ NRD_CSS_SHARED_SRAM_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_SYSTEM_NCI \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SYSTEM_NCI_BASE, \
+ NRD_CSS_SYSTEM_NCI_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_DEBUG_NIC \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_DEBUG_NIC_BASE, \
+ NRD_CSS_DEBUG_NIC_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_UART \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_UART_BASE, \
+ NRD_CSS_NS_UART_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_REALM_UART \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_UART_BASE, \
+ NRD_CSS_REALM_UART_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_AP_NS_WDOG \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_NS_WDOG_BASE, \
+ NRD_CSS_AP_NS_WDOG_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_ROOT_WDOG \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_ROOT_WDOG_BASE, \
+ NRD_CSS_AP_ROOT_WDOG_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_SECURE_WDOG \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_SECURE_WDOG_BASE, \
+ NRD_CSS_AP_SECURE_WDOG_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_SECURE_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_AP_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_AP_BASE, \
+ NRD_CSS_NS_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_AP_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_AP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_AP_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_AP_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SECURE_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_NS_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_SCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_SCP_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_SCP_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SECURE_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_NS_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_MCP \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_MCP_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_MCP_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SECURE_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SECURE_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_SECURE_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_NS_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_NS_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_NS_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_ROOT_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_ROOT_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_ROOT_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_REALM_SRAM_ERB_RSE \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_REALM_SRAM_ERB_RSE_BASE, \
+ NRD_CSS_REALM_SRAM_ERB_RSE_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_RSE_SECURE_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_RSE_SECURE_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_RSE_NS_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_RSE_NS_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_RSE_NS_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_SCP_SECURE_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_SCP_SECURE_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_SCP_NS_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_NS_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_SCP_NS_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_MCP_SECURE_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_MCP_SECURE_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_MCP_NS_SRAM_ERB_RSM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_MCP_NS_SRAM_ERB_RSM_BASE, \
+ NRD_CSS_MCP_NS_SRAM_ERB_RSM_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_SCP_ROOT_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_SCP_ROOT_MHU_BASE, \
+ NRD_CSS_AP_SCP_ROOT_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_MCP_NS_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_MCP_NS_MHU_BASE, \
+ NRD_CSS_AP_MCP_NS_MHU_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_MCP_SECURE_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_MCP_SECURE_MHU_BASE, \
+ NRD_CSS_AP_MCP_SECURE_MHU_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_AP_MCP_ROOT_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_MCP_ROOT_MHU_BASE, \
+ NRD_CSS_AP_MCP_ROOT_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_RSE_NS_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_NS_MHU_BASE, \
+ NRD_CSS_AP_RSE_NS_MHU_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_AP_RSE_SECURE_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_SECURE_MHU_BASE, \
+ NRD_CSS_AP_RSE_SECURE_MHU_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_AP_RSE_ROOT_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_ROOT_MHU_BASE, \
+ NRD_CSS_AP_RSE_ROOT_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_AP_RSE_REALM_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_AP_RSE_REALM_MHU_BASE, \
+ NRD_CSS_AP_RSE_REALM_MHU_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_BASE, \
+ NRD_CSS_SCP_MCP_RSE_CROSS_CHIP_MHU_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_BASE, \
+ NRD_CSS_SYNCNT_MSTUPDTVAL_ADDR_SIZE, \
+ GPT_GPI_SECURE)
+
+#define NRD_PAS_STM_SYSTEM_ITS \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_STM_SYSTEM_ITS_BASE, \
+ NRD_CSS_STM_SYSTEM_ITS_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_SCP_MCP_RSE_SHARED_SRAM \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_BASE, \
+ NRD_CSS_SCP_MCP_RSE_SHARED_SRAM_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_GIC \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_GIC_BASE, \
+ NRD_CSS_GIC_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_NS_DRAM \
+ GPT_MAP_REGION_GRANULE( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM1_CHIP1 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 1), \
+ ARM_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM1_CHIP2 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 2), \
+ ARM_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM1_CHIP3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM1_BASE, 3), \
+ ARM_DRAM1_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_RMM \
+ GPT_MAP_REGION_GRANULE( \
+ ARM_REALM_BASE, \
+ ARM_REALM_SIZE + \
+ ARM_EL3_RMM_SHARED_SIZE, \
+ GPT_GPI_REALM)
+
+#define NRD_PAS_L1GPT \
+ GPT_MAP_REGION_GRANULE( \
+ ARM_L1_GPT_BASE, \
+ ARM_L1_GPT_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_CMN \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_CMN_BASE, \
+ NRD_CSS_CMN_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_LCP_PERIPHERAL \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_LCP_PERIPHERAL_BASE, \
+ NRD_CSS_LCP_PERIPHERAL_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_DDR_IO \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_DDR_IO_BASE, \
+ NRD_CSS_DDR_IO_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_SMMU_NCI_IO \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_SMMU_NCI_IO_BASE, \
+ NRD_CSS_SMMU_NCI_IO_SIZE, \
+ GPT_GPI_ANY)
+
+#define NRD_PAS_GPC_SMMUV3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_CSS_GPC_SMMUV3_BASE, \
+ NRD_CSS_GPC_SMMUV3_SIZE, \
+ GPT_GPI_ROOT)
+
+#define NRD_PAS_DRAM2_CHIP0 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 0), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM2_CHIP1 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 1), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM2_CHIP2 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 2), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#define NRD_PAS_DRAM2_CHIP3 \
+ GPT_MAP_REGION_GRANULE( \
+ NRD_MC_BASE(NRD_CSS_DRAM2_BASE, 3), \
+ ARM_DRAM2_SIZE, \
+ GPT_GPI_NS)
+
+#endif /* NRD_PAS_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
new file mode 100644
index 0000000..0dce512
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -0,0 +1,756 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the platform port definitions for the
+ * third generation of platforms.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF3_H
+#define NRD_PLAT_ARM_DEF3_H
+
+#include <common/tbbr/tbbr_img_def.h>
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+#endif /* __ASSEMBLER__ */
+
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/common/common_def.h>
+#include <nrd_css_fw_def3.h>
+#include <nrd_ros_fw_def3.h>
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
+ PLAT_ARM_CLUSTER_COUNT * \
+ NRD_MAX_CPUS_PER_CLUSTER * \
+ NRD_MAX_PE_PER_CPU)
+
+/*******************************************************************************
+ * PA/VA config
+ ******************************************************************************/
+
+#ifdef __aarch64__
+#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
+ NRD_CHIP_COUNT)
+#else
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#endif
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage. In addition to that, on
+ * multi-chip platforms, address regions on each of the remote chips are
+ * also mapped. In BL31, for instance, three address regions on the remote
+ * chips are accessed - secure ram, css device and soc device regions.
+ */
+#if defined(IMAGE_BL31)
+# define PLAT_ARM_MMAP_ENTRIES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (9 + ((NRD_CHIP_COUNT - 1) * 3))
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES U(8)
+# define MAX_XLAT_TABLES U(5)
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES (16 + (NRD_CHIP_COUNT - 1))
+# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2))
+#else
+# define PLAT_ARM_MMAP_ENTRIES U(7)
+# define MAX_XLAT_TABLES U(7)
+#endif
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
+
+#define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
+ */
+#define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \
+ ((NRD_CHIP_COUNT - 1) * 0x2000))
+
+#define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \
+ PLAT_ARM_MAX_BL2_SIZE + \
+ PLAT_ARM_MAX_BL1_RW_SIZE)
+
+/*******************************************************************************
+ * BL31 plat param
+ ******************************************************************************/
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
+
+/*******************************************************************************
+ * Stack sizes
+ ******************************************************************************/
+
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE UL(0x1000)
+# else
+# define PLATFORM_STACK_SIZE UL(0x440)
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE UL(0x1000)
+# else
+# define PLATFORM_STACK_SIZE UL(0x400)
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE UL(0x400)
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+# define PLATFORM_STACK_SIZE UL(0x500)
+# else
+# define PLATFORM_STACK_SIZE UL(0x400)
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE UL(0x440)
+#endif
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define ARM_CONSOLE_BAUDRATE (115200)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SECURE_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE NRD_CSS_SECURE_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SECURE_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * System counter and timer config
+ ******************************************************************************/
+
+#define ARM_SYS_CNTCTL_BASE NRD_CSS_GENERIC_REFCLK_BASE
+#define ARM_SYS_CNTREAD_BASE NRD_CSS_CNTCTL_REFCLK_READFRAME_BASE
+#define ARM_SYS_TIMCTL_BASE NRD_CSS_SYS_TIMCTL_BASE
+#define ARM_SYS_CNT_BASE_S NRD_CSS_SECURE_TIMER_CTL_BASE
+#define ARM_SYS_CNT_BASE_NS NRD_CSS_NS_TIMER_CTL_BASE
+
+/*******************************************************************************
+ * SRAM and DRAM config for FW
+ ******************************************************************************/
+
+#define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_SECURE_ROM_BASE
+#define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_SECURE_ROM_SIZE
+
+#define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE
+#define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_SECURE_SRAM_SIZE
+
+#define PLAT_ARM_NSTIMER_FRAME_ID (0)
+
+#define PLAT_ARM_NSRAM_BASE NRD_CSS_NS_SRAM_BASE
+#define PLAT_ARM_NSRAM_SIZE NRD_CSS_NS_SRAM_SIZE
+
+/*******************************************************************************
+ * Power config
+ ******************************************************************************/
+
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define ARM_PWR_LVL0 MPIDR_AFFLVL0
+#define ARM_PWR_LVL1 MPIDR_AFFLVL1
+#define ARM_PWR_LVL2 MPIDR_AFFLVL2
+#define ARM_PWR_LVL3 MPIDR_AFFLVL3
+
+/* Local power state for power domains in Run state. */
+#define ARM_LOCAL_STATE_RUN U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define ARM_LOCAL_STATE_RET U(1)
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains
+ */
+#define ARM_LOCAL_STATE_OFF U(2)
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * id will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
+
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*******************************************************************************
+ * MHU config
+ ******************************************************************************/
+
+#define PLAT_CSS_MHU_BASE NRD_CSS_AP_SCP_SECURE_MHU_BASE
+#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
+
+/*******************************************************************************
+ * Cache config
+ ******************************************************************************/
+
+#define ARM_CACHE_WRITEBACK_SHIFT U(6)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+
+/*******************************************************************************
+ * SCMI config
+ ******************************************************************************/
+
+/* Number of SCMI channels on the platform */
+#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
+
+/*******************************************************************************
+ * GIC/EHF config
+ ******************************************************************************/
+
+/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */
+#define PLAT_CORE_FAULT_IRQ U(17)
+
+/* ARM platforms use 3 upper bits of secure interrupt priority */
+#define PLAT_PRI_BITS U(3)
+
+#if ENABLE_FEAT_RAS && FFH_SUPPORT
+#define PLAT_RAS_PRI U(0x10)
+#endif
+
+#if ENABLE_FEAT_RAS && FFH_SUPPORT
+#define PLAT_SP_PRI PLAT_RAS_PRI
+#else
+#define PLAT_SP_PRI U(0x10)
+#endif
+
+#define ARM_IRQ_SEC_PHY_TIMER U(29)
+
+#define ARM_IRQ_SEC_SGI_0 U(8)
+#define ARM_IRQ_SEC_SGI_1 U(9)
+#define ARM_IRQ_SEC_SGI_2 U(10)
+#define ARM_IRQ_SEC_SGI_3 U(11)
+#define ARM_IRQ_SEC_SGI_4 U(12)
+#define ARM_IRQ_SEC_SGI_5 U(13)
+#define ARM_IRQ_SEC_SGI_6 U(14)
+#define ARM_IRQ_SEC_SGI_7 U(15)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+#define PLAT_ARM_GICD_BASE NRD_CSS_GIC_BASE
+#if (NRD_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x00100000)
+#else
+#define PLAT_ARM_GICR_BASE NRD_CSS_GIC_BASE + UL(0x001C0000)
+#endif
+
+/*******************************************************************************
+ * SDEI config
+ ******************************************************************************/
+
+#define PLAT_SDEI_CRITICAL_PRI U(0x60)
+#define PLAT_SDEI_NORMAL_PRI U(0x70)
+
+/* SGI used for SDEI signalling */
+#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
+
+#if SDEI_IN_FCONF
+/* ARM SDEI dynamic private event max count */
+#define ARM_SDEI_DP_EVENT_MAX_CNT U(3)
+
+/* ARM SDEI dynamic shared event max count */
+#define ARM_SDEI_DS_EVENT_MAX_CNT U(3)
+#else
+/* ARM SDEI dynamic private event numbers */
+#define ARM_SDEI_DP_EVENT_0 UL(1000)
+#define ARM_SDEI_DP_EVENT_1 UL(1001)
+#define ARM_SDEI_DP_EVENT_2 UL(1002)
+
+/* ARM SDEI dynamic shared event numbers */
+#define ARM_SDEI_DS_EVENT_0 UL(2000)
+#define ARM_SDEI_DS_EVENT_1 UL(2001)
+#define ARM_SDEI_DS_EVENT_2 UL(2002)
+
+#define ARM_SDEI_PRIVATE_EVENTS \
+ SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+
+#define ARM_SDEI_SHARED_EVENTS \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, \
+ SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+#endif /* SDEI_IN_FCONF */
+
+/*******************************************************************************
+ * SDS config
+ ******************************************************************************/
+
+/* SDS ID for unusable CPU MPID list structure */
+#define SDS_ISOLATED_CPU_LIST_ID U(128)
+
+/* Index of SDS region used in the communication with SCP */
+#define SDS_SCP_AP_REGION_ID U(0)
+
+/*******************************************************************************
+ * SMMUv3 Config
+ ******************************************************************************/
+
+/* SMMUv3 root offset register */
+#define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0xA0000)
+
+/*******************************************************************************
+ * Platform type identification macro
+ ******************************************************************************/
+
+/* Platform ID related accessors */
+#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F)
+#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00)
+#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08)
+#define BOARD_CSS_PLAT_TYPE_RTL U(0x00)
+#define BOARD_CSS_PLAT_TYPE_FPGA U(0x01)
+#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
+#define BOARD_CSS_PLAT_TYPE_FVP U(0x03)
+
+#ifndef __ASSEMBLER__
+#define BOARD_CSS_GET_PLAT_TYPE(addr) \
+ ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
+ >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
+#endif /* __ASSEMBLER__ */
+
+/* Platform ID address */
+#define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_PERIPH_BASE + \
+ UL(0x00FE00E0)
+
+/*******************************************************************************
+ * Flash config
+ ******************************************************************************/
+
+#define MAX_IO_DEVICES U(3)
+#define MAX_IO_HANDLES U(4)
+
+#define V2M_SYS_LED U(0x8)
+
+#define V2M_SYS_LED_SS_SHIFT U(0)
+#define V2M_SYS_LED_EL_SHIFT U(1)
+#define V2M_SYS_LED_EC_SHIFT U(3)
+
+#define V2M_SYS_LED_SS_MASK U(0x01)
+#define V2M_SYS_LED_EL_MASK U(0x03)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
+
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
+
+#define V2M_SYSREGS_BASE NRD_ROS_SYSTEM_PERIPH_BASE + \
+ UL(0x00010000)
+#define V2M_FLASH0_BASE NRD_ROS_SMC0_BASE
+#define V2M_FLASH0_SIZE NRD_ROS_SMC0_SIZE
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*******************************************************************************
+ * ROS peripheral config
+ ******************************************************************************/
+
+/* Non-volatile counters */
+#define SOC_TRUSTED_NVCTR_BASE NRD_ROS_PLATFORM_PERIPH_BASE + \
+ UL(0x00E70000)
+#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000)
+#define TFW_NVCTR_SIZE U(4)
+#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004)
+#define NTFW_CTR_SIZE U(4)
+
+/*******************************************************************************
+ * SRAM layout
+ ******************************************************************************/
+
+/*
+ * Trusted SRAM
+ * 0x00100000 +--------------+
+ * | L0 GPT |
+ * 0x000E0000 +--------------+ loaded by BL2 +----------------+
+ * | BL1 (rw) | <<<<<<<<<<<<< | |
+ * |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
+ * | BL2 | <<<<<<<<<<<<< | |
+ * |--------------| <<<<<<<<<<<<< |----------------|
+ * | | <<<<<<<<<<<<< | BL31 PROGBITS |
+ * | | +----------------+
+ * +--------------+
+ * | CONFIG |
+ * 0x0001A000 +--------------+
+ * | Shared |
+ * 0x00019000 +--------------+
+ * | BL1 (ro) |
+ * 0x00000000 +--------------+
+ */
+
+/*******************************************************************************
+ * BL1 RO specifics
+ ******************************************************************************/
+
+/*
+ * SRAM region to store BL1 code and RO. This has been carved out at the bottom
+ * of SRAM
+ */
+
+#define BL1_RO_BASE NRD_CSS_BL1_RO_BASE
+#define BL1_RO_LIMIT (NRD_CSS_BL1_RO_BASE \
+ + NRD_CSS_BL1_RO_SIZE)
+
+/*******************************************************************************
+ * L0 GPT specifics
+ ******************************************************************************/
+
+/*
+ * L0 GPT has to be aligned to its size. In order to avoid holes due to
+ * alignment, place L0 GPT at the top of SRAM.
+ */
+#define ARM_L0_GPT_SIZE UL(0x00020000) /* 128KB */
+#define ARM_L0_GPT_BASE NRD_CSS_SHARED_SRAM_SIZE - \
+ ARM_L0_GPT_SIZE
+
+#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE)
+
+/*******************************************************************************
+ * Arm shared RAM specifics
+ ******************************************************************************/
+
+#define ARM_SHARED_RAM_BASE (NRD_CSS_BL1_RO_BASE + \
+ NRD_CSS_BL1_RO_SIZE)
+#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
+
+/*******************************************************************************
+ * Arm BL RAM specifics
+ ******************************************************************************/
+
+/*Rest of SRAM till L0 GPT base */
+#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
+ ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE (ARM_L0_GPT_BASE - \
+ ARM_BL_RAM_BASE)
+
+/*******************************************************************************
+ * FW_CONFIG specifics
+ ******************************************************************************/
+
+/*
+ * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
+ * and limit. Leave enough space of BL2 meminfo.
+ */
+#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
+ + (PAGE_SIZE / 2U))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
+#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
+ + (PAGE_SIZE / 2U))
+
+/*
+ * Define limit of firmware configuration memory:
+ * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
+ */
+#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
+
+/*******************************************************************************
+ * BL1 RW specifics
+ ******************************************************************************/
+
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE - \
+ PLAT_ARM_MAX_BL1_RW_SIZE)
+#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE)
+
+/*******************************************************************************
+ * BL2 specific defines.
+ ******************************************************************************/
+
+/* Put BL2 just below BL1. */
+#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_LIMIT BL1_RW_BASE
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+
+/* Keep BL31 below BL2 in the Trusted SRAM.*/
+#define BL31_BASE ((ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE) - \
+ PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_PROGBITS_LIMIT BL2_BASE
+#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS 7
+
+#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
+ ARM_BL_REGIONS)
+
+/*******************************************************************************
+ * DRAM layout
+ ******************************************************************************/
+
+/*
+ * The top 100MB of DRAM1 is configured as follows:
+ * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
+ * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM
+ * - REALM DRAM: Reserved for Realm world if RME is enabled
+ *
+ * DRAM layout
+ * +------------------+
+ * | REALM (RMM) |
+ * | (32MB - 4KB) |
+ * +------------------+
+ * | |
+ * | TF-A <-> RMM |
+ * | SHARED (4KB) |
+ * +------------------+
+ * | L1 GPT |
+ * | |
+ * DRAM1 End +------------------+
+ */
+
+/* Number of DRAM banks */
+#if (NRD_PLATFORM_VARIANT == 2)
+#define ARM_DRAM_NUM_BANKS U(8)
+#else
+#define ARM_DRAM_NUM_BANKS U(2)
+#endif
+
+/*******************************************************************************
+ * DRAM bank1 specific defines.
+ ******************************************************************************/
+
+/* Bank-1 DRAM */
+#define ARM_DRAM1_BASE UL(0x80000000)
+#define ARM_DRAM1_SIZE UL(0x80000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - 1U)
+
+/*******************************************************************************
+ * DRAM bank2 specific defines.
+ ******************************************************************************/
+
+/* Bank-2 DRAM */
+#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
+#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
+#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
+ ARM_DRAM2_SIZE - 1U)
+
+/*******************************************************************************
+ * L1GPT specific defines.
+ ******************************************************************************/
+
+/* 2MB per L1 entry, PPS - 48 bits, PGS - 4KB, L0GPTSZ - 16GB */
+#define ARM_L1_GPT_SIZE (UL(40 * 1024 * 1024) + \
+ ((NRD_CHIP_COUNT - 1) * \
+ (4 * 1024 * 1024)))
+
+#define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - \
+ ARM_L1_GPT_SIZE)
+#define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \
+ ARM_L1_GPT_SIZE - 1U)
+
+/*******************************************************************************
+ * "RMM TF-A shared region" specific defines.
+ ******************************************************************************/
+
+/* PLAT_ARM_EL3_RMM_SHARED_SIZE */
+#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
+
+#define ARM_EL3_RMM_SHARED_BASE (ARM_L1_GPT_BASE - \
+ ARM_EL3_RMM_SHARED_SIZE)
+
+#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \
+ ARM_EL3_RMM_SHARED_SIZE - 1U)
+
+/*******************************************************************************
+ * RMM specific defines.
+ ******************************************************************************/
+
+/* ARM_REALM_SIZE */
+#define ARM_REALM_SIZE (UL(0x02600000) - \
+ ARM_EL3_RMM_SHARED_SIZE)
+#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \
+ ARM_REALM_SIZE)
+
+#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U)
+
+#define RMM_BASE (ARM_REALM_BASE)
+#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE)
+#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE)
+#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE)
+
+/*******************************************************************************
+ * NRD_CSS_CARVEOUT_RESERVED region specific defines.
+ ******************************************************************************/
+
+#define NRD_CSS_CARVEOUT_RESERVED_BASE (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - \
+ NRD_CSS_DRAM1_CARVEOUT_SIZE)
+#define NRD_CSS_CARVEOUT_RESERVED_SIZE (NRD_CSS_DRAM1_CARVEOUT_SIZE - \
+ (ARM_EL3_RMM_SHARED_SIZE + \
+ ARM_REALM_SIZE + \
+ ARM_L1_GPT_SIZE))
+
+#define NRD_CSS_CARVEOUT_RESERVED_END (NRD_CSS_CARVEOUT_RESERVED_BASE +\
+ NRD_CSS_CARVEOUT_RESERVED_SIZE - 1U)
+
+/*******************************************************************************
+ * NS RAM specific defines specific defines.
+ ******************************************************************************/
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ NRD_CSS_DRAM1_CARVEOUT_SIZE)
+
+#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
+ ARM_NS_DRAM1_SIZE - 1U)
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define V2M_MAP_FLASH0_RW \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define V2M_MAP_FLASH0_RO \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_RO_DATA | EL3_PAS)
+
+#define ARM_MAP_L0_GPT_REGION \
+ MAP_REGION_FLAT( \
+ ARM_L0_GPT_BASE, \
+ ARM_L0_GPT_SIZE, \
+ MT_MEMORY | MT_RW | MT_ROOT)
+
+#define ARM_MAP_BL_CONFIG_REGION \
+ MAP_REGION_FLAT( \
+ ARM_BL_RAM_BASE, \
+ (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#if SEPARATE_CODE_AND_RODATA
+#define ARM_MAP_BL_RO \
+ MAP_REGION_FLAT( \
+ BL_CODE_BASE, \
+ (BL_CODE_END - BL_CODE_BASE), \
+ MT_CODE | EL3_PAS), \
+ MAP_REGION_FLAT( \
+ BL_RO_DATA_BASE, \
+ (BL_RO_DATA_END - BL_RO_DATA_BASE), \
+ MT_RO_DATA | EL3_PAS)
+#else
+#define ARM_MAP_BL_RO \
+ MAP_REGION_FLAT( \
+ BL_CODE_BASE, \
+ (BL_CODE_END - BL_CODE_BASE), \
+ MT_CODE | EL3_PAS)
+#endif
+
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM \
+ MAP_REGION_FLAT( \
+ BL_COHERENT_RAM_BASE, \
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+#endif
+
+#define ARM_MAP_DRAM2 \
+ MAP_REGION_FLAT( \
+ ARM_DRAM2_BASE, \
+ ARM_DRAM2_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#endif /* NRD_PLAT_ARM_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_def3.h
new file mode 100644
index 0000000..c987621
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_def3.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file contains the RoS specific definitions for the third generation of
+ * platforms.
+ */
+
+#ifndef NRD_ROS_DEF3_H
+#define NRD_ROS_DEF3_H
+
+/*******************************************************************************
+ * RoS memory map related defines
+ ******************************************************************************/
+
+/* System peripherals */
+#define NRD_ROS_SYSTEM_PERIPH_BASE UL(0x0C000000)
+#define NRD_ROS_SYSTEM_PERIPH_SIZE UL(0x02000000)
+
+/* Platform peripherals */
+#define NRD_ROS_PLATFORM_PERIPH_BASE UL(0x0E000000)
+#define NRD_ROS_PLATFORM_PERIPH_SIZE UL(0x02000000)
+
+/* SMC0 */
+#define NRD_ROS_SMC0_BASE UL(0x08000000)
+#define NRD_ROS_SMC0_SIZE UL(0x04000000)
+
+#endif /* NRD_ROS_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_fw_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_fw_def3.h
new file mode 100644
index 0000000..c0fde85
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_ros_fw_def3.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS firmware specific definitions for the
+ * third generation of platforms. RoS (Rest Of System) is used to refer to the
+ * part of the reference design platform that excludes CSS.
+ */
+
+#ifndef NRD_ROS_FW_DEF3_H
+#define NRD_ROS_FW_DEF3_H
+
+#include <nrd_ros_def3.h>
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define NRD_ROS_PLATFORM_PERIPH_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_ROS_PLATFORM_PERIPH_BASE, \
+ NRD_ROS_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_SYSTEM_PERIPH_MMAP \
+ MAP_REGION_FLAT( \
+ NRD_ROS_SYSTEM_PERIPH_BASE, \
+ NRD_ROS_SYSTEM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_ROS_V2M_MEM_PROTECT_MMAP \
+ MAP_REGION_FLAT( \
+ PLAT_ARM_MEM_PROT_ADDR, \
+ V2M_FLASH_BLOCK_SIZE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+
+#define NRD_ROS_FLASH0_RO_MMAP \
+ MAP_REGION_FLAT( \
+ V2M_FLASH0_BASE, \
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+#endif /* NRD_ROS_FW_DEF3_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index 94f80c3..391c68c 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -28,6 +28,14 @@
#define RD_V2_SID_VER_PART_NUM 0x07F2
#define RD_V2_CONFIG_ID 0x1
+/* SID Version values for RD-Fremont */
+#define RD_FREMONT_SID_VER_PART_NUM 0x07EE
+#define RD_FREMONT_CONFIG_ID 0x0
+
+/* SID Version values for RD-Fremont variants */
+#define RD_FREMONT_CFG1_SID_VER_PART_NUM 0x07F9
+#define RD_FREMONT_CFG2_SID_VER_PART_NUM 0x07EE
+
/* Structure containing Neoverse RD platform variant information */
typedef struct nrd_platform_info {
unsigned int platform_id; /* Part Number of the platform */
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index a22c799..5a7dfb1 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -73,6 +73,52 @@
#endif
};
+static scmi_channel_plat_info_t plat3_rd_scmi_info[] = {
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #if (NRD_CHIP_COUNT > 1)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(1),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(1) +
+ MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #endif
+ #if (NRD_CHIP_COUNT > 2)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(2),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(2) +
+ MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #endif
+ #if (NRD_CHIP_COUNT > 3)
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(3),
+ .db_reg_addr = PLAT_CSS_MHU_BASE +
+ NRD_REMOTE_CHIP_MEM_OFFSET(3) +
+ MHU_V3_SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhu_ring_doorbell,
+ },
+ #endif
+};
+
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
@@ -85,6 +131,13 @@
panic();
}
return &plat_rd_scmi_info[channel_id];
+ } else if (nrd_plat_info.platform_id == RD_FREMONT_SID_VER_PART_NUM ||
+ nrd_plat_info.platform_id == RD_FREMONT_CFG1_SID_VER_PART_NUM ||
+ nrd_plat_info.platform_id == RD_FREMONT_CFG2_SID_VER_PART_NUM) {
+ if (channel_id >= ARRAY_SIZE(plat3_rd_scmi_info)) {
+ panic();
+ }
+ return &plat3_rd_scmi_info[channel_id];
} else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) {
return &sgi575_scmi_plat_info;
} else {
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat3.c b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
new file mode 100644
index 0000000..7b98052
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/nrd_plat3.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <drivers/arm/css/sds.h>
+#include <drivers/arm/sbsa.h>
+#include <lib/utils_def.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+/*
+ * Table of regions for different BL stages to map using the MMU.
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ NRD_CSS_SHARED_RAM_MMAP(0),
+ NRD_ROS_FLASH0_RO_MMAP,
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PLATFORM_PERIPH_MMAP,
+ NRD_ROS_SYSTEM_PERIPH_MMAP,
+ {0}
+};
+#endif /* IMAGE_BL3 */
+
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ NRD_CSS_SHARED_RAM_MMAP(0),
+ NRD_ROS_FLASH0_RO_MMAP,
+#ifdef PLAT_ARM_MEM_PROT_ADDR
+ NRD_ROS_V2M_MEM_PROTECT_MMAP,
+#endif
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PLATFORM_PERIPH_MMAP,
+ NRD_ROS_SYSTEM_PERIPH_MMAP,
+ NRD_CSS_NS_DRAM1_MMAP,
+#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
+ NRD_CSS_BL1_RW_MMAP,
+#endif
+ NRD_CSS_GPT_L1_DRAM_MMAP,
+ NRD_CSS_RMM_REGION_MMAP,
+ {0}
+};
+#endif /* IMAGE_BL2 */
+
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+ NRD_CSS_SHARED_RAM_MMAP(0),
+#ifdef PLAT_ARM_MEM_PROT_ADDR
+ NRD_ROS_V2M_MEM_PROTECT_MMAP,
+#endif
+ NRD_CSS_PERIPH_MMAP(0),
+ NRD_ROS_PLATFORM_PERIPH_MMAP,
+ NRD_ROS_SYSTEM_PERIPH_MMAP,
+ NRD_CSS_GPT_L1_DRAM_MMAP,
+ NRD_CSS_EL3_RMM_SHARED_MEM_MMAP,
+ NRD_CSS_GPC_SMMU_SMMUV3_MMAP,
+ {0}
+};
+#endif /* IMAGE_BL31 */
+
+ARM_CASSERT_MMAP
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(NRD_CSS_AP_SECURE_WDOG_BASE,
+ NRD_CSS_AP_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(NRD_CSS_AP_SECURE_WDOG_BASE);
+}
+
+static sds_region_desc_t nrd_sds_regions[] = {
+ { .base = PLAT_ARM_SDS_MEM_BASE },
+};
+
+sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
+{
+ *region_count = ARRAY_SIZE(nrd_sds_regions);
+
+ return nrd_sds_regions;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts
new file mode 100644
index 0000000..62ba0fa
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_fw_config.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/tbbr/tbbr_img_def.h>
+
+/dts-v1/;
+
+/ {
+ dtb-registry {
+ compatible = "fconf,dyn_cfg-dtb_registry";
+
+ tb_fw-config {
+ load-address = <0x0 0x01f300>;
+ max-size = <0x200>;
+ id = <TB_FW_CONFIG_ID>;
+ };
+
+ nt_fw-config {
+ load-address = <0x0 0xF3000000>;
+ max-size = <0x0100000>;
+ id = <NT_FW_CONFIG_ID>;
+ };
+ };
+};
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts
new file mode 100644
index 0000000..62cad39
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_nt_fw_config.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+/ {
+ /* compatible string */
+ compatible = "arm,rd-fremont";
+
+ /*
+ * Place holder for system-id node with default values. The
+ * value of platform-id and config-id will be set to the
+ * correct values during the BL2 stage of boot.
+ */
+ system-id {
+ platform-id = <0x0>;
+ config-id = <0x0>;
+ multi-chip-mode = <0x0>;
+ };
+};
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts
new file mode 100644
index 0000000..a4c7c72
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/fdts/rdfremont_tb_fw_config.dts
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ tb_fw-config {
+ compatible = "arm,tb_fw";
+
+ /* Disable authentication for development */
+ disable_auth = <0x0>;
+
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
+ };
+};
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
new file mode 100644
index 0000000..b55dbe8
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <plat/arm/css/common/css_def.h>
+#include <nrd_css_fw_def3.h>
+#include <nrd_pas_def3.h>
+#include <nrd_plat_arm_def3.h>
+#include <nrd_ros_fw_def3.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
+
+/* PE-Cluster count */
+#if (NRD_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT U(8)
+#elif (NRD_PLATFORM_VARIANT == 2)
+#define PLAT_ARM_CLUSTER_COUNT U(4)
+#else
+#define PLAT_ARM_CLUSTER_COUNT U(16)
+#endif
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
+
+/* Shared RAM*/
+#define NRD_CSS_SHARED_SRAM_SIZE UL(0x000100000)
+
+/* DRAM1 */
+#define NRD_CSS_DRAM1_SIZE ULL(0x80000000)
+
+/* DRAM2 */
+#define NRD_CSS_DRAM2_SIZE ULL(0x180000000)
+
+/* Address bits */
+#define NRD_ADDR_BITS_PER_CHIP U(36) /* 64GB */
+
+/*
+ * In the current implementation, the RoT Service request that requires the
+ * biggest message buffer is the RSE_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The
+ * maximum required buffer size is calculated based on the platform-specific
+ * needs of this request.
+ */
+#define PLAT_RSE_COMMS_PAYLOAD_MAX_SIZE UL(0x1000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h
new file mode 100644
index 0000000..400dcc5
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_mhuv3.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RDFREMONT_MHUV3_H
+#define RDFREMONT_MHUV3_H
+
+void mhu_v3_get_secure_device_base(uintptr_t *base, bool sender);
+
+#endif /* RDFREMONT_MHUV3_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h
new file mode 100644
index 0000000..ad1bc23
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/rdfremont_rse_comms.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RDFREMONT_RSE_COMMS_H
+#define RDFREMONT_RSE_COMMS_H
+
+int plat_rse_comms_init(void);
+
+#endif /* RDFREMONT_RSE_COMMS_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
new file mode 100644
index 0000000..bca6172
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
@@ -0,0 +1,139 @@
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+RD_FREMONT_VARIANTS := 0 1 2
+ifneq ($(NRD_PLATFORM_VARIANT), \
+ $(filter $(NRD_PLATFORM_VARIANT),$(RD_FREMONT_VARIANTS)))
+ $(error "NRD_PLATFORM_VARIANT for RD-FREMONT should be 0, 1, or 2,"
+ "currently set to ${NRD_PLATFORM_VARIANT}.")
+endif
+
+$(eval $(call CREATE_SEQ,SEQ,4))
+ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
+ $(error "Chip count for RD-Fremont-MC should be either $(SEQ) \
+ currently it is set to ${NRD_CHIP_COUNT}.")
+endif
+
+# Build options
+# Major and Minor versions
+override ARM_ARCH_MAJOR := 8
+override ARM_ARCH_MINOR := 7
+
+# Image flags
+override NEED_BL1 := yes
+override NEED_BL2 := yes
+override NEED_BL32 := no
+override NEED_RMM := no
+
+# Misc options
+override CTX_INCLUDE_AARCH32_REGS := 0
+
+# RD-Fremont platform uses GIC-700 which is based on GICv4.1
+GIC_ENABLE_V4_EXTN := 1
+
+# Enable GIC multichip extension only for multichip platforms
+ifeq (${NRD_PLATFORM_VARIANT}, 2)
+GICV3_IMPL_GIC600_MULTICHIP := 1
+endif
+
+# RD-Fremont uses MHUv3
+PLAT_MHU_VERSION := 3
+
+include plat/arm/board/neoverse_rd/common/nrd-common.mk
+include drivers/arm/rse/rse_comms.mk
+include drivers/auth/mbedtls/mbedtls_common.mk
+ifeq (${MEASURED_BOOT},1)
+include drivers/measured_boot/rse/rse_measured_boot.mk
+endif
+
+RDFREMONT_BASE = plat/arm/board/neoverse_rd/platform/rdfremont
+
+PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd3/ \
+ -I${RDFREMONT_BASE}/include/ \
+ -Iinclude/lib/psa
+
+NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v3.S
+
+# Source files for RD-Fremont variants
+PLAT_BL_COMMON_SOURCES \
+ += ${NRD_COMMON_BASE}/nrd_plat3.c \
+ ${RDFREMONT_BASE}/rdfremont_common.c
+
+PLAT_MEASURED_BOOT_SOURCES \
+ := ${MEASURED_BOOT_SOURCES} \
+ ${RSE_COMMS_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_common_measured_boot.c \
+ lib/psa/measured_boot.c
+
+BL1_SOURCES += ${NRD_CPU_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_err.c \
+ ${RDFREMONT_BASE}/rdfremont_mhuv3.c
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+BL1_SOURCES += ${RDFREMONT_BASE}/rdfremont_trusted_boot.c
+endif
+ifeq (${MEASURED_BOOT},1)
+BL1_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_bl1_measured_boot.c
+endif
+
+BL2_SOURCES += ${RDFREMONT_BASE}/rdfremont_bl2_setup.c \
+ ${RDFREMONT_BASE}/rdfremont_err.c \
+ ${RDFREMONT_BASE}/rdfremont_mhuv3.c \
+ ${RDFREMONT_BASE}/rdfremont_security.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+BL2_SOURCES += ${RDFREMONT_BASE}/rdfremont_trusted_boot.c
+endif
+ifeq (${MEASURED_BOOT},1)
+BL2_SOURCES += ${PLAT_MEASURED_BOOT_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_bl2_measured_boot.c
+endif
+
+BL31_SOURCES += ${NRD_CPU_SOURCES} \
+ ${MBEDTLS_SOURCES} \
+ ${RSE_COMMS_SOURCES} \
+ ${RDFREMONT_BASE}/rdfremont_bl31_setup.c \
+ ${RDFREMONT_BASE}/rdfremont_mhuv3.c \
+ ${RDFREMONT_BASE}/rdfremont_topology.c \
+ ${RDFREMONT_BASE}/rdfremont_plat_attest_token.c \
+ ${RDFREMONT_BASE}/rdfremont_realm_attest_key.c \
+ drivers/arm/smmu/smmu_v3.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/psa/cca_attestation.c \
+ lib/psa/delegated_attestation.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_dyn_cfg.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+ifeq (${NRD_PLATFORM_VARIANT}, 2)
+BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
+endif
+
+# XLAT options for RD-Fremont variants
+BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
+BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${RDFREMONT_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${RDFREMONT_BASE}/fdts/${PLAT}_tb_fw_config.dts \
+ ${RDFREMONT_BASE}/fdts/${PLAT}_nt_fw_config.dts
+
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+# Add the NT_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config))
+
+# Features for RD-Fremont variants
+override ENABLE_FEAT_MPAM := 2
+override ENABLE_FEAT_AMU := 2
+override ENABLE_SVE_FOR_SWD := 1
+override ENABLE_SVE_FOR_NS := 2
+override ENABLE_FEAT_MTE2 := 2
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c
new file mode 100644
index 0000000..92e96c2
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl1_measured_boot.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <drivers/arm/rse_comms.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
+#include <lib/psa/measured_boot.h>
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+#include <nrd_plat.h>
+#include <rdfremont_rse_comms.h>
+
+/*
+ * Platform specific table with image IDs and metadata. Intentionally not a
+ * const struct, some members might set by bootloaders during trusted boot.
+ */
+struct rse_mboot_metadata rdfremont_rse_mboot_metadata[] = {
+ {
+ .id = FW_CONFIG_ID,
+ .slot = U(8),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_FW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = TB_FW_CONFIG_ID,
+ .slot = U(9),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_TB_FW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = BL2_IMAGE_ID,
+ .slot = U(10),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_BL2_IMAGE_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = RSE_MBOOT_INVALID_ID
+ }
+};
+
+void bl1_plat_mboot_init(void)
+{
+ /* Initialize the communication channel between AP and RSE */
+ (void)plat_rse_comms_init();
+
+ rse_measured_boot_init(rdfremont_rse_mboot_metadata);
+}
+
+void bl1_plat_mboot_finish(void)
+{
+ /* Nothing to do. */
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c
new file mode 100644
index 0000000..570c33a
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_measured_boot.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <drivers/arm/rse_comms.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
+#include <lib/psa/measured_boot.h>
+#include <plat/common/common_def.h>
+#include <platform_def.h>
+
+#include <nrd_plat.h>
+#include <rdfremont_rse_comms.h>
+
+/*
+ * Platform specific table with image IDs and metadata. Intentionally not a
+ * const struct, some members might set by bootloaders during trusted boot.
+ */
+struct rse_mboot_metadata rdfremont_rse_mboot_metadata[] = {
+ {
+ .id = BL31_IMAGE_ID,
+ .slot = U(11),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_BL31_IMAGE_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = HW_CONFIG_ID,
+ .slot = U(12),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_HW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+ {
+ .id = SOC_FW_CONFIG_ID,
+ .slot = U(13),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_SOC_FW_CONFIG_STRING,
+ .lock_measurement = false
+ },
+#if ENABLE_RME
+ {
+ .id = RMM_IMAGE_ID,
+ .slot = U(14),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_RMM_IMAGE_STRING,
+ .lock_measurement = false
+ },
+#endif /* ENABLE_RME */
+ {
+ .id = RSE_MBOOT_INVALID_ID
+ }
+};
+
+void bl2_plat_mboot_init(void)
+{
+ /* Initialize the communication channel between AP and RSE */
+ (void)plat_rse_comms_init();
+
+ rse_measured_boot_init(rdfremont_rse_mboot_metadata);
+}
+
+void bl2_plat_mboot_finish(void)
+{
+ /* Nothing to do. */
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c
new file mode 100644
index 0000000..8dac8d3
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl2_setup.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/gpt_rme/gpt_rme.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <nrd_plat.h>
+
+/*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+static pas_region_t pas_regions[] = {
+ NRD_PAS_SHARED_SRAM,
+ NRD_PAS_SYSTEM_NCI,
+ NRD_PAS_DEBUG_NIC,
+ NRD_PAS_NS_UART,
+ NRD_PAS_REALM_UART,
+ NRD_PAS_AP_NS_WDOG,
+ NRD_PAS_AP_ROOT_WDOG,
+ NRD_PAS_AP_SECURE_WDOG,
+ NRD_PAS_SECURE_SRAM_ERB_AP,
+ NRD_PAS_NS_SRAM_ERB_AP,
+ NRD_PAS_ROOT_SRAM_ERB_AP,
+ NRD_PAS_REALM_SRAM_ERB_AP,
+ NRD_PAS_SECURE_SRAM_ERB_SCP,
+ NRD_PAS_NS_SRAM_ERB_SCP,
+ NRD_PAS_ROOT_SRAM_ERB_SCP,
+ NRD_PAS_REALM_SRAM_ERB_SCP,
+ NRD_PAS_SECURE_SRAM_ERB_MCP,
+ NRD_PAS_NS_SRAM_ERB_MCP,
+ NRD_PAS_ROOT_SRAM_ERB_MCP,
+ NRD_PAS_REALM_SRAM_ERB_MCP,
+ NRD_PAS_SECURE_SRAM_ERB_RSE,
+ NRD_PAS_NS_SRAM_ERB_RSE,
+ NRD_PAS_ROOT_SRAM_ERB_RSE,
+ NRD_PAS_REALM_SRAM_ERB_RSE,
+ NRD_PAS_RSE_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_RSE_NS_SRAM_ERB_RSM,
+ NRD_PAS_SCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_SCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_MCP_SECURE_SRAM_ERB_RSM,
+ NRD_PAS_MCP_NS_SRAM_ERB_RSM,
+ NRD_PAS_AP_SCP_ROOT_MHU,
+ NRD_PAS_AP_MCP_NS_MHU,
+ NRD_PAS_AP_MCP_SECURE_MHU,
+ NRD_PAS_AP_MCP_ROOT_MHU,
+ NRD_PAS_AP_RSE_NS_MHU,
+ NRD_PAS_AP_RSE_SECURE_MHU,
+ NRD_PAS_AP_RSE_ROOT_MHU,
+ NRD_PAS_AP_RSE_REALM_MHU,
+ NRD_PAS_SCP_MCP_RSE_CROSS_CHIP_MHU,
+ NRD_PAS_SYNCNT_MSTUPDTVAL_ADDR,
+ NRD_PAS_STM_SYSTEM_ITS,
+ NRD_PAS_SCP_MCP_RSE_SHARED_SRAM,
+ NRD_PAS_GIC,
+ NRD_PAS_NS_DRAM,
+ NRD_PAS_RMM,
+ NRD_PAS_L1GPT,
+ NRD_PAS_CMN,
+ NRD_PAS_LCP_PERIPHERAL,
+ NRD_PAS_DDR_IO,
+ NRD_PAS_SMMU_NCI_IO,
+ NRD_PAS_DRAM2_CHIP0,
+#if NRD_CHIP_COUNT > 1
+ NRD_PAS_DRAM1_CHIP1,
+ NRD_PAS_DRAM2_CHIP1,
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_PAS_DRAM1_CHIP2,
+ NRD_PAS_DRAM2_CHIP2,
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_PAS_DRAM1_CHIP3,
+ NRD_PAS_DRAM2_CHIP3
+#endif
+};
+
+static const arm_gpt_info_t arm_gpt_info = {
+ .pas_region_base = pas_regions,
+ .pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
+ .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
+ .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
+ .l0_size = (size_t)ARM_L0_GPT_SIZE,
+ .l1_size = (size_t)ARM_L1_GPT_SIZE,
+ .pps = GPCCR_PPS_256TB,
+ .pgs = GPCCR_PGS_4K
+};
+
+const arm_gpt_info_t *plat_arm_get_gpt_info(void)
+{
+ return &arm_gpt_info;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
new file mode 100644
index 0000000..8544930
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/rse_comms.h>
+#include <drivers/arm/smmu_v3.h>
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <nrd_plat.h>
+#include <nrd_variant.h>
+#include <rdfremont_rse_comms.h>
+
+#if (NRD_PLATFORM_VARIANT == 2)
+static const mmap_region_t rdfremontmc_dynamic_mmap[] = {
+#if NRD_CHIP_COUNT > 1
+ NRD_CSS_SHARED_RAM_MMAP(1),
+ NRD_CSS_PERIPH_MMAP(1),
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_CSS_SHARED_RAM_MMAP(2),
+ NRD_CSS_PERIPH_MMAP(2),
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_CSS_SHARED_RAM_MMAP(3),
+ NRD_CSS_PERIPH_MMAP(3),
+#endif
+};
+
+static struct gic600_multichip_data rdfremontmc_multichip_data __init = {
+ .rt_owner_base = PLAT_ARM_GICD_BASE,
+ .rt_owner = 0,
+ .chip_count = NRD_CHIP_COUNT,
+ .chip_addrs = {
+ PLAT_ARM_GICD_BASE >> 16,
+#if NRD_CHIP_COUNT > 1
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+#endif
+#if NRD_CHIP_COUNT > 2
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+#endif
+#if NRD_CHIP_COUNT > 3
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+#endif
+ },
+ .spi_ids = {
+ {PLAT_ARM_GICD_BASE, 32, 511},
+#if NRD_CHIP_COUNT > 1
+ {PLAT_ARM_GICD_BASE, 512, 991},
+#endif
+#if NRD_CHIP_COUNT > 2
+ {PLAT_ARM_GICD_BASE, 4096, 4575},
+#endif
+#if NRD_CHIP_COUNT > 3
+ {PLAT_ARM_GICD_BASE, 4576, 5055},
+#endif
+ }
+};
+
+static uintptr_t rdfremontmc_multichip_gicr_frames[] = {
+ /* Chip 0's GICR Base */
+ PLAT_ARM_GICR_BASE,
+#if NRD_CHIP_COUNT > 1
+ /* Chip 1's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
+#endif
+#if NRD_CHIP_COUNT > 2
+ /* Chip 2's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
+#endif
+#if NRD_CHIP_COUNT > 3
+ /* Chip 3's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
+#endif
+ UL(0) /* Zero Termination */
+};
+#endif /* NRD_PLATFORM_VARIANT == 2 */
+
+void bl31_platform_setup(void)
+{
+ /*
+ * Perform SMMUv3 GPT configuration for the GPC SMMU present in system
+ * control block on RD-Fremont platforms. This SMMUv3 initialization is
+ * not fatal.
+ *
+ * Don't perform smmuv3_security_init() for this instance of SMMUv3 as
+ * the global aborts need not be configured to allow the components in
+ * system control block send transations downstream to SMMUv3.
+ */
+ if (smmuv3_init(NRD_CSS_GPC_SMMUV3_BASE) != 0) {
+ WARN("Failed initializing System SMMU.\n");
+ }
+
+#if (NRD_PLATFORM_VARIANT == 2)
+ int ret;
+ unsigned int i;
+
+ if (plat_arm_nrd_get_multi_chip_mode() == 0) {
+ ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
+ NRD_CHIP_COUNT);
+ panic();
+ } else {
+ INFO("Enabling multi-chip support for RD-Fremont variant\n");
+
+ for (i = 0; i < ARRAY_SIZE(rdfremontmc_dynamic_mmap); i++) {
+ ret = mmap_add_dynamic_region(
+ rdfremontmc_dynamic_mmap[i].base_pa,
+ rdfremontmc_dynamic_mmap[i].base_va,
+ rdfremontmc_dynamic_mmap[i].size,
+ rdfremontmc_dynamic_mmap[i].attr);
+ if (ret != 0) {
+ ERROR("Failed to add entry i: %d (ret=%d)\n",
+ i, ret);
+ panic();
+ }
+ }
+
+ plat_arm_override_gicr_frames(
+ rdfremontmc_multichip_gicr_frames);
+ gic600_multichip_init(&rdfremontmc_multichip_data);
+ }
+#endif /* NRD_PLATFORM_VARIANT == 2 */
+ nrd_bl31_common_platform_setup();
+
+ if (plat_rse_comms_init() != 0) {
+ WARN("Failed initializing AP-RSE comms.\n");
+ }
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
new file mode 100644
index 0000000..31cc2a0
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
+#include <drivers/arm/rse_comms.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+#include <nrd_plat.h>
+#include <rdfremont_mhuv3.h>
+#include <rdfremont_rse_comms.h>
+
+unsigned int plat_arm_nrd_get_platform_id(void)
+{
+ return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) &
+ SID_SYSTEM_ID_PART_NUM_MASK;
+}
+
+unsigned int plat_arm_nrd_get_config_id(void)
+{
+ return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
+}
+
+unsigned int plat_arm_nrd_get_multi_chip_mode(void)
+{
+ return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
+ SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
+}
+
+/*
+ * Get a pointer to the RMM-EL3 shared buffer and return it
+ * through the pointer passed as parameter.
+ *
+ * This function returns the size of the shared buffer.
+ */
+size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
+{
+ *shared = (uintptr_t)RMM_SHARED_BASE;
+
+ return (size_t)RMM_SHARED_SIZE;
+}
+
+int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
+{
+ uint64_t checksum, num_banks, num_consoles;
+ struct ns_dram_bank *bank_ptr;
+ struct console_info *console_ptr;
+
+ assert(manifest != NULL);
+
+ /* DRAM Bank-1 and Bank-2 */
+ num_banks = 2;
+ assert(num_banks <= ARM_DRAM_NUM_BANKS);
+
+ /* Set number of consoles */
+ num_consoles = NRD_CSS_RMM_CONSOLE_COUNT;
+
+ manifest->version = RMMD_MANIFEST_VERSION;
+ manifest->padding = 0U; /* RES0 */
+ manifest->plat_data = (uintptr_t)NULL;
+ manifest->plat_dram.num_banks = num_banks;
+ manifest->plat_console.num_consoles = num_consoles;
+
+ /*
+ * Boot Manifest structure illustration, with two dram banks and
+ * a single console.
+ *
+ * +----------------------------------------+
+ * | offset | field | comment |
+ * +--------+----------------+--------------+
+ * | 0 | version | 0x00000003 |
+ * +--------+----------------+--------------+
+ * | 4 | padding | 0x00000000 |
+ * +--------+----------------+--------------+
+ * | 8 | plat_data | NULL |
+ * +--------+----------------+--------------+
+ * | 16 | num_banks | |
+ * +--------+----------------+ |
+ * | 24 | banks | plat_dram |
+ * +--------+----------------+ |
+ * | 32 | checksum | |
+ * +--------+----------------+--------------+
+ * | 40 | num_consoles | |
+ * +--------+----------------+ |
+ * | 48 | consoles | plat_console |
+ * +--------+----------------+ |
+ * | 56 | checksum | |
+ * +--------+----------------+--------------+
+ * | 64 | base 0 | |
+ * +--------+----------------+ bank[0] |
+ * | 72 | size 0 | |
+ * +--------+----------------+--------------+
+ * | 80 | base 1 | |
+ * +--------+----------------+ bank[1] |
+ * | 88 | size 1 | |
+ * +--------+----------------+--------------+
+ * | 96 | base | |
+ * +--------+----------------+ |
+ * | 104 | map_pages | |
+ * +--------+----------------+ |
+ * | 112 | name | |
+ * +--------+----------------+ consoles[0] |
+ * | 120 | clk_in_hz | |
+ * +--------+----------------+ |
+ * | 128 | baud_rate | |
+ * +--------+----------------+ |
+ * | 136 | flags | |
+ * +--------+----------------+--------------+
+ */
+
+ bank_ptr = (struct ns_dram_bank *)
+ (((uintptr_t)manifest) + sizeof(*manifest));
+ console_ptr = (struct console_info *)
+ ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr)));
+
+ manifest->plat_dram.banks = bank_ptr;
+ manifest->plat_console.consoles = console_ptr;
+
+ /* Ensure the manifest is not larger than the shared buffer */
+ assert((sizeof(struct rmm_manifest) +
+ (sizeof(struct console_info) *
+ manifest->plat_console.num_consoles) +
+ (sizeof(struct ns_dram_bank) * manifest->plat_dram.num_banks))
+ <= ARM_EL3_RMM_SHARED_SIZE);
+
+ /* Calculate checksum of plat_dram structure */
+ checksum = num_banks + (uint64_t)bank_ptr;
+
+ /* Store FVP DRAM banks data in Boot Manifest */
+ bank_ptr[0].base = ARM_NS_DRAM1_BASE;
+ bank_ptr[0].size = ARM_NS_DRAM1_SIZE;
+
+ bank_ptr[1].base = ARM_DRAM2_BASE;
+ bank_ptr[1].size = ARM_DRAM2_SIZE;
+
+ /* Update checksum */
+ checksum += bank_ptr[0].base + bank_ptr[0].size + bank_ptr[1].base +
+ bank_ptr[1].size;
+
+ /* Checksum must be 0 */
+ manifest->plat_dram.checksum = ~checksum + 1UL;
+
+ /* Calculate the checksum of the plat_consoles structure */
+ checksum = num_consoles + (uint64_t)console_ptr;
+
+ /* Zero out the console info struct */
+ memset((void *)console_ptr, '\0',
+ sizeof(struct console_info) * num_consoles);
+
+ console_ptr[0].map_pages = 1;
+ console_ptr[0].base = NRD_CSS_RMM_CONSOLE_BASE;
+ console_ptr[0].clk_in_hz = NRD_CSS_RMM_CONSOLE_CLK_IN_HZ;
+ console_ptr[0].baud_rate = NRD_CSS_RMM_CONSOLE_BAUD;
+
+ strlcpy(console_ptr[0].name, NRD_CSS_RMM_CONSOLE_NAME,
+ sizeof(console_ptr[0].name));
+
+ /* Update checksum */
+ checksum += console_ptr[0].base + console_ptr[0].map_pages +
+ console_ptr[0].clk_in_hz + console_ptr[0].baud_rate;
+
+ /* Checksum must be 0 */
+ manifest->plat_console.checksum = ~checksum + 1UL;
+
+ return 0;
+}
+
+int plat_rse_comms_init(void)
+{
+ uintptr_t snd_base, rcv_base;
+
+ /* Get sender and receiver frames for AP-RSE communication */
+ mhu_v3_get_secure_device_base(&snd_base, true);
+ mhu_v3_get_secure_device_base(&rcv_base, false);
+
+ VERBOSE("Initializing the rse_comms now\n");
+ /* Initialize the communication channel between AP and RSE */
+ return rse_comms_init(snd_base, rcv_base);
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c
new file mode 100644
index 0000000..e95c544
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common_measured_boot.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/desc_image_load.h>
+#include <drivers/measured_boot/rse/rse_measured_boot.h>
+
+extern struct rse_mboot_metadata rdfremont_rse_mboot_metadata[];
+
+struct rse_mboot_metadata *plat_rse_mboot_get_metadata(void)
+{
+ return rdfremont_rse_mboot_metadata;
+}
+
+int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data)
+{
+ int err;
+
+ /* Calculate image hash and record data in RSE */
+ err = rse_mboot_measure_and_record(rdfremont_rse_mboot_metadata,
+ image_data->image_base,
+ image_data->image_size,
+ image_id);
+ if (err != 0) {
+ ERROR("Measure and record failed for image id %u, err (%i)\n",
+ image_id, err);
+ }
+
+ return err;
+}
+
+int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+{
+ return rse_mboot_set_signer_id(rdfremont_rse_mboot_metadata, pk_oid,
+ pk_ptr, pk_len);
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c
new file mode 100644
index 0000000..de6cc68
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * rdfremont error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ while (1) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c
new file mode 100644
index 0000000..41332cc
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_mhuv3.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include <nrd_css_def3.h>
+#include <nrd_plat.h>
+#include <rdfremont_mhuv3.h>
+
+void mhu_v3_get_secure_device_base(uintptr_t *base, bool sender)
+{
+ if (sender) {
+ *base = AP_RSE_ROOT_MHU_V3_PBX;
+ } else {
+ *base = AP_RSE_ROOT_MHU_V3_MBX;
+ }
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c
new file mode 100644
index 0000000..188a09f
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_plat_attest_token.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdint.h>
+
+#include <cca_attestation.h>
+#include <common/debug.h>
+#include <psa/error.h>
+
+int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size)
+{
+ psa_status_t ret;
+
+ ret = cca_attestation_get_plat_token(buf, len, hash, hash_size);
+ if (ret != PSA_SUCCESS) {
+ ERROR("Unable to fetch CCA attestation token\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c
new file mode 100644
index 0000000..224c20b
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_realm_attest_key.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdint.h>
+
+#include <cca_attestation.h>
+#include <common/debug.h>
+#include <psa/error.h>
+
+int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
+ unsigned int type)
+{
+ psa_status_t ret;
+
+ ret = cca_attestation_get_realm_key(buf, len, type);
+ if (ret != PSA_SUCCESS) {
+ ERROR("Unable to fetch CCA attestation key\n");
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c
new file mode 100644
index 0000000..a12d3e2
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_security.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Placeholder function to resolve build dependency */
+void plat_arm_security_setup(void)
+{
+}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
new file mode 100644
index 0000000..e7931d4
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+const unsigned char rd_fremont_pd_tree_desc[] = {
+ (PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1))
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 2))
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (PLAT_ARM_CLUSTER_COUNT > 12 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 3))
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return rd_fremont_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+#if (NRD_PLATFORM_VARIANT == 2)
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+#if (NRD_CHIP_COUNT > 1)
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (NRD_CHIP_COUNT > 2)
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (NRD_CHIP_COUNT > 3)
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+};
+#else
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+#if (NRD_PLATFORM_VARIANT == 0)
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+#endif
+};
+#endif
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c
new file mode 100644
index 0000000..6aec208
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_trusted_boot.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier ::= SEQUENCE {
+ * algorithm OBJECT IDENTIFIER,
+ * parameters ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ * digestAlgorithm AlgorithmIdentifier,
+ * digest OCTET STRING
+ * }
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}