feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index 6a38657..b9ca3f6 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -58,4 +58,12 @@
}
#endif
+#ifdef PLAT_sun50i_h616
+void sunxi_soc_fdt_fixup(void *dtb);
+#else
+static inline void sunxi_soc_fdt_fixup(void *dtb)
+{
+}
+#endif
+
#endif /* SUNXI_PRIVATE_H */