feat(allwinner): adjust H616 L2 cache size in DTB
The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.
Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.
The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.
Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index 6a38657..b9ca3f6 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -58,4 +58,12 @@
}
#endif
+#ifdef PLAT_sun50i_h616
+void sunxi_soc_fdt_fixup(void *dtb);
+#else
+static inline void sunxi_soc_fdt_fixup(void *dtb)
+{
+}
+#endif
+
#endif /* SUNXI_PRIVATE_H */
diff --git a/plat/allwinner/common/sunxi_prepare_dtb.c b/plat/allwinner/common/sunxi_prepare_dtb.c
index 66af35a..0f68974 100644
--- a/plat/allwinner/common/sunxi_prepare_dtb.c
+++ b/plat/allwinner/common/sunxi_prepare_dtb.c
@@ -34,6 +34,8 @@
}
#endif
+ sunxi_soc_fdt_fixup(fdt);
+
if (sunxi_psci_is_scpi()) {
ret = fdt_add_cpu_idle_states(fdt, sunxi_idle_states);
if (ret < 0) {
diff --git a/plat/allwinner/sun50i_h616/platform.mk b/plat/allwinner/sun50i_h616/platform.mk
index e83ef58..6f44e8c 100644
--- a/plat/allwinner/sun50i_h616/platform.mk
+++ b/plat/allwinner/sun50i_h616/platform.mk
@@ -21,4 +21,5 @@
BL31_SOURCES += common/fdt_wrappers.c \
drivers/allwinner/axp/axp805.c \
drivers/allwinner/sunxi_rsb.c \
- drivers/mentor/i2c/mi2cv.c
+ drivers/mentor/i2c/mi2cv.c \
+ ${AW_PLAT}/${PLAT}/sunxi_h616_dtb.c
diff --git a/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c b/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
new file mode 100644
index 0000000..ec49f4c
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/sunxi_h616_dtb.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Amend the device tree to adjust the L2 cache size, which is different
+ * between the revisions of the H616 chips: earlier versions have 256 KB of L2,
+ * later versions 1 MB.
+ * Read the cache ID registers and adjust the size and number of sets entries
+ * in the L2 cache DT node.
+ */
+
+#include <common/fdt_wrappers.h>
+#include <lib/utils_def.h>
+#include <libfdt.h>
+
+#define CACHE_L1D 0x0
+#define CACHE_L1I 0x1
+#define CACHE_L2U 0x2
+
+#define CCSIDR_SETS_SHIFT 13
+#define CCSIDR_SETS_MASK GENMASK(14, 0)
+#define CCSIDR_ASSOC_SHIFT 3
+#define CCSIDR_ASSOC_MASK GENMASK(9, 0)
+#define CCSIDR_LSIZE_SHIFT 0
+#define CCSIDR_LSIZE_MASK GENMASK(2, 0)
+
+static uint32_t armv8_get_ccsidr(unsigned int sel)
+{
+ uint32_t reg;
+
+ __asm__ volatile ("msr CSSELR_EL1, %0\n" :: "r" (sel));
+ __asm__ volatile ("mrs %0, CCSIDR_EL1\n" : "=r" (reg));
+
+ return reg;
+}
+
+void sunxi_soc_fdt_fixup(void *dtb)
+{
+ int node = fdt_path_offset(dtb, "/cpus/cpu@0");
+ uint32_t phandle, ccsidr, cell;
+ int sets, line_size, assoc;
+ int ret;
+
+ if (node < 0) {
+ return;
+ }
+
+ ret = fdt_read_uint32(dtb, node, "next-level-cache", &phandle);
+ if (ret != 0) {
+ return;
+ }
+
+ node = fdt_node_offset_by_phandle(dtb, phandle);
+ if (ret != 0) {
+ return;
+ }
+
+ ccsidr = armv8_get_ccsidr(CACHE_L2U);
+ sets = ((ccsidr >> CCSIDR_SETS_SHIFT) & CCSIDR_SETS_MASK) + 1;
+ line_size = 16U << ((ccsidr >> CCSIDR_LSIZE_SHIFT) & CCSIDR_LSIZE_MASK);
+ assoc = ((ccsidr >> CCSIDR_ASSOC_SHIFT) & CCSIDR_ASSOC_MASK) + 1;
+
+ cell = cpu_to_fdt32(sets);
+ fdt_setprop(dtb, node, "cache-sets", &cell, sizeof(cell));
+
+ cell = cpu_to_fdt32(line_size);
+ fdt_setprop(dtb, node, "cache-line-size", &cell, sizeof(cell));
+
+ cell = cpu_to_fdt32(sets * assoc * line_size);
+ fdt_setprop(dtb, node, "cache-size", &cell, sizeof(cell));
+}