commit ac838c59a065e40d81827318c5a6cca7bdfa12c2
author Dimitris Papastamos <dimitris.papastamos@arm.com> Tue Jun 13 12:33:39 2017 +0100
committer Dimitris Papastamos <dimitris.papastamos@arm.com> Tue Jun 20 15:14:01 2017 +0100
tree 09e5830a29733f3831a6d7a2e5eddb7d0f1d5f5d
parent 2b40ca6e2eb472c9d01cc55a1b6dee7a875be970

aarch32: Fix L2CTRL definition for Cortex A57 and A72

Fixes ARM-software/tf-issues#495

Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

include/lib/cpus/aarch32/cortex_a57.h

diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index 1c3fa25..1486b98 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -55,7 +55,7 @@
 /*******************************************************************************
  * L2 Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A57_L2CTLR			p15, 1, c9, c0, 3
+#define CORTEX_A57_L2CTLR			p15, 1, c9, c0, 2
 
 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT	6