diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 22fd2ac..0ae00b5 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -242,28 +242,28 @@
 	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
 	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
-	its1: its@30040000 {
+	its1: msi-controller@30040000 {
 		compatible = "arm,gic-v3-its";
 		msi-controller;
 		#msi-cells = <1>;
 		reg = <0x0 0x30040000 0x0 0x20000>;
 	};
 
-	its2: its@30060000 {
+	its2: msi-controller@30060000 {
 		compatible = "arm,gic-v3-its";
 		msi-controller;
 		#msi-cells = <1>;
 		reg = <0x0 0x30060000 0x0 0x20000>;
 	};
 
-	its_ccix: its@30080000 {
+	its_ccix: msi-controller@30080000 {
 		compatible = "arm,gic-v3-its";
 		msi-controller;
 		#msi-cells = <1>;
 		reg = <0x0 0x30080000 0x0 0x20000>;
 	};
 
-	its_pcie: its@300a0000 {
+	its_pcie: msi-controller@300a0000 {
 		compatible = "arm,gic-v3-its";
 		msi-controller;
 		#msi-cells = <1>;
diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi
index f119820..54af9ac 100644
--- a/fdts/morello.dtsi
+++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -70,12 +70,12 @@
 		#size-cells = <1>;
 		ranges = <0 0x0 0x06000000 0x8000>;
 
-		cpu_scp_hpri0: scp-shmem@0 {
+		cpu_scp_hpri0: scp-sram@0 {
 			compatible = "arm,scmi-shmem";
 			reg = <0x0 0x80>;
 		};
 
-		cpu_scp_hpri1: scp-shmem@80 {
+		cpu_scp_hpri1: scp-sram@80 {
 			compatible = "arm,scmi-shmem";
 			reg = <0x80 0x80>;
 		};
@@ -95,7 +95,7 @@
 		clock-output-names = "uartclk";
 	};
 
-	soc_uart0: uart@2a400000 {
+	soc_uart0: serial@2a400000 {
 		compatible = "arm,pl011", "arm,primecell";
 		reg = <0x0 0x2a400000 0x0 0x1000>;
 		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;