refactor(cpus): reorder Cortex-A710 errata by ascending order
Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.
Change-Id: I4a6ed55d48e91ec914b7a591c6d30da5ce5d915d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index cebd6f0..774de73 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,74 +69,48 @@
b cpu_rev_var_ls
endfunc check_errata_1987031
-/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2081180.
- * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
- * It is still open.
+/* ---------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2008768.
+ * This applies to revision r0p0, r1p0 and r2p0.
+ * It is fixed in r2p1.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+ * Shall clobber: x0, x1, x2, x17
+ * ---------------------------------------------------------------
*/
-func errata_a710_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
+func errata_a710_2008768_wa
+ mov x17, x30
+ bl check_errata_2008768
+ cbz x0, 1f
- /* Apply instruction patching sequence */
- ldr x0,=0x3
- msr S3_6_c15_c8_0,x0
- ldr x0,=0xF3A08002
- msr S3_6_c15_c8_2,x0
- ldr x0,=0xFFF0F7FE
- msr S3_6_c15_c8_3,x0
- ldr x0,=0x10002001003FF
- msr S3_6_c15_c8_1,x0
- ldr x0,=0x4
- msr S3_6_c15_c8_0,x0
- ldr x0,=0xBF200000
- msr S3_6_c15_c8_2,x0
- ldr x0,=0xFFEF0000
- msr S3_6_c15_c8_3,x0
- ldr x0,=0x10002001003F3
- msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a710_2081180_wa
+ /* Stash ERRSELR_EL1 in x2 */
+ mrs x2, ERRSELR_EL1
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
+ /* Select error record 0 and clear ED bit */
+ msr ERRSELR_EL1, xzr
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
-/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2055002.
- * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------------
- */
-func errata_a710_2055002_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2055002
- cbz x0, 1f
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
- msr CORTEX_A710_CPUACTLR_EL1, x1
+ /* Select error record 1 and clear ED bit */
+ mov x0, #1
+ msr ERRSELR_EL1, x0
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
+
+ /* Restore ERRSELR_EL1 from x2 */
+ msr ERRSELR_EL1, x2
+
1:
- ret x17
-endfunc errata_a710_2055002_wa
+ ret x17
+endfunc errata_a710_2008768_wa
-func check_errata_2055002
- /* Applies to r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2055002
+func check_errata_2008768
+ /* Applies to r0p0, r1p0 and r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2008768
/* -------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2017096.
@@ -165,33 +139,31 @@
b cpu_rev_var_ls
endfunc check_errata_2017096
-
/* ---------------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2083908.
- * This applies to revision r2p0 of Cortex-A710 and is still open.
+ * Errata Workaround for Cortex-A710 Erratum 2055002.
+ * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* ---------------------------------------------------------------------
*/
-func errata_a710_2083908_wa
+func errata_a710_2055002_wa
/* Compare x0 against revision r2p0 */
mov x17, x30
- bl check_errata_2083908
+ bl check_errata_2055002
cbz x0, 1f
- mrs x1, CORTEX_A710_CPUACTLR5_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
- msr CORTEX_A710_CPUACTLR5_EL1, x1
+ mrs x1, CORTEX_A710_CPUACTLR_EL1
+ orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
+ msr CORTEX_A710_CPUACTLR_EL1, x1
1:
ret x17
-endfunc errata_a710_2083908_wa
+endfunc errata_a710_2055002_wa
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #CPU_REV(2, 0)
- mov x2, #CPU_REV(2, 0)
- b cpu_rev_var_range
-endfunc check_errata_2083908
+func check_errata_2055002
+ /* Applies to r1p0, r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2055002
/* ---------------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2058056.
@@ -222,33 +194,75 @@
endfunc check_errata_2058056
/* --------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2267065.
- * This applies to revisions r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
+ * Errata Workaround for Cortex-A710 Erratum 2081180.
+ * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
+ * It is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
+ * Shall clobber: x0-x17
* --------------------------------------------------
*/
-func errata_a710_2267065_wa
- /* Compare x0 against revision r2p0 */
+func errata_a710_2081180_wa
+ /* Check revision. */
mov x17, x30
- bl check_errata_2267065
+ bl check_errata_2081180
cbz x0, 1f
/* Apply instruction patching sequence */
- mrs x1, CORTEX_A710_CPUACTLR_EL1
- orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
- msr CORTEX_A710_CPUACTLR_EL1, x1
+ ldr x0,=0x3
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xF3A08002
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFF0F7FE
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x10002001003FF
+ msr S3_6_c15_c8_1,x0
+ ldr x0,=0x4
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xBF200000
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0000
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x10002001003F3
+ msr S3_6_c15_c8_1,x0
+ isb
1:
ret x17
-endfunc errata_a710_2267065_wa
+endfunc errata_a710_2081180_wa
-func check_errata_2267065
+func check_errata_2081180
/* Applies to r0p0, r1p0 and r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
-endfunc check_errata_2267065
+endfunc check_errata_2081180
+
+
+/* ---------------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2083908.
+ * This applies to revision r2p0 of Cortex-A710 and is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------------
+ */
+func errata_a710_2083908_wa
+ /* Compare x0 against revision r2p0 */
+ mov x17, x30
+ bl check_errata_2083908
+ cbz x0, 1f
+ mrs x1, CORTEX_A710_CPUACTLR5_EL1
+ orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13
+ msr CORTEX_A710_CPUACTLR5_EL1, x1
+1:
+ ret x17
+endfunc errata_a710_2083908_wa
+
+func check_errata_2083908
+ /* Applies to r2p0 */
+ mov x1, #CPU_REV(2, 0)
+ mov x2, #CPU_REV(2, 0)
+ b cpu_rev_var_range
+endfunc check_errata_2083908
/* ---------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2136059.
@@ -353,6 +367,35 @@
b cpu_rev_var_ls
endfunc check_errata_2216384
+/* --------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2267065.
+ * This applies to revisions r0p0, r1p0 and r2p0.
+ * It is fixed in r2p1.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * --------------------------------------------------
+ */
+func errata_a710_2267065_wa
+ /* Compare x0 against revision r2p0 */
+ mov x17, x30
+ bl check_errata_2267065
+ cbz x0, 1f
+
+ /* Apply instruction patching sequence */
+ mrs x1, CORTEX_A710_CPUACTLR_EL1
+ orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22
+ msr CORTEX_A710_CPUACTLR_EL1, x1
+1:
+ ret x17
+endfunc errata_a710_2267065_wa
+
+func check_errata_2267065
+ /* Applies to r0p0, r1p0 and r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2267065
+
/* ---------------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2282622.
* This applies to revision r0p0, r1p0, r2p0 and r2p1.
@@ -411,49 +454,6 @@
b cpu_rev_var_ls
endfunc check_errata_2291219
-/* ---------------------------------------------------------------
- * Errata Workaround for Cortex-A710 Erratum 2008768.
- * This applies to revision r0p0, r1p0 and r2p0.
- * It is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * ---------------------------------------------------------------
- */
-func errata_a710_2008768_wa
- mov x17, x30
- bl check_errata_2008768
- cbz x0, 1f
-
- /* Stash ERRSELR_EL1 in x2 */
- mrs x2, ERRSELR_EL1
-
- /* Select error record 0 and clear ED bit */
- msr ERRSELR_EL1, xzr
- mrs x1, ERXCTLR_EL1
- bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
- msr ERXCTLR_EL1, x1
-
- /* Select error record 1 and clear ED bit */
- mov x0, #1
- msr ERRSELR_EL1, x0
- mrs x1, ERXCTLR_EL1
- bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
- msr ERXCTLR_EL1, x1
-
- /* Restore ERRSELR_EL1 from x2 */
- msr ERRSELR_EL1, x2
-
-1:
- ret x17
-endfunc errata_a710_2008768_wa
-
-func check_errata_2008768
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2008768
-
/* -------------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2371105.
* This applies to revisions <= r2p0 and is fixed in r2p1.