Merge pull request #1721 from marex/arm/master/memsize-passing-v2
plat: rcar: Move FDT from x3 to x1
diff --git a/Makefile b/Makefile
index 2d01648..5c61f8d 100644
--- a/Makefile
+++ b/Makefile
@@ -154,7 +154,7 @@
march32-directive = -march=armv8-a
endif
-ifeq ($(notdir $(CC)),armclang)
+ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi -march=armv8-a
LD = $(LINKER)
@@ -188,8 +188,50 @@
ASFLAGS_aarch32 = $(march32-directive)
ASFLAGS_aarch64 = -march=armv8-a
+WARNING1 := -Wextra
+WARNING1 += -Wunused -Wno-unused-parameter
+WARNING1 += -Wmissing-declarations
+WARNING1 += -Wmissing-format-attribute
+WARNING1 += -Wmissing-prototypes
+WARNING1 += -Wold-style-definition
+WARNING1 += -Wunused-but-set-variable
+WARNING1 += -Wunused-const-variable
+
+WARNING2 := -Waggregate-return
+WARNING2 += -Wcast-align
+WARNING2 += -Wdisabled-optimization
+WARNING2 += -Wnested-externs
+WARNING2 += -Wshadow
+WARNING2 += -Wlogical-op
+WARNING2 += -Wmissing-field-initializers
+WARNING2 += -Wsign-compare
+WARNING2 += -Wmaybe-uninitialized
+
+WARNING3 := -Wbad-function-cast
+WARNING3 += -Wcast-qual
+WARNING3 += -Wconversion
+WARNING3 += -Wpacked
+WARNING3 += -Wpadded
+WARNING3 += -Wpointer-arith
+WARNING3 += -Wredundant-decls
+WARNING3 += -Wswitch-default
+WARNING3 += -Wpacked-bitfield-compat
+WARNING3 += -Wvla
+
+ifeq (${W},1)
+WARNINGS := $(WARNING1)
+else ifeq (${W},2)
+WARNINGS := $(WARNING1) $(WARNING2)
+else ifeq (${W},3)
+WARNINGS := $(WARNING1) $(WARNING2) $(WARNING3)
+endif
+
+ifneq (${E},0)
+ERRORS := -Werror
+endif
+
CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
- -Wmissing-include-dirs -Werror
+ -Wmissing-include-dirs $(ERRORS) $(WARNINGS)
ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \
-D__ASSEMBLY__ -ffreestanding \
-Wa,--fatal-warnings
@@ -838,7 +880,7 @@
.PHONY: libraries
romlib.bin: libraries
- ${Q}${MAKE} BUILD_PLAT=${BUILD_PLAT} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
+ ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
cscope:
@echo " CSCOPE"
diff --git a/bl2/aarch32/bl2_arch_setup.c b/bl2/aarch32/bl2_arch_setup.c
index db8a068..4fd8d07 100644
--- a/bl2/aarch32/bl2_arch_setup.c
+++ b/bl2/aarch32/bl2_arch_setup.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include "../bl2_private.h"
/*******************************************************************************
* Place holder function to perform any Secure SVC specific architectural
diff --git a/bl2/bl2_private.h b/bl2/bl2_private.h
index 7fd17bf..01f6c6b 100644
--- a/bl2/bl2_private.h
+++ b/bl2/bl2_private.h
@@ -8,6 +8,9 @@
#define BL2_PRIVATE_H
#if BL2_IN_XIP_MEM
+
+#include <stdint.h>
+
/*******************************************************************************
* Declarations of linker defined symbols which will tell us where BL2 lives
* in Trusted ROM and RAM
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 43d0ed4..fd53ed8 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -66,11 +66,11 @@
__CPU_OPS_END__ = .;
/*
- * Keep the .got section in the RO section as the it is patched
+ * Keep the .got section in the RO section as it is patched
* prior to enabling the MMU and having the .got in RO is better for
- * security.
+ * security. GOT is a table of addresses so ensure 8-byte alignment.
*/
- . = ALIGN(16);
+ . = ALIGN(8);
__GOT_START__ = .;
*(.got)
__GOT_END__ = .;
@@ -112,6 +112,16 @@
KEEP(*(cpu_ops))
__CPU_OPS_END__ = .;
+ /*
+ * Keep the .got section in the RO section as it is patched
+ * prior to enabling the MMU and having the .got in RO is better for
+ * security. GOT is a table of addresses so ensure 8-byte alignment.
+ */
+ . = ALIGN(8);
+ __GOT_START__ = .;
+ *(.got)
+ __GOT_END__ = .;
+
/* Place pubsub sections for events */
. = ALIGN(8);
#include <pubsub_events.h>
@@ -165,11 +175,12 @@
__DATA_END__ = .;
} >RAM
- . = ALIGN(16);
/*
* .rela.dyn needs to come after .data for the read-elf utility to parse
- * this section correctly.
+ * this section correctly. Ensure 8-byte alignment so that the fields of
+ * RELA data structure are aligned.
*/
+ . = ALIGN(8);
__RELA_START__ = .;
.rela.dyn . : {
} >RAM
diff --git a/docs/marvell/build.txt b/docs/marvell/build.txt
index 0682b77..a00dbb5 100644
--- a/docs/marvell/build.txt
+++ b/docs/marvell/build.txt
@@ -167,7 +167,7 @@
(1) ARM cross compiler capable of building images for the service CPU (CM3).
This component is usually included in the Linux host packages.
- On Debian/Uboot hosts the default GNU ARM tool chain can be installed
+ On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed
using the following command::
> sudo apt-get install gcc-arm-linux-gnueabi
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index a8bd40c..103f1c7 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -1875,16 +1875,16 @@
-C cluster0.NUM_CORES=4 \
-C cluster1.NUM_CORES=4 \
-C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBAR=0x04020000 \
- -C cluster0.cpu1.RVBAR=0x04020000 \
- -C cluster0.cpu2.RVBAR=0x04020000 \
- -C cluster0.cpu3.RVBAR=0x04020000 \
- -C cluster1.cpu0.RVBAR=0x04020000 \
- -C cluster1.cpu1.RVBAR=0x04020000 \
- -C cluster1.cpu2.RVBAR=0x04020000 \
- -C cluster1.cpu3.RVBAR=0x04020000 \
- --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
+ -C cluster0.cpu0.RVBAR=0x04010000 \
+ -C cluster0.cpu1.RVBAR=0x04010000 \
+ -C cluster0.cpu2.RVBAR=0x04010000 \
+ -C cluster0.cpu3.RVBAR=0x04010000 \
+ -C cluster1.cpu0.RVBAR=0x04010000 \
+ -C cluster1.cpu1.RVBAR=0x04010000 \
+ -C cluster1.cpu2.RVBAR=0x04010000 \
+ -C cluster1.cpu3.RVBAR=0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
@@ -1892,6 +1892,9 @@
Notes:
+- Since Position Independent Executable (PIE) support is enabled for BL31
+ in this config, it can be loaded at any valid address for execution.
+
- Since a FIP is not loaded when using BL31 as reset entrypoint, the
``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
parameter is needed to load the individual bootloader images in memory.
@@ -1932,14 +1935,14 @@
-C cluster1.cpu1.CONFIG64=0 \
-C cluster1.cpu2.CONFIG64=0 \
-C cluster1.cpu3.CONFIG64=0 \
- -C cluster0.cpu0.RVBAR=0x04001000 \
- -C cluster0.cpu1.RVBAR=0x04001000 \
- -C cluster0.cpu2.RVBAR=0x04001000 \
- -C cluster0.cpu3.RVBAR=0x04001000 \
- -C cluster1.cpu0.RVBAR=0x04001000 \
- -C cluster1.cpu1.RVBAR=0x04001000 \
- -C cluster1.cpu2.RVBAR=0x04001000 \
- -C cluster1.cpu3.RVBAR=0x04001000 \
+ -C cluster0.cpu0.RVBAR=0x04002000 \
+ -C cluster0.cpu1.RVBAR=0x04002000 \
+ -C cluster0.cpu2.RVBAR=0x04002000 \
+ -C cluster0.cpu3.RVBAR=0x04002000 \
+ -C cluster1.cpu0.RVBAR=0x04002000 \
+ -C cluster1.cpu1.RVBAR=0x04002000 \
+ -C cluster1.cpu2.RVBAR=0x04002000 \
+ -C cluster1.cpu3.RVBAR=0x04002000 \
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
@@ -1962,16 +1965,16 @@
-C bp.secure_memory=1 \
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBARADDR=0x04020000 \
- -C cluster0.cpu1.RVBARADDR=0x04020000 \
- -C cluster0.cpu2.RVBARADDR=0x04020000 \
- -C cluster0.cpu3.RVBARADDR=0x04020000 \
- -C cluster1.cpu0.RVBARADDR=0x04020000 \
- -C cluster1.cpu1.RVBARADDR=0x04020000 \
- -C cluster1.cpu2.RVBARADDR=0x04020000 \
- -C cluster1.cpu3.RVBARADDR=0x04020000 \
- --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
- --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
+ -C cluster0.cpu0.RVBARADDR=0x04010000 \
+ -C cluster0.cpu1.RVBARADDR=0x04010000 \
+ -C cluster0.cpu2.RVBARADDR=0x04010000 \
+ -C cluster0.cpu3.RVBARADDR=0x04010000 \
+ -C cluster1.cpu0.RVBARADDR=0x04010000 \
+ -C cluster1.cpu1.RVBARADDR=0x04010000 \
+ -C cluster1.cpu2.RVBARADDR=0x04010000 \
+ -C cluster1.cpu3.RVBARADDR=0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
+ --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
@@ -1990,10 +1993,10 @@
-C bp.secure_memory=1 \
-C bp.tzc_400.diagnostics=1 \
-C cache_state_modelled=1 \
- -C cluster0.cpu0.RVBARADDR=0x04001000 \
- -C cluster0.cpu1.RVBARADDR=0x04001000 \
- -C cluster0.cpu2.RVBARADDR=0x04001000 \
- -C cluster0.cpu3.RVBARADDR=0x04001000 \
+ -C cluster0.cpu0.RVBARADDR=0x04002000 \
+ -C cluster0.cpu1.RVBARADDR=0x04002000 \
+ -C cluster0.cpu2.RVBARADDR=0x04002000 \
+ -C cluster0.cpu3.RVBARADDR=0x04002000 \
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c
index 59a7576..d46e020 100644
--- a/drivers/arm/ccn/ccn.c
+++ b/drivers/arm/ccn/ccn.c
@@ -553,7 +553,14 @@
return REGION_ID_LIMIT;
}
- region_id += node_pos_in_map;
+ /*
+ * According to section 3.1.1 in CCN specification, region offset for
+ * the RN-I components is calculated as (128 + NodeID of RN-I).
+ */
+ if (node_type == NODE_TYPE_RNI)
+ region_id += node_id;
+ else
+ region_id += node_pos_in_map;
return region_id;
}
diff --git a/drivers/io/io_block.c b/drivers/io/io_block.c
index 8226554..ff13113 100644
--- a/drivers/io/io_block.c
+++ b/drivers/io/io_block.c
@@ -67,8 +67,10 @@
static int find_first_block_state(const io_block_dev_spec_t *dev_spec,
unsigned int *index_out)
{
+ unsigned int index;
int result = -ENOENT;
- for (int index = 0; index < MAX_IO_BLOCK_DEVICES; ++index) {
+
+ for (index = 0U; index < MAX_IO_BLOCK_DEVICES; ++index) {
/* dev_spec is used as identifier since it's unique */
if (state_pool[index].dev_spec == dev_spec) {
result = 0;
diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h
index 2f5334f..a9ec7b7 100644
--- a/include/drivers/arm/gic_common.h
+++ b/include/drivers/arm/gic_common.h
@@ -35,11 +35,9 @@
#define GIC_INTR_CFG_LEVEL (0 << 1)
#define GIC_INTR_CFG_EDGE (1 << 1)
-/* Constants to categorise priorities */
+/* Highest possible interrupt priorities */
#define GIC_HIGHEST_SEC_PRIORITY U(0x00)
-#define GIC_LOWEST_SEC_PRIORITY U(0x7f)
#define GIC_HIGHEST_NS_PRIORITY U(0x80)
-#define GIC_LOWEST_NS_PRIORITY U(0xfe) /* 0xff would disable all interrupts */
/*******************************************************************************
* GIC Distributor interface register offsets that are common to GICv3 & GICv2
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index 7d1944c..a6fe14f 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -248,6 +248,19 @@
DEFINE_COPROCR_RW_FUNCS(cnthp_tval_el2, CNTHP_TVAL)
DEFINE_COPROCR_RW_FUNCS_64(cnthp_cval_el2, CNTHP_CVAL_64)
+#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
+ CNTP_CTL_ENABLE_MASK)
+#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
+ CNTP_CTL_IMASK_MASK)
+#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
+ CNTP_CTL_ISTATUS_MASK)
+
+#define set_cntp_ctl_enable(x) ((x) |= U(1) << CNTP_CTL_ENABLE_SHIFT)
+#define set_cntp_ctl_imask(x) ((x) |= U(1) << CNTP_CTL_IMASK_SHIFT)
+
+#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
+#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
+
DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
@@ -378,4 +391,59 @@
#define read_amcntenset0_el0() read_amcntenset0()
#define read_amcntenset1_el0() read_amcntenset1()
+/* Helper functions to manipulate CPSR */
+static inline void enable_irq(void)
+{
+ /*
+ * The compiler memory barrier will prevent the compiler from
+ * scheduling non-volatile memory access after the write to the
+ * register.
+ *
+ * This could happen if some initialization code issues non-volatile
+ * accesses to an area used by an interrupt handler, in the assumption
+ * that it is safe as the interrupts are disabled at the time it does
+ * that (according to program order). However, non-volatile accesses
+ * are not necessarily in program order relatively with volatile inline
+ * assembly statements (and volatile accesses).
+ */
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsie i");
+ isb();
+}
+
+static inline void enable_serror(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsie a");
+ isb();
+}
+
+static inline void enable_fiq(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsie f");
+ isb();
+}
+
+static inline void disable_irq(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsid i");
+ isb();
+}
+
+static inline void disable_serror(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsid a");
+ isb();
+}
+
+static inline void disable_fiq(void)
+{
+ COMPILER_BARRIER();
+ __asm__ volatile ("cpsid f");
+ isb();
+}
+
#endif /* ARCH_HELPERS_H */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 97595e9..6f81e1b 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -534,19 +534,6 @@
#define CNTP_CTL_IMASK_MASK U(1)
#define CNTP_CTL_ISTATUS_MASK U(1)
-#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
- CNTP_CTL_ENABLE_MASK)
-#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
- CNTP_CTL_IMASK_MASK)
-#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
- CNTP_CTL_ISTATUS_MASK)
-
-#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
-#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
-
-#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
-#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
-
/* Exception Syndrome register bits and bobs */
#define ESR_EC_SHIFT U(26)
#define ESR_EC_MASK U(0x3f)
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 8b3d53a..7222b9d 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -215,11 +215,81 @@
DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
DEFINE_SYSOP_FUNC(isb)
+static inline void enable_irq(void)
+{
+ /*
+ * The compiler memory barrier will prevent the compiler from
+ * scheduling non-volatile memory access after the write to the
+ * register.
+ *
+ * This could happen if some initialization code issues non-volatile
+ * accesses to an area used by an interrupt handler, in the assumption
+ * that it is safe as the interrupts are disabled at the time it does
+ * that (according to program order). However, non-volatile accesses
+ * are not necessarily in program order relatively with volatile inline
+ * assembly statements (and volatile accesses).
+ */
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_IRQ_BIT);
+ isb();
+}
+
+static inline void enable_fiq(void)
+{
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_FIQ_BIT);
+ isb();
+}
+
+static inline void enable_serror(void)
+{
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_ABT_BIT);
+ isb();
+}
+
+static inline void enable_debug_exceptions(void)
+{
+ COMPILER_BARRIER();
+ write_daifclr(DAIF_DBG_BIT);
+ isb();
+}
+
+static inline void disable_irq(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_IRQ_BIT);
+ isb();
+}
+
+static inline void disable_fiq(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_FIQ_BIT);
+ isb();
+}
+
+static inline void disable_serror(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_ABT_BIT);
+ isb();
+}
+
+static inline void disable_debug_exceptions(void)
+{
+ COMPILER_BARRIER();
+ write_daifset(DAIF_DBG_BIT);
+ isb();
+}
+
+#if !ERROR_DEPRECATED
uint32_t get_afflvl_shift(uint32_t);
uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
+#endif
void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
@@ -306,6 +376,19 @@
DEFINE_SYSREG_READ_FUNC(cntpct_el0)
DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
+#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
+ CNTP_CTL_ENABLE_MASK)
+#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
+ CNTP_CTL_IMASK_MASK)
+#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
+ CNTP_CTL_ISTATUS_MASK)
+
+#define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
+#define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
+
+#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
+#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
+
DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index cbac247..c5c10ab 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -407,12 +407,16 @@
#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
PLAT_ARM_MAX_BL31_SIZE)
#elif (RESET_TO_BL31)
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+# if !ENABLE_PIE
+# error "BL31 must be a PIE if RESET_TO_BL31=1."
+# endif
/*
- * Put BL31_BASE in the middle of the Trusted SRAM.
+ * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
+ * used for building BL31 when RESET_TO_BL31=1.
*/
-#define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
- (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
-#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#define BL31_BASE 0x0
+#define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
#else
/* Put BL31 below BL2 in the Trusted SRAM.*/
#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 002942e..8920f72 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -9,9 +9,11 @@
#include <assert_macros.S>
#include <xlat_tables_defs.h>
+#if !ERROR_DEPRECATED
.globl get_afflvl_shift
.globl mpidr_mask_lower_afflvls
.globl eret
+#endif /* ERROR_DEPRECATED */
.globl smc
.globl zero_normalmem
@@ -30,6 +32,7 @@
.globl enable_vfp
#endif
+#if !ERROR_DEPRECATED
func get_afflvl_shift
cmp x0, #3
cinc x0, x0, eq
@@ -52,7 +55,7 @@
func eret
eret
endfunc eret
-
+#endif /* ERROR_DEPRECATED */
func smc
smc #0
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 00dde31..0e5d447 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -60,11 +60,16 @@
$(LIB_DIR)/libwrappers.a: jmptbl.i $(WRAPPER_DIR)/jmpvar.o
@echo " AR $@"
- $(Q)./genwrappers.sh -b $(WRAPPER_DIR) -o $@ jmptbl.i
+ $(Q)./genwrappers.sh -b $(WRAPPER_DIR) -o $@ $(BUILD_DIR)/jmptbl.i
$(BUILD_DIR)/jmptbl.s: jmptbl.i
@echo " TBL $@"
- $(Q)./gentbl.sh -o $@ jmptbl.i
+ if [ -e "../../$(PLAT_DIR)/jmptbl.i" ] ; \
+ then \
+ $(Q)./gentbl.sh -o $@ -b $(BUILD_DIR) ../../$(PLAT_DIR)/jmptbl.i; \
+ else \
+ @echo "USE_ROMLIB=1 requires jump table list file: jmptbl.i in platform directory"; \
+ fi
clean:
@rm -f $(BUILD_DIR)/*
diff --git a/lib/romlib/gentbl.sh b/lib/romlib/gentbl.sh
index 0695f6e..e64cfe2 100755
--- a/lib/romlib/gentbl.sh
+++ b/lib/romlib/gentbl.sh
@@ -6,6 +6,7 @@
set -e
output=jmptbl.s
+build=.
for i
do
@@ -14,27 +15,45 @@
output=$2
shift 2
;;
+ -b)
+ build=$2
+ shift 2
+ ;;
--)
shift
break
;;
-*)
- echo usage: gentbl.sh [-o output] file ... >&2
+ echo usage: gentbl.sh [-o output] [-b dir] file ... >&2
exit 1
;;
esac
done
tmp=`mktemp`
-trap "rm -f $tmp" EXIT INT QUIT
-
+trap "rm -f $$.tmp" EXIT INT QUIT
rm -f $output
+# Pre-process include files
+awk '!/^$/ && !/[:blank:]*#.*/{
+if (NF == 2 && $1 == "include") {
+ while ((getline line < $2) > 0)
+ if (line !~ /^$/ && line !~ /[:blank:]*#.*/)
+ print line
+ close($2)
+} else
+ print
+}' "$@" |
+awk -v OFS="\t" '
+BEGIN{print "#index\tlib\tfunction\t[patch]"}
+{print NR-1, $0}' | tee $build/jmptbl.i |
awk -v OFS="\n" '
BEGIN {print "\t.text",
"\t.globl\tjmptbl",
"jmptbl:"}
{sub(/[:blank:]*#.*/,"")}
-!/^$/ {print "\tb\t" $3}' "$@" > $tmp
-
-mv $tmp $output
+!/^$/ {if ($3 == "reserved")
+ print "\t.word\t0x0"
+ else
+ print "\tb\t" $3}' > $$.tmp &&
+mv $$.tmp $output
diff --git a/lib/romlib/genwrappers.sh b/lib/romlib/genwrappers.sh
index 48ee5a4..746e4ba 100755
--- a/lib/romlib/genwrappers.sh
+++ b/lib/romlib/genwrappers.sh
@@ -31,7 +31,7 @@
done
awk '{sub(/[:blank:]*#.*/,"")}
-!/^$/ && !/\\tpatch$/ {print $1*4, $2, $3}' "$@" |
+!/^$/ && !/\\tpatch$/ !/\\treserved$/ {print $1*4, $2, $3}' "$@" |
while read idx lib sym
do
file=$build/${lib}_$sym
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
index 5eca5aa..a7280d0 100644
--- a/lib/romlib/jmptbl.i
+++ b/lib/romlib/jmptbl.i
@@ -4,37 +4,40 @@
# SPDX-License-Identifier: BSD-3-Clause
#
# Format:
-# index lib function [patch]
+# lib function [patch]
# Add "patch" at the end of the line to patch a function. For example:
-# 14 mbedtls mbedtls_memory_buffer_alloc_init patch
+# mbedtls mbedtls_memory_buffer_alloc_init patch
+# Holes can be introduced in the table by using a special keyword "reserved".
+# Example:
+# reserved reserved
+# The jump table will contain an invalid instruction instead of branch
-0 rom rom_lib_init
-1 fdt fdt_getprop_namelen
-2 fdt fdt_setprop_inplace
-3 fdt fdt_check_header
-4 fdt fdt_node_offset_by_compatible
-5 mbedtls mbedtls_asn1_get_alg
-6 mbedtls mbedtls_asn1_get_alg_null
-7 mbedtls mbedtls_asn1_get_bitstring_null
-8 mbedtls mbedtls_asn1_get_bool
-9 mbedtls mbedtls_asn1_get_int
-10 mbedtls mbedtls_asn1_get_tag
-11 mbedtls mbedtls_free
-12 mbedtls mbedtls_md
-13 mbedtls mbedtls_md_get_size
-14 mbedtls mbedtls_memory_buffer_alloc_init
-15 mbedtls mbedtls_oid_get_md_alg
-16 mbedtls mbedtls_oid_get_numeric_string
-17 mbedtls mbedtls_oid_get_pk_alg
-18 mbedtls mbedtls_oid_get_sig_alg
-19 mbedtls mbedtls_pk_free
-20 mbedtls mbedtls_pk_init
-21 mbedtls mbedtls_pk_parse_subpubkey
-22 mbedtls mbedtls_pk_verify_ext
-23 mbedtls mbedtls_platform_set_calloc_free
-24 mbedtls mbedtls_platform_set_snprintf
-25 mbedtls mbedtls_x509_get_rsassa_pss_params
-26 mbedtls mbedtls_x509_get_sig_alg
-27 mbedtls mbedtls_md_info_from_type
-28 c exit
-29 c atexit
\ No newline at end of file
+rom rom_lib_init
+fdt fdt_getprop_namelen
+fdt fdt_setprop_inplace
+fdt fdt_check_header
+fdt fdt_node_offset_by_compatible
+mbedtls mbedtls_asn1_get_alg
+mbedtls mbedtls_asn1_get_alg_null
+mbedtls mbedtls_asn1_get_bitstring_null
+mbedtls mbedtls_asn1_get_bool
+mbedtls mbedtls_asn1_get_int
+mbedtls mbedtls_asn1_get_tag
+mbedtls mbedtls_free
+mbedtls mbedtls_md
+mbedtls mbedtls_md_get_size
+mbedtls mbedtls_memory_buffer_alloc_init
+mbedtls mbedtls_oid_get_md_alg
+mbedtls mbedtls_oid_get_numeric_string
+mbedtls mbedtls_oid_get_pk_alg
+mbedtls mbedtls_oid_get_sig_alg
+mbedtls mbedtls_pk_free
+mbedtls mbedtls_pk_init
+mbedtls mbedtls_pk_parse_subpubkey
+mbedtls mbedtls_pk_verify_ext
+mbedtls mbedtls_platform_set_snprintf
+mbedtls mbedtls_x509_get_rsassa_pss_params
+mbedtls mbedtls_x509_get_sig_alg
+mbedtls mbedtls_md_info_from_type
+c exit
+c atexit
diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i
new file mode 100644
index 0000000..8d232d5
--- /dev/null
+++ b/plat/arm/board/fvp/jmptbl.i
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform specific romlib functions can be added or included here.
+# The index in the output file will be generated cumulatively in the same
+# order as it is given in this file.
+# Output file can be found at: $BUILD_DIR/jmptbl.i
+#
+# Format:
+# lib function [patch]
+# Example:
+# rom rom_lib_init
+# fdt fdt_getprop_namelen patch
+
+include ../../lib/romlib/jmptbl.i
diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i
new file mode 100644
index 0000000..8d232d5
--- /dev/null
+++ b/plat/arm/board/juno/jmptbl.i
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform specific romlib functions can be added or included here.
+# The index in the output file will be generated cumulatively in the same
+# order as it is given in this file.
+# Output file can be found at: $BUILD_DIR/jmptbl.i
+#
+# Format:
+# lib function [patch]
+# Example:
+# rom rom_lib_init
+# fdt fdt_getprop_namelen patch
+
+include ../../lib/romlib/jmptbl.i
diff --git a/plat/common/plat_log_common.c b/plat/common/plat_log_common.c
index 49e1c15..c757c6b 100644
--- a/plat/common/plat_log_common.c
+++ b/plat/common/plat_log_common.c
@@ -5,6 +5,7 @@
*/
#include <debug.h>
+#include <platform.h>
/* Allow platforms to override the log prefix string */
#pragma weak plat_log_get_prefix
diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h
index f2d358a..485eb38 100644
--- a/plat/hisilicon/hikey/include/platform_def.h
+++ b/plat/hisilicon/hikey/include/platform_def.h
@@ -41,7 +41,7 @@
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/* eMMC RPMB and eMMC User Data */
-#define MAX_IO_BLOCK_DEVICES 2
+#define MAX_IO_BLOCK_DEVICES U(2)
/* GIC related constants (no GICR in GIC-400) */
#define PLAT_ARM_GICD_BASE 0xF6801000
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 3717ff8..427a1e7 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -38,7 +38,7 @@
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
/* UFS RPMB and UFS User Data */
-#define MAX_IO_BLOCK_DEVICES 2
+#define MAX_IO_BLOCK_DEVICES U(2)
/*
diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h
index 6287a76..e39d944 100644
--- a/plat/hisilicon/poplar/include/platform_def.h
+++ b/plat/hisilicon/poplar/include/platform_def.h
@@ -40,7 +40,7 @@
/* IO framework user */
#define MAX_IO_DEVICES (4)
#define MAX_IO_HANDLES (4)
-#define MAX_IO_BLOCK_DEVICES (2)
+#define MAX_IO_BLOCK_DEVICES U(2)
/* Memory size options */
#define POPLAR_DRAM_SIZE_1G 0
diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h
index d0148f4..4ee6fd3 100644
--- a/plat/imx/imx7/warp7/include/platform_def.h
+++ b/plat/imx/imx7/warp7/include/platform_def.h
@@ -169,7 +169,7 @@
#define MAX_XLAT_TABLES 6
#define MAX_IO_DEVICES 2
#define MAX_IO_HANDLES 3
-#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_BLOCK_DEVICES 1U
/* UART defines */
#if PLAT_WARP7_UART == 1
diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h
index 3d71db2..6e9b98e 100644
--- a/plat/socionext/uniphier/include/platform_def.h
+++ b/plat/socionext/uniphier/include/platform_def.h
@@ -53,7 +53,7 @@
#define MAX_IO_HANDLES 2
#define MAX_IO_DEVICES 2
-#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_BLOCK_DEVICES U(1)
#define TSP_SEC_MEM_BASE (BL32_BASE)
#define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE))
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 545b140..8890e82 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -83,10 +83,6 @@
plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
plat/st/stm32mp1/plat_image_load.c
-# For memory footprint optimization, build with thumb and interwork support
-ASFLAGS += -mthumb -mthumb-interwork
-TF_CFLAGS += -mthumb -mthumb-interwork
-
# Macros and rules to build TF binary
STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed
STM32_DT_BASENAME := $(STM32_DTB_FILE_NAME:.dtb=)