fix(poplar): use sysctrl module to reset
Use sysctrl module rather than watchdog0 to reset the entire system.
Sysctrl is more reliable and requires less resources such as clocks and
resets. Doing this also allows non-secure OS to use the watchdog.
Change-Id: I30ac2780cc70055d81b35e55e35c9cb7f58b40cc
Signed-off-by: Yang Xiwen <forbidden405@foxmail.com>
diff --git a/plat/hisilicon/poplar/include/hi3798cv200.h b/plat/hisilicon/poplar/include/hi3798cv200.h
index e31f4b3..802dec5 100644
--- a/plat/hisilicon/poplar/include/hi3798cv200.h
+++ b/plat/hisilicon/poplar/include/hi3798cv200.h
@@ -38,7 +38,11 @@
/* SCTL */
#define REG_BASE_SCTL (0xF8000000)
+#define REG_SC_SYSRES (0x0004)
#define REG_SC_GEN12 (0x00B0)
+#define REG_SC_LOCKEN (0x020C)
+
+#define SC_UNLOCK_MAGIC (0x4F50454E)
/* CRG */
#define REG_BASE_CRG (0xF8A22000)
diff --git a/plat/hisilicon/poplar/plat_pm.c b/plat/hisilicon/poplar/plat_pm.c
index df842e8..77fc532 100644
--- a/plat/hisilicon/poplar/plat_pm.c
+++ b/plat/hisilicon/poplar/plat_pm.c
@@ -100,9 +100,10 @@
static void __dead2 poplar_system_reset(void)
{
- mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0xc00), 0x1ACCE551);
- mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x0), 0x00000100);
- mmio_write_32((uintptr_t)(HISI_WDG0_BASE + 0x8), 0x00000003);
+ /* Unlock Sysctrl critical registers */
+ mmio_write_32((uintptr_t)(REG_BASE_SCTL + REG_SC_LOCKEN), SC_UNLOCK_MAGIC);
+ /* Assert system reset */
+ mmio_write_32((uintptr_t)(REG_BASE_SCTL + REG_SC_SYSRES), 0xfee1dead);
wfi();
ERROR("Poplar System Reset: operation not handled.\n");