Merge "fix(nxp-tools): fix create_pbl buildroot build" into integration
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index 084539e..480edb9 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -190,7 +190,8 @@
ret = socfpga_vab_init(image_id);
if (ret < 0) {
ERROR("SOCFPGA VAB Authentication failed\n");
- wfi();
+ while (1)
+ wfi();
}
#endif
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk
index d534b2e..ee33402 100644
--- a/plat/intel/soc/agilex/platform.mk
+++ b/plat/intel/soc/agilex/platform.mk
@@ -1,7 +1,7 @@
#
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
-# Copyright (c) 2024, Altera Corporation. All rights reserved.
+# Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -115,5 +115,9 @@
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
USE_COHERENT_MEM := 1
+HANDLE_EA_EL3_FIRST_NS := 1
-HANDLE_EA_EL3_FIRST_NS := 1
\ No newline at end of file
+#To get the TF-A version via SMC calls
+DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR}
+DEFINES += -DVERSION_MINOR=${VERSION_MINOR}
+DEFINES += -DVERSION_PATCH=${VERSION_PATCH}
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 17d955a..20701a4 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -61,6 +61,10 @@
console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
PLAT_BAUDRATE, &console);
+ /* Enable TF-A BL31 logs when running from non-secure world also. */
+ console_set_scope(&console,
+ (CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH));
+
setup_smmu_stream_id();
/*
@@ -290,7 +294,7 @@
void bl31_plat_runtime_setup(void)
{
- console_switch_state(CONSOLE_FLAG_RUNTIME|CONSOLE_FLAG_BOOT);
+ /* Dummy override function. */
}
void bl31_plat_enable_mmu(uint32_t flags)
diff --git a/plat/intel/soc/agilex5/platform.mk b/plat/intel/soc/agilex5/platform.mk
index 58d4b2e..471b86f 100644
--- a/plat/intel/soc/agilex5/platform.mk
+++ b/plat/intel/soc/agilex5/platform.mk
@@ -142,4 +142,9 @@
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
-BL2_INV_DCACHE := 0
\ No newline at end of file
+BL2_INV_DCACHE := 0
+
+#To get the TF-A version via SMC calls
+DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR}
+DEFINES += -DVERSION_MINOR=${VERSION_MINOR}
+DEFINES += -DVERSION_PATCH=${VERSION_PATCH}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_ddr.c b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
index ef2ae57..0d60324 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_ddr.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_ddr.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -370,10 +370,10 @@
/* DDR size queried from the IOSSM controller */
hw_ddr_size = (phys_size_t)io96b_ctrl.overall_size * SZ_1G / SZ_8;
- /* TODO: Hard code 1GB as of now, and DDR start and end address */
- config_ddr_size = 0x40000000;
- ddr_info_set[0].start = 0x80000000;
- ddr_info_set[0].size = 0x40000000;
+ /* TODO: To update config_ddr_size by using FDT in the future. */
+ config_ddr_size = 0x80000000;
+ ddr_info_set[0].start = DRAM_BASE;
+ ddr_info_set[0].size = hw_ddr_size;
if (config_ddr_size != hw_ddr_size) {
WARN("DDR: DDR size configured is (%lld MiB)\n", config_ddr_size >> 20);
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 31474c4..fc667cc 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -146,6 +146,9 @@
#define INTEL_SIP_SMC_SEU_ERR_STATUS 0xC2000099
#define INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR 0xC200009A
+/* ATF build version */
+#define INTEL_SIP_SMC_ATF_BUILD_VER 0xC200009B
+
#define INTEL_SIP_SMC_FCS_SHA_MODE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_MASK 0xF
#define INTEL_SIP_SMC_FCS_DIGEST_SIZE_OFFSET 4U
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index d64ead7..f7b41fa 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1354,6 +1354,10 @@
status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
SMC_RET1(handle, status);
+ case INTEL_SIP_SMC_ATF_BUILD_VER:
+ SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR,
+ VERSION_MINOR, VERSION_PATCH);
+
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
diff --git a/plat/intel/soc/common/socfpga_vab.c b/plat/intel/soc/common/socfpga_vab.c
index 969abb3..3b7be5b 100644
--- a/plat/intel/soc/common/socfpga_vab.c
+++ b/plat/intel/soc/common/socfpga_vab.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -113,10 +113,10 @@
VERBOSE("mbox_data_addr = %lx mbox_data_sz = %d\n", mbox_data_addr, mbox_data_sz);
- memcpy_s(mbox_relocate_data_addr, mbox_data_sz * sizeof(uint32_t),
- (uint8_t *)mbox_data_addr, mbox_data_sz * sizeof(uint32_t));
+ memcpy_s(mbox_relocate_data_addr, (mbox_data_sz * sizeof(uint32_t)) / MBOX_WORD_BYTE,
+ (uint8_t *)mbox_data_addr, (mbox_data_sz * sizeof(uint32_t)) / MBOX_WORD_BYTE);
- *((unsigned int *)mbox_relocate_data_addr) = CCERT_CMD_TEST_PGM_MASK;
+ *((unsigned int *)mbox_relocate_data_addr) = 0;
do {
/* Invoke SMC call to ATF to send the VAB certificate to SDM */
diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk
index 4770f8d..4caafc5 100644
--- a/plat/intel/soc/n5x/platform.mk
+++ b/plat/intel/soc/n5x/platform.mk
@@ -1,6 +1,6 @@
#
# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
-# Copyright (c) 2024, Altera Corporation. All rights reserved.
+# Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -75,3 +75,8 @@
RESET_TO_BL2 := 1
BL2_INV_DCACHE := 0
USE_COHERENT_MEM := 1
+
+#To get the TF-A version via SMC calls
+DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR}
+DEFINES += -DVERSION_MINOR=${VERSION_MINOR}
+DEFINES += -DVERSION_PATCH=${VERSION_PATCH}
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 4cd7032..9946db8 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -1,7 +1,7 @@
#
# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
-# Copyright (c) 2024, Altera Corporation. All rights reserved.
+# Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -105,3 +105,8 @@
PROGRAMMABLE_RESET_ADDRESS := 0
RESET_TO_BL2 := 1
USE_COHERENT_MEM := 1
+
+#To get the TF-A version via SMC calls
+DEFINES += -DVERSION_MAJOR=${VERSION_MAJOR}
+DEFINES += -DVERSION_MINOR=${VERSION_MINOR}
+DEFINES += -DVERSION_PATCH=${VERSION_PATCH}
diff --git a/services/std_svc/rmmd/rmmd_main.c b/services/std_svc/rmmd/rmmd_main.c
index 10a2c42..4ddf484 100644
--- a/services/std_svc/rmmd/rmmd_main.c
+++ b/services/std_svc/rmmd/rmmd_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -502,12 +502,12 @@
case RMM_GTSI_UNDELEGATE:
ret = gpt_undelegate_pas(x1, PAGE_SIZE_4KB, SMC_FROM_REALM);
SMC_RET1(handle, gpt_to_gts_error(ret, smc_fid, x1));
- case RMM_ATTEST_GET_PLAT_TOKEN:
- ret = rmmd_attest_get_platform_token(x1, &x2, x3, &remaining_len);
- SMC_RET3(handle, ret, x2, remaining_len);
case RMM_ATTEST_GET_REALM_KEY:
ret = rmmd_attest_get_signing_key(x1, &x2, x3);
SMC_RET2(handle, ret, x2);
+ case RMM_ATTEST_GET_PLAT_TOKEN:
+ ret = rmmd_attest_get_platform_token(x1, &x2, x3, &remaining_len);
+ SMC_RET3(handle, ret, x2, remaining_len);
case RMM_EL3_FEATURES:
ret = rmm_el3_ifc_get_feat_register(x1, &x2);
SMC_RET2(handle, ret, x2);