diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h
index dac79aa..4b81547 100644
--- a/include/drivers/arm/tzc_common.h
+++ b/include/drivers/arm/tzc_common.h
@@ -73,10 +73,10 @@
 
 /* Macros for allowing Non-Secure access to a region based on NSAID */
 #define TZC_REGION_ACCESS_RD(nsaid)				\
-	((U(1) << (nsaid & TZC_REGION_ACCESS_ID_MASK)) <<	\
+	((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<	\
 	 TZC_REGION_ACCESS_RD_EN_SHIFT)
 #define TZC_REGION_ACCESS_WR(nsaid)				\
-	((U(1) << (nsaid & TZC_REGION_ACCESS_ID_MASK)) <<	\
+	((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<	\
 	 TZC_REGION_ACCESS_WR_EN_SHIFT)
 #define TZC_REGION_ACCESS_RDWR(nsaid)				\
 	(TZC_REGION_ACCESS_RD(nsaid) |				\
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index 4a1d43c..ed57fc9 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -48,9 +48,9 @@
 #define V2M_SYS_LED_EL_SHIFT		0x1
 #define V2M_SYS_LED_EC_SHIFT		0x3
 
-#define V2M_SYS_LED_SS_MASK		0x1
-#define V2M_SYS_LED_EL_MASK		0x3
-#define V2M_SYS_LED_EC_MASK		0x1f
+#define V2M_SYS_LED_SS_MASK		U(0x1)
+#define V2M_SYS_LED_EL_MASK		U(0x3)
+#define V2M_SYS_LED_EC_MASK		U(0x1f)
 
 /* V2M sysid register bits */
 #define V2M_SYS_ID_REV_SHIFT		28
@@ -59,28 +59,28 @@
 #define V2M_SYS_ID_ARCH_SHIFT		8
 #define V2M_SYS_ID_FPGA_SHIFT		0
 
-#define V2M_SYS_ID_REV_MASK		0xf
-#define V2M_SYS_ID_HBI_MASK		0xfff
-#define V2M_SYS_ID_BLD_MASK		0xf
-#define V2M_SYS_ID_ARCH_MASK		0xf
-#define V2M_SYS_ID_FPGA_MASK		0xff
+#define V2M_SYS_ID_REV_MASK		U(0xf)
+#define V2M_SYS_ID_HBI_MASK		U(0xfff)
+#define V2M_SYS_ID_BLD_MASK		U(0xf)
+#define V2M_SYS_ID_ARCH_MASK		U(0xf)
+#define V2M_SYS_ID_FPGA_MASK		U(0xff)
 
 #define V2M_SYS_ID_BLD_LENGTH		4
 
 
 /* NOR Flash */
-#define V2M_FLASH0_BASE			0x08000000
-#define V2M_FLASH0_SIZE			0x04000000
-#define V2M_FLASH_BLOCK_SIZE		0x00040000	/* 256 KB */
+#define V2M_FLASH0_BASE			UL(0x08000000)
+#define V2M_FLASH0_SIZE			UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE		UL(0x00040000)	/* 256 KB */
 
-#define V2M_IOFPGA_BASE			0x1c000000
-#define V2M_IOFPGA_SIZE			0x03000000
+#define V2M_IOFPGA_BASE			UL(0x1c000000)
+#define V2M_IOFPGA_SIZE			UL(0x03000000)
 
 /* PL011 UART related constants */
-#define V2M_IOFPGA_UART0_BASE		0x1c090000
-#define V2M_IOFPGA_UART1_BASE		0x1c0a0000
-#define V2M_IOFPGA_UART2_BASE		0x1c0b0000
-#define V2M_IOFPGA_UART3_BASE		0x1c0c0000
+#define V2M_IOFPGA_UART0_BASE		UL(0x1c090000)
+#define V2M_IOFPGA_UART1_BASE		UL(0x1c0a0000)
+#define V2M_IOFPGA_UART2_BASE		UL(0x1c0b0000)
+#define V2M_IOFPGA_UART3_BASE		UL(0x1c0c0000)
 
 #define V2M_IOFPGA_UART0_CLK_IN_HZ	24000000
 #define V2M_IOFPGA_UART1_CLK_IN_HZ	24000000
@@ -88,15 +88,15 @@
 #define V2M_IOFPGA_UART3_CLK_IN_HZ	24000000
 
 /* SP804 timer related constants */
-#define V2M_SP804_TIMER0_BASE		0x1C110000
-#define V2M_SP804_TIMER1_BASE		0x1C120000
+#define V2M_SP804_TIMER0_BASE		UL(0x1C110000)
+#define V2M_SP804_TIMER1_BASE		UL(0x1C120000)
 
 /* SP810 controller */
-#define V2M_SP810_BASE			0x1c020000
-#define V2M_SP810_CTRL_TIM0_SEL		(1 << 15)
-#define V2M_SP810_CTRL_TIM1_SEL		(1 << 17)
-#define V2M_SP810_CTRL_TIM2_SEL		(1 << 19)
-#define V2M_SP810_CTRL_TIM3_SEL		(1 << 21)
+#define V2M_SP810_BASE			UL(0x1c020000)
+#define V2M_SP810_CTRL_TIM0_SEL		BIT_32(15)
+#define V2M_SP810_CTRL_TIM1_SEL		BIT_32(17)
+#define V2M_SP810_CTRL_TIM2_SEL		BIT_32(19)
+#define V2M_SP810_CTRL_TIM3_SEL		BIT_32(21)
 
 /*
  * The flash can be mapped either as read-only or read-write.
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 0f5b57f..088d59d 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -21,7 +21,7 @@
  *****************************************************************************/
 
 /* Special value used to verify platform parameters from BL2 to BL31 */
-#define ARM_BL31_PLAT_PARAM_VAL		0x0f1e2d3c4b5a6978ULL
+#define ARM_BL31_PLAT_PARAM_VAL		ULL(0x0f1e2d3c4b5a6978)
 
 #define ARM_SYSTEM_COUNT		1
 
@@ -350,8 +350,8 @@
  * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
  * and limit. Leave enough space of BL2 meminfo.
  */
-#define ARM_TB_FW_CONFIG_BASE		ARM_BL_RAM_BASE + sizeof(meminfo_t)
-#define ARM_TB_FW_CONFIG_LIMIT		ARM_BL_RAM_BASE + PAGE_SIZE
+#define ARM_TB_FW_CONFIG_BASE		(ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_TB_FW_CONFIG_LIMIT		(ARM_BL_RAM_BASE + PAGE_SIZE)
 
 /*******************************************************************************
  * BL1 specific defines.
@@ -482,7 +482,7 @@
 #  define TSP_SEC_MEM_SIZE		PLAT_ARM_TRUSTED_DRAM_SIZE
 #  define BL32_BASE			PLAT_ARM_TRUSTED_DRAM_BASE
 #  define BL32_LIMIT			(PLAT_ARM_TRUSTED_DRAM_BASE	\
-						+ (1 << 21))
+						+ (UL(1) << 21))
 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
 #  define TSP_SEC_MEM_BASE		ARM_AP_TZC_DRAM1_BASE
 #  define TSP_SEC_MEM_SIZE		ARM_AP_TZC_DRAM1_SIZE
@@ -511,7 +511,7 @@
 #define BL2U_LIMIT			BL2_LIMIT
 
 #define NS_BL2U_BASE			ARM_NS_DRAM1_BASE
-#define NS_BL1U_BASE			(PLAT_ARM_NVM_BASE + 0x03EB8000)
+#define NS_BL1U_BASE			(PLAT_ARM_NVM_BASE + UL(0x03EB8000))
 
 /*
  * ID of the secure physical generic timer interrupt used by the TSP.
diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h
index eb6f77f..a8ed9d3 100644
--- a/plat/arm/board/fvp/fvp_def.h
+++ b/plat/arm/board/fvp/fvp_def.h
@@ -31,70 +31,70 @@
  * FVP memory map related constants
  ******************************************************************************/
 
-#define FLASH1_BASE			0x0c000000
-#define FLASH1_SIZE			0x04000000
+#define FLASH1_BASE			UL(0x0c000000)
+#define FLASH1_SIZE			UL(0x04000000)
 
-#define PSRAM_BASE			0x14000000
-#define PSRAM_SIZE			0x04000000
+#define PSRAM_BASE			UL(0x14000000)
+#define PSRAM_SIZE			UL(0x04000000)
 
-#define VRAM_BASE			0x18000000
-#define VRAM_SIZE			0x02000000
+#define VRAM_BASE			UL(0x18000000)
+#define VRAM_SIZE			UL(0x02000000)
 
 /* Aggregate of all devices in the first GB */
-#define DEVICE0_BASE			0x20000000
-#define DEVICE0_SIZE			0x0c200000
+#define DEVICE0_BASE			UL(0x20000000)
+#define DEVICE0_SIZE			UL(0x0c200000)
 
 /*
  *  In case of FVP models with CCN, the CCN register space overlaps into
  *  the NSRAM area.
  */
 #if FVP_INTERCONNECT_DRIVER == FVP_CCN
-#define DEVICE1_BASE			0x2e000000
-#define DEVICE1_SIZE			0x1A00000
+#define DEVICE1_BASE			UL(0x2e000000)
+#define DEVICE1_SIZE			UL(0x1A00000)
 #else
-#define DEVICE1_BASE			0x2f000000
-#define DEVICE1_SIZE			0x200000
-#define NSRAM_BASE			0x2e000000
-#define NSRAM_SIZE			0x10000
+#define DEVICE1_BASE			UL(0x2f000000)
+#define DEVICE1_SIZE			UL(0x200000)
+#define NSRAM_BASE			UL(0x2e000000)
+#define NSRAM_SIZE			UL(0x10000)
 #endif
 /* Devices in the second GB */
-#define DEVICE2_BASE			0x7fe00000
-#define DEVICE2_SIZE			0x00200000
+#define DEVICE2_BASE			UL(0x7fe00000)
+#define DEVICE2_SIZE			UL(0x00200000)
 
-#define PCIE_EXP_BASE			0x40000000
-#define TZRNG_BASE			0x7fe60000
+#define PCIE_EXP_BASE			UL(0x40000000)
+#define TZRNG_BASE			UL(0x7fe60000)
 
 /* Non-volatile counters */
-#define TRUSTED_NVCTR_BASE		0x7fe70000
-#define TFW_NVCTR_BASE			(TRUSTED_NVCTR_BASE + 0x0000)
-#define TFW_NVCTR_SIZE			4
-#define NTFW_CTR_BASE			(TRUSTED_NVCTR_BASE + 0x0004)
-#define NTFW_CTR_SIZE			4
+#define TRUSTED_NVCTR_BASE		UL(0x7fe70000)
+#define TFW_NVCTR_BASE			(TRUSTED_NVCTR_BASE + UL(0x0000))
+#define TFW_NVCTR_SIZE			UL(4)
+#define NTFW_CTR_BASE			(TRUSTED_NVCTR_BASE + UL(0x0004))
+#define NTFW_CTR_SIZE			UL(4)
 
 /* Keys */
-#define SOC_KEYS_BASE			0x7fe80000
-#define TZ_PUB_KEY_HASH_BASE		(SOC_KEYS_BASE + 0x0000)
-#define TZ_PUB_KEY_HASH_SIZE		32
-#define HU_KEY_BASE			(SOC_KEYS_BASE + 0x0020)
-#define HU_KEY_SIZE			16
-#define END_KEY_BASE			(SOC_KEYS_BASE + 0x0044)
-#define END_KEY_SIZE			32
+#define SOC_KEYS_BASE			UL(0x7fe80000)
+#define TZ_PUB_KEY_HASH_BASE		(SOC_KEYS_BASE + UL(0x0000))
+#define TZ_PUB_KEY_HASH_SIZE		UL(32)
+#define HU_KEY_BASE			(SOC_KEYS_BASE + UL(0x0020))
+#define HU_KEY_SIZE			UL(16)
+#define END_KEY_BASE			(SOC_KEYS_BASE + UL(0x0044))
+#define END_KEY_SIZE			UL(32)
 
 /* Constants to distinguish FVP type */
-#define HBI_BASE_FVP			0x020
-#define REV_BASE_FVP_V0			0x0
-#define REV_BASE_FVP_REVC		0x2
+#define HBI_BASE_FVP			U(0x020)
+#define REV_BASE_FVP_V0			U(0x0)
+#define REV_BASE_FVP_REVC		U(0x2)
 
-#define HBI_FOUNDATION_FVP		0x010
-#define REV_FOUNDATION_FVP_V2_0		0x0
-#define REV_FOUNDATION_FVP_V2_1		0x1
-#define REV_FOUNDATION_FVP_v9_1		0x2
-#define REV_FOUNDATION_FVP_v9_6		0x3
+#define HBI_FOUNDATION_FVP		U(0x010)
+#define REV_FOUNDATION_FVP_V2_0		U(0x0)
+#define REV_FOUNDATION_FVP_V2_1		U(0x1)
+#define REV_FOUNDATION_FVP_v9_1		U(0x2)
+#define REV_FOUNDATION_FVP_v9_6		U(0x3)
 
-#define BLD_GIC_VE_MMAP			0x0
-#define BLD_GIC_A53A57_MMAP		0x1
+#define BLD_GIC_VE_MMAP			U(0x0)
+#define BLD_GIC_A53A57_MMAP		U(0x1)
 
-#define ARCH_MODEL			0x1
+#define ARCH_MODEL			U(0x1)
 
 /* FVP Power controller base address*/
 #define PWRC_BASE			UL(0x1c100000)
@@ -104,26 +104,26 @@
 #define SP804_TIMER_CLKDIV		35
 
 /* SP810 controller. FVP specific flags */
-#define FVP_SP810_CTRL_TIM0_OV		(1 << 16)
-#define FVP_SP810_CTRL_TIM1_OV		(1 << 18)
-#define FVP_SP810_CTRL_TIM2_OV		(1 << 20)
-#define FVP_SP810_CTRL_TIM3_OV		(1 << 22)
+#define FVP_SP810_CTRL_TIM0_OV		BIT_32(16)
+#define FVP_SP810_CTRL_TIM1_OV		BIT_32(18)
+#define FVP_SP810_CTRL_TIM2_OV		BIT_32(20)
+#define FVP_SP810_CTRL_TIM3_OV		BIT_32(22)
 
 /*******************************************************************************
  * GIC-400 & interrupt handling related constants
  ******************************************************************************/
 /* VE compatible GIC memory map */
-#define VE_GICD_BASE			0x2c001000
-#define VE_GICC_BASE			0x2c002000
-#define VE_GICH_BASE			0x2c004000
-#define VE_GICV_BASE			0x2c006000
+#define VE_GICD_BASE			UL(0x2c001000)
+#define VE_GICC_BASE			UL(0x2c002000)
+#define VE_GICH_BASE			UL(0x2c004000)
+#define VE_GICV_BASE			UL(0x2c006000)
 
 /* Base FVP compatible GIC memory map */
-#define BASE_GICD_BASE			0x2f000000
-#define BASE_GICR_BASE			0x2f100000
-#define BASE_GICC_BASE			0x2c000000
-#define BASE_GICH_BASE			0x2c010000
-#define BASE_GICV_BASE			0x2c02f000
+#define BASE_GICD_BASE			UL(0x2f000000)
+#define BASE_GICR_BASE			UL(0x2f100000)
+#define BASE_GICC_BASE			UL(0x2c000000)
+#define BASE_GICH_BASE			UL(0x2c010000)
+#define BASE_GICV_BASE			UL(0x2c02f000)
 
 #define FVP_IRQ_TZ_WDOG			56
 #define FVP_IRQ_SEC_SYS_TIMER		57
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index ed1a302..44ab1b3 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 /* Enable the dynamic translation tables library. */
 #ifdef AARCH32
@@ -44,26 +44,26 @@
  */
 #define PLAT_ARM_CLUSTER_COUNT		FVP_CLUSTER_COUNT
 
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	UL(0x00040000)	/* 256 KB */
 
-#define PLAT_ARM_TRUSTED_ROM_BASE	0x00000000
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x04000000	/* 64 MB */
+#define PLAT_ARM_TRUSTED_ROM_BASE	UL(0x00000000)
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x04000000)	/* 64 MB */
 
-#define PLAT_ARM_TRUSTED_DRAM_BASE	0x06000000
-#define PLAT_ARM_TRUSTED_DRAM_SIZE	0x02000000	/* 32 MB */
+#define PLAT_ARM_TRUSTED_DRAM_BASE	UL(0x06000000)
+#define PLAT_ARM_TRUSTED_DRAM_SIZE	UL(0x02000000)	/* 32 MB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
 /* No SCP in FVP */
-#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	ULL(0x0)
+#define PLAT_ARM_SCP_TZC_DRAM1_SIZE	UL(0x0)
 
-#define PLAT_ARM_DRAM2_SIZE		ULL(0x80000000)
+#define PLAT_ARM_DRAM2_SIZE		UL(0x80000000)
 
 /*
  * Load address of BL33 for this platform port
  */
-#define PLAT_ARM_NS_IMAGE_OFFSET	(ARM_DRAM1_BASE + U(0x8000000))
+#define PLAT_ARM_NS_IMAGE_OFFSET	(ARM_DRAM1_BASE + UL(0x8000000))
 
 /*
  * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
@@ -94,18 +94,18 @@
  * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
  * plus a little space for growth.
  */
-#define PLAT_ARM_MAX_BL1_RW_SIZE	0xB000
+#define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xB000)
 
 /*
  * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
  */
 
 #if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0xe000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0xe000)
 #else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE	UL(0)
 #endif
 
 /*
@@ -113,9 +113,9 @@
  * little space for growth.
  */
 #if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1D000)
 #else
-# define PLAT_ARM_MAX_BL2_SIZE		0x11000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x11000)
 #endif
 
 /*
@@ -123,7 +123,7 @@
  * calculated using the current BL31 PROGBITS debug size plus the sizes of
  * BL2 and BL1-RW
  */
-#define PLAT_ARM_MAX_BL31_SIZE		0x3B000
+#define PLAT_ARM_MAX_BL31_SIZE		UL(0x3B000)
 
 #ifdef AARCH32
 /*
@@ -131,7 +131,7 @@
  * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
  * BL2 and BL1-RW
  */
-# define PLAT_ARM_MAX_BL32_SIZE		0x3B000
+# define PLAT_ARM_MAX_BL32_SIZE		UL(0x3B000)
 #endif
 
 /*
@@ -139,28 +139,28 @@
  */
 #if defined(IMAGE_BL1)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x440
+#  define PLATFORM_STACK_SIZE		UL(0x440)
 # endif
 #elif defined(IMAGE_BL2)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE		UL(0x400)
 #elif defined(IMAGE_BL31)
 # if ENABLE_SPM
-#  define PLATFORM_STACK_SIZE 0x500
+#  define PLATFORM_STACK_SIZE		UL(0x500)
 # elif PLAT_XLAT_TABLES_DYNAMIC
-#  define PLATFORM_STACK_SIZE 0x800
+#  define PLATFORM_STACK_SIZE		UL(0x800)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE		UL(0x440)
 #endif
 
 #define MAX_IO_DEVICES			3
@@ -191,20 +191,20 @@
 #define PLAT_ARM_TSP_UART_BASE		V2M_IOFPGA_UART2_BASE
 #define PLAT_ARM_TSP_UART_CLK_IN_HZ	V2M_IOFPGA_UART2_CLK_IN_HZ
 
-#define PLAT_FVP_SMMUV3_BASE		0x2b400000
+#define PLAT_FVP_SMMUV3_BASE		UL(0x2b400000)
 
 /* CCI related constants */
-#define PLAT_FVP_CCI400_BASE		0x2c090000
+#define PLAT_FVP_CCI400_BASE		UL(0x2c090000)
 #define PLAT_FVP_CCI400_CLUS0_SL_PORT	3
 #define PLAT_FVP_CCI400_CLUS1_SL_PORT	4
 
 /* CCI-500/CCI-550 on Base platform */
-#define PLAT_FVP_CCI5XX_BASE		0x2a000000
+#define PLAT_FVP_CCI5XX_BASE		UL(0x2a000000)
 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT	5
 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT	6
 
 /* CCN related constants. Only CCN 502 is currently supported */
-#define PLAT_ARM_CCN_BASE		0x2e000000
+#define PLAT_ARM_CCN_BASE		UL(0x2e000000)
 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP	1, 5, 7, 11
 
 /* System timer related constants */
@@ -229,7 +229,7 @@
  * Give access to the CPUs and Virtio. Some devices
  * would normally use the default ID so allow that too.
  */
-#define PLAT_ARM_TZC_BASE		0x2a4a0000
+#define PLAT_ARM_TZC_BASE		UL(0x2a4a0000)
 #define PLAT_ARM_TZC_FILTERS		TZC_400_REGION_ATTR_FILTER_BIT(0)
 
 #define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
@@ -268,4 +268,4 @@
 #define PLAT_ARM_SP_IMAGE_STACK_BASE	(ARM_SP_IMAGE_NS_BUF_BASE +	\
 					 ARM_SP_IMAGE_NS_BUF_SIZE)
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index d4a77f0..89e28ef 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __PLATFORM_DEF_H__
-#define __PLATFORM_DEF_H__
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
 
 /* Enable the dynamic translation tables library. */
 #ifdef AARCH32
@@ -41,7 +41,7 @@
 					JUNO_CLUSTER1_CORE_COUNT)
 
 /* Cryptocell HW Base address */
-#define PLAT_CRYPTOCELL_BASE		0x60050000
+#define PLAT_CRYPTOCELL_BASE		UL(0x60050000)
 
 /*
  * Other platform porting definitions are provided by included headers
@@ -52,13 +52,13 @@
  */
 #define PLAT_ARM_CLUSTER_COUNT		JUNO_CLUSTER_COUNT
 
-#define PLAT_ARM_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE	UL(0x00040000)	/* 256 KB */
 
 /* Use the bypass address */
 #define PLAT_ARM_TRUSTED_ROM_BASE	V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET
 
-#define NSRAM_BASE			0x2e000000
-#define NSRAM_SIZE			0x00008000	/* 32KB */
+#define NSRAM_BASE			UL(0x2e000000)
+#define NSRAM_SIZE			UL(0x00008000)	/* 32KB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
 #define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
@@ -71,9 +71,9 @@
 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE	0
 
 #if TRUSTED_BOARD_BOOT
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00020000
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x00020000)
 #else
-#define PLAT_ARM_TRUSTED_ROM_SIZE	0x00010000
+#define PLAT_ARM_TRUSTED_ROM_SIZE	UL(0x00010000)
 #endif /* TRUSTED_BOARD_BOOT */
 
 /*
@@ -115,18 +115,18 @@
  * plus a little space for growth.
  */
 #if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL1_RW_SIZE	0xB000
+# define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0xB000)
 #else
-# define PLAT_ARM_MAX_BL1_RW_SIZE	0x6000
+# define PLAT_ARM_MAX_BL1_RW_SIZE	UL(0x6000)
 #endif
 
 /*
  * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
  */
 #if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0x1000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0x1000)
 #else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	0
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE	UL(0)
 #endif
 
 /*
@@ -135,14 +135,14 @@
  */
 #if TRUSTED_BOARD_BOOT
 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE		0x1F000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1F000)
 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE		0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1D000)
 #else
-# define PLAT_ARM_MAX_BL2_SIZE		0x1C000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0x1C000)
 #endif
 #else
-# define PLAT_ARM_MAX_BL2_SIZE		0xF000
+# define PLAT_ARM_MAX_BL2_SIZE		UL(0xF000)
 #endif
 
 /*
@@ -151,7 +151,7 @@
  * BL2 and BL1-RW.  SCP_BL2 image is loaded into the space BL31 -> BL2_BASE.
  * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
  */
-#define PLAT_ARM_MAX_BL31_SIZE		0x3E000
+#define PLAT_ARM_MAX_BL31_SIZE		UL(0x3E000)
 
 #if JUNO_AARCH32_EL3_RUNTIME
 /*
@@ -160,7 +160,7 @@
  * BL2 and BL1-RW.  SCP_BL2 image is loaded into the space BL32 -> BL2_BASE.
  * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE.
  */
-#define PLAT_ARM_MAX_BL32_SIZE		0x3E000
+#define PLAT_ARM_MAX_BL32_SIZE		UL(0x3E000)
 #endif
 
 /*
@@ -168,26 +168,26 @@
  */
 #if defined(IMAGE_BL1)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x440
+#  define PLATFORM_STACK_SIZE		UL(0x440)
 # endif
 #elif defined(IMAGE_BL2)
 # if TRUSTED_BOARD_BOOT
-#  define PLATFORM_STACK_SIZE 0x1000
+#  define PLATFORM_STACK_SIZE		UL(0x1000)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
+# define PLATFORM_STACK_SIZE		UL(0x400)
 #elif defined(IMAGE_BL31)
 # if PLAT_XLAT_TABLES_DYNAMIC
-#  define PLATFORM_STACK_SIZE 0x800
+#  define PLATFORM_STACK_SIZE		UL(0x800)
 # else
-#  define PLATFORM_STACK_SIZE 0x400
+#  define PLATFORM_STACK_SIZE		UL(0x400)
 # endif
 #elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
+# define PLATFORM_STACK_SIZE		UL(0x440)
 #endif
 
 /*
@@ -197,7 +197,7 @@
 #define PLAT_LOG_LEVEL_ASSERT		40
 
 /* CCI related constants */
-#define PLAT_ARM_CCI_BASE		0x2c090000
+#define PLAT_ARM_CCI_BASE		UL(0x2c090000)
 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX	4
 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX	3
 
@@ -205,7 +205,7 @@
 #define PLAT_ARM_NSTIMER_FRAME_ID		1
 
 /* TZC related constants */
-#define PLAT_ARM_TZC_BASE		0x2a4a0000
+#define PLAT_ARM_TZC_BASE		UL(0x2a4a0000)
 #define PLAT_ARM_TZC_NS_DEV_ACCESS	(				\
 		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400)	|	\
 		TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE)	|	\
@@ -223,13 +223,13 @@
  */
 
 /* GIC related constants (no GICR in GIC-400) */
-#define PLAT_ARM_GICD_BASE		0x2c010000
-#define PLAT_ARM_GICC_BASE		0x2c02f000
-#define PLAT_ARM_GICH_BASE		0x2c04f000
-#define PLAT_ARM_GICV_BASE		0x2c06f000
+#define PLAT_ARM_GICD_BASE		UL(0x2c010000)
+#define PLAT_ARM_GICC_BASE		UL(0x2c02f000)
+#define PLAT_ARM_GICH_BASE		UL(0x2c04f000)
+#define PLAT_ARM_GICV_BASE		UL(0x2c06f000)
 
 /* MHU related constants */
-#define PLAT_CSS_MHU_BASE		0x2b1f0000
+#define PLAT_CSS_MHU_BASE		UL(0x2b1f0000)
 
 /*
  * Base address of the first memory region used for communication between AP
@@ -243,7 +243,7 @@
  * 32-bit word on all CSS platforms. On Juno, part of this configuration is
  * which CPU is the primary, according to the shift and mask definitions below.
  */
-#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + 0x80)
+#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE	(ARM_TRUSTED_SRAM_BASE + UL(0x80))
 #define PLAT_CSS_PRIMARY_CPU_SHIFT		8
 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH		4
 #endif
@@ -252,13 +252,13 @@
  * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
  * SCP_BL2 size plus a little space for growth.
  */
-#define PLAT_CSS_MAX_SCP_BL2_SIZE	0x14000
+#define PLAT_CSS_MAX_SCP_BL2_SIZE	UL(0x14000)
 
 /*
  * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
  * SCP_BL2U size plus a little space for growth.
  */
-#define PLAT_CSS_MAX_SCP_BL2U_SIZE	0x14000
+#define PLAT_CSS_MAX_SCP_BL2U_SIZE	UL(0x14000)
 
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 	CSS_G1S_IRQ_PROPS(grp), \
@@ -287,9 +287,9 @@
  */
 
 /* CSS SoC NIC-400 Global Programmers View (GPV) */
-#define PLAT_SOC_CSS_NIC400_BASE	0x2a000000
+#define PLAT_SOC_CSS_NIC400_BASE	UL(0x2a000000)
 
 #define PLAT_ARM_PRIVATE_SDEI_EVENTS	ARM_SDEI_PRIVATE_EVENTS
 #define PLAT_ARM_SHARED_SDEI_EVENTS	ARM_SDEI_SHARED_EVENTS
 
-#endif /* __PLATFORM_DEF_H__ */
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/juno/juno_def.h b/plat/arm/board/juno/juno_def.h
index 95f2b39..5301886 100644
--- a/plat/arm/board/juno/juno_def.h
+++ b/plat/arm/board/juno/juno_def.h
@@ -14,20 +14,20 @@
  ******************************************************************************/
 
 /* Board revisions */
-#define REV_JUNO_R0			0x1	/* Rev B */
-#define REV_JUNO_R1			0x2	/* Rev C */
-#define REV_JUNO_R2			0x3	/* Rev D */
+#define REV_JUNO_R0			U(0x1)	/* Rev B */
+#define REV_JUNO_R1			U(0x2)	/* Rev C */
+#define REV_JUNO_R2			U(0x3)	/* Rev D */
 
 /* Bypass offset from start of NOR flash */
-#define BL1_ROM_BYPASS_OFFSET		0x03EC0000
+#define BL1_ROM_BYPASS_OFFSET		UL(0x03EC0000)
 
-#define EMMC_BASE			0x0c000000
-#define EMMC_SIZE			0x04000000
+#define EMMC_BASE			UL(0x0c000000)
+#define EMMC_SIZE			UL(0x04000000)
 
-#define PSRAM_BASE			0x14000000
-#define PSRAM_SIZE			0x02000000
+#define PSRAM_BASE			UL(0x14000000)
+#define PSRAM_SIZE			UL(0x02000000)
 
-#define JUNO_SSC_VER_PART_NUM		0x030
+#define JUNO_SSC_VER_PART_NUM		U(0x030)
 
 /*******************************************************************************
  * Juno topology related constants
@@ -54,19 +54,19 @@
 /*******************************************************************************
  * TRNG related constants
  ******************************************************************************/
-#define TRNG_BASE	0x7FE60000ULL
+#define TRNG_BASE	UL(0x7FE60000)
 #define TRNG_NOUTPUTS	4
-#define TRNG_STATUS	0x10
-#define TRNG_INTMASK	0x14
-#define TRNG_CONFIG	0x18
-#define TRNG_CONTROL	0x1C
+#define TRNG_STATUS	UL(0x10)
+#define TRNG_INTMASK	UL(0x14)
+#define TRNG_CONFIG	UL(0x18)
+#define TRNG_CONTROL	UL(0x1C)
 #define TRNG_NBYTES	16	/* Number of bytes generated per round. */
 
 /*******************************************************************************
  * MMU-401 related constants
  ******************************************************************************/
-#define MMU401_SSD_OFFSET		0x4000
-#define MMU401_DMA330_BASE		0x7fb00000
+#define MMU401_SSD_OFFSET		UL(0x4000)
+#define MMU401_DMA330_BASE		UL(0x7fb00000)
 
 /*******************************************************************************
  * Interrupt handling constants