plat/arm: Fix types of constants in headers
Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/include/drivers/arm/tzc_common.h b/include/drivers/arm/tzc_common.h
index dac79aa..4b81547 100644
--- a/include/drivers/arm/tzc_common.h
+++ b/include/drivers/arm/tzc_common.h
@@ -73,10 +73,10 @@
/* Macros for allowing Non-Secure access to a region based on NSAID */
#define TZC_REGION_ACCESS_RD(nsaid) \
- ((U(1) << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
TZC_REGION_ACCESS_RD_EN_SHIFT)
#define TZC_REGION_ACCESS_WR(nsaid) \
- ((U(1) << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \
+ ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \
TZC_REGION_ACCESS_WR_EN_SHIFT)
#define TZC_REGION_ACCESS_RDWR(nsaid) \
(TZC_REGION_ACCESS_RD(nsaid) | \
diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index 4a1d43c..ed57fc9 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -48,9 +48,9 @@
#define V2M_SYS_LED_EL_SHIFT 0x1
#define V2M_SYS_LED_EC_SHIFT 0x3
-#define V2M_SYS_LED_SS_MASK 0x1
-#define V2M_SYS_LED_EL_MASK 0x3
-#define V2M_SYS_LED_EC_MASK 0x1f
+#define V2M_SYS_LED_SS_MASK U(0x1)
+#define V2M_SYS_LED_EL_MASK U(0x3)
+#define V2M_SYS_LED_EC_MASK U(0x1f)
/* V2M sysid register bits */
#define V2M_SYS_ID_REV_SHIFT 28
@@ -59,28 +59,28 @@
#define V2M_SYS_ID_ARCH_SHIFT 8
#define V2M_SYS_ID_FPGA_SHIFT 0
-#define V2M_SYS_ID_REV_MASK 0xf
-#define V2M_SYS_ID_HBI_MASK 0xfff
-#define V2M_SYS_ID_BLD_MASK 0xf
-#define V2M_SYS_ID_ARCH_MASK 0xf
-#define V2M_SYS_ID_FPGA_MASK 0xff
+#define V2M_SYS_ID_REV_MASK U(0xf)
+#define V2M_SYS_ID_HBI_MASK U(0xfff)
+#define V2M_SYS_ID_BLD_MASK U(0xf)
+#define V2M_SYS_ID_ARCH_MASK U(0xf)
+#define V2M_SYS_ID_FPGA_MASK U(0xff)
#define V2M_SYS_ID_BLD_LENGTH 4
/* NOR Flash */
-#define V2M_FLASH0_BASE 0x08000000
-#define V2M_FLASH0_SIZE 0x04000000
-#define V2M_FLASH_BLOCK_SIZE 0x00040000 /* 256 KB */
+#define V2M_FLASH0_BASE UL(0x08000000)
+#define V2M_FLASH0_SIZE UL(0x04000000)
+#define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */
-#define V2M_IOFPGA_BASE 0x1c000000
-#define V2M_IOFPGA_SIZE 0x03000000
+#define V2M_IOFPGA_BASE UL(0x1c000000)
+#define V2M_IOFPGA_SIZE UL(0x03000000)
/* PL011 UART related constants */
-#define V2M_IOFPGA_UART0_BASE 0x1c090000
-#define V2M_IOFPGA_UART1_BASE 0x1c0a0000
-#define V2M_IOFPGA_UART2_BASE 0x1c0b0000
-#define V2M_IOFPGA_UART3_BASE 0x1c0c0000
+#define V2M_IOFPGA_UART0_BASE UL(0x1c090000)
+#define V2M_IOFPGA_UART1_BASE UL(0x1c0a0000)
+#define V2M_IOFPGA_UART2_BASE UL(0x1c0b0000)
+#define V2M_IOFPGA_UART3_BASE UL(0x1c0c0000)
#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000
#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000
@@ -88,15 +88,15 @@
#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000
/* SP804 timer related constants */
-#define V2M_SP804_TIMER0_BASE 0x1C110000
-#define V2M_SP804_TIMER1_BASE 0x1C120000
+#define V2M_SP804_TIMER0_BASE UL(0x1C110000)
+#define V2M_SP804_TIMER1_BASE UL(0x1C120000)
/* SP810 controller */
-#define V2M_SP810_BASE 0x1c020000
-#define V2M_SP810_CTRL_TIM0_SEL (1 << 15)
-#define V2M_SP810_CTRL_TIM1_SEL (1 << 17)
-#define V2M_SP810_CTRL_TIM2_SEL (1 << 19)
-#define V2M_SP810_CTRL_TIM3_SEL (1 << 21)
+#define V2M_SP810_BASE UL(0x1c020000)
+#define V2M_SP810_CTRL_TIM0_SEL BIT_32(15)
+#define V2M_SP810_CTRL_TIM1_SEL BIT_32(17)
+#define V2M_SP810_CTRL_TIM2_SEL BIT_32(19)
+#define V2M_SP810_CTRL_TIM3_SEL BIT_32(21)
/*
* The flash can be mapped either as read-only or read-write.
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 0f5b57f..088d59d 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -21,7 +21,7 @@
*****************************************************************************/
/* Special value used to verify platform parameters from BL2 to BL31 */
-#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
#define ARM_SYSTEM_COUNT 1
@@ -350,8 +350,8 @@
* To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
* and limit. Leave enough space of BL2 meminfo.
*/
-#define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t)
-#define ARM_TB_FW_CONFIG_LIMIT ARM_BL_RAM_BASE + PAGE_SIZE
+#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
/*******************************************************************************
* BL1 specific defines.
@@ -482,7 +482,7 @@
# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
- + (1 << 21))
+ + (UL(1) << 21))
# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
@@ -511,7 +511,7 @@
#define BL2U_LIMIT BL2_LIMIT
#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
-#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000)
+#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
/*
* ID of the secure physical generic timer interrupt used by the TSP.