diff --git a/plat/intel/soc/agilex/include/agilex_clock_manager.h b/plat/intel/soc/agilex/include/agilex_clock_manager.h
index 8ec8e59..ee22241 100644
--- a/plat/intel/soc/agilex/include/agilex_clock_manager.h
+++ b/plat/intel/soc/agilex/include/agilex_clock_manager.h
@@ -127,6 +127,7 @@
 uint32_t get_wdt_clk(void);
 uint32_t get_uart_clk(void);
 uint32_t get_mmc_clk(void);
+uint32_t get_mpu_clk(void);
 uint32_t get_cpu_clk(void);
 
 #endif
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 76b9937..10ef11b 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -388,12 +388,22 @@
 	return mmc_clk;
 }
 
+/* Return MPU clock */
+uint32_t get_mpu_clk(void)
+{
+	uint32_t mpu_clk;
+
+	mpu_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC0,
+				CLKMGR_PERPLL_PLLC0);
+	return mpu_clk;
+}
+
 /* Get cpu freq clock */
 uint32_t get_cpu_clk(void)
 {
 	uint32_t cpu_clk;
 
-	cpu_clk = get_l3_clk()/PLAT_SYS_COUNTER_CONVERT_TO_MHZ;
+	cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
 
 	return cpu_clk;
 }
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 2b3f144..4e50156 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -191,7 +191,7 @@
  * System counter frequency related constants
  ******************************************************************************/
 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS	(400000000)
-#define PLAT_SYS_COUNTER_CONVERT_TO_MHZ	(1000000)
+#define PLAT_HZ_CONVERT_TO_MHZ	(1000000)
 
 #define PLAT_INTEL_SOCFPGA_GICD_BASE	PLAT_GICD_BASE
 #define PLAT_INTEL_SOCFPGA_GICC_BASE	PLAT_GICC_BASE
diff --git a/plat/intel/soc/n5x/include/n5x_clock_manager.h b/plat/intel/soc/n5x/include/n5x_clock_manager.h
index 6e2b978..14a5717 100644
--- a/plat/intel/soc/n5x/include/n5x_clock_manager.h
+++ b/plat/intel/soc/n5x/include/n5x_clock_manager.h
@@ -22,6 +22,8 @@
 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK			GENMASK(26, 24)
 #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET		24
 
+#define CLKMGR_PLLOUTDIV_C0CNT_MASK			GENMASK(4, 0)
+#define CLKMGR_PLLOUTDIV_C0CNT_OFFSET			0
 #define CLKMGR_PLLOUTDIV_C1CNT_MASK			GENMASK(12, 8)
 #define CLKMGR_PLLOUTDIV_C1CNT_OFFSET			8
 #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK			GENMASK(26, 24)
@@ -52,6 +54,7 @@
 uint64_t clk_get_pll_output_hz(void);
 uint64_t get_l4_clk(void);
 uint32_t get_clk_freq(uint32_t psrc_reg);
+uint32_t get_mpu_clk(void);
 uint32_t get_cpu_clk(void);
 
 #endif
diff --git a/plat/intel/soc/n5x/soc/n5x_clock_manager.c b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
index c09b25b..f8ff2c5 100644
--- a/plat/intel/soc/n5x/soc/n5x_clock_manager.c
+++ b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
@@ -95,6 +95,44 @@
 	return clock;
 }
 
+/* Return MPU clock */
+uint32_t get_mpu_clk(void)
+{
+	uint32_t clock = 0;
+	uint32_t mainpll_c0cnt;
+	uint32_t perpll_c0cnt;
+	uint32_t clksrc;
+
+	mainpll_c0cnt = ((get_clk_freq(CLKMGR_MAINPLL_PLLOUTDIV)) &
+			CLKMGR_PLLOUTDIV_C0CNT_MASK) >> CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
+
+	perpll_c0cnt = ((get_clk_freq(CLKMGR_PERPLL_PLLOUTDIV)) &
+			CLKMGR_PLLOUTDIV_C0CNT_MASK) >> CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
+
+	clksrc = ((get_clk_freq(CLKMGR_MAINPLL_NOCCLK)) & CLKMGR_CLKSRC_MASK) >>
+			CLKMGR_CLKSRC_OFFSET;
+
+	switch (clksrc) {
+	case CLKMGR_CLKSRC_MAIN:
+		clock = clk_get_pll_output_hz();
+		clock /= 1 + mainpll_c0cnt;
+		break;
+
+	case CLKMGR_CLKSRC_PER:
+		clock = clk_get_pll_output_hz();
+		clock /= 1 + perpll_c0cnt;
+		break;
+
+	default:
+		return 0;
+	}
+
+	clock /= BIT(((get_clk_freq(CLKMGR_MAINPLL_NOCDIV)) >>
+			CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_NOCDIV_DIVIDER_MASK);
+
+	return clock;
+}
+
 /* Calculate clock frequency based on parameter */
 uint32_t get_clk_freq(uint32_t psrc_reg)
 {
@@ -110,7 +148,7 @@
 {
 	uint32_t cpu_clk = 0;
 
-	cpu_clk = get_l4_clk()/PLAT_SYS_COUNTER_CONVERT_TO_MHZ;
+	cpu_clk = get_mpu_clk()/PLAT_HZ_CONVERT_TO_MHZ;
 
 	return cpu_clk;
 }
diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
index 30009f7..416d359 100644
--- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
@@ -316,7 +316,7 @@
 	data32 = mmio_read_32(ALT_CLKMGR_MAINPLL + ALT_CLKMGR_MAINPLL_PLLGLOB);
 	ref_clk = get_ref_clk(data32);
 
-	cpu_clk = get_l3_clk(ref_clk)/PLAT_SYS_COUNTER_CONVERT_TO_MHZ;
+	cpu_clk = get_l3_clk(ref_clk)/PLAT_HZ_CONVERT_TO_MHZ;
 
 	return cpu_clk;
 }