feat(mediatek): configure DEV_IRQ as G1S interrupt
In order to register DEV_IRQ as secure interrupt in OP-TEE, the the GICD
EnableGrp1S should be enabled for DEV_IRQ. Add mtk_interrupt_props in
MTK GIC driver to configure the interrupt properly.
Change-Id: Id909a42b535088c6d0dcaf803d3f2faf312ae846
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index 8696f2a..a70abec 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -95,6 +95,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 23