Merge pull request #1808 from sandrine-bailleux-arm/sb/maintainers
maintainers: Fix broken links to some Github accounts
diff --git a/Makefile b/Makefile
index 0169f3f..34f6890 100644
--- a/Makefile
+++ b/Makefile
@@ -248,7 +248,6 @@
# Common sources and include directories
################################################################################
include lib/compiler-rt/compiler-rt.mk
-include lib/libc/libc.mk
BL_COMMON_SOURCES += common/bl_common.c \
common/tf_log.c \
@@ -390,6 +389,13 @@
include ${AARCH32_SP_MAKE}
endif
+endif
+
+################################################################################
+# Include libc if not overridden
+################################################################################
+ifeq (${OVERRIDE_LIBC},0)
+include lib/libc/libc.mk
endif
################################################################################
@@ -595,6 +601,7 @@
$(eval $(call assert_boolean,HW_ASSISTED_COHERENCY))
$(eval $(call assert_boolean,MULTI_CONSOLE_API))
$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call assert_boolean,OVERRIDE_LIBC))
$(eval $(call assert_boolean,PL011_GENERIC_UART))
$(eval $(call assert_boolean,PROGRAMMABLE_RESET_ADDRESS))
$(eval $(call assert_boolean,PSCI_EXTENDED_STATE_ID))
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 1af1962..c7d587c 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -224,9 +224,11 @@
*/
. = ALIGN(CACHE_WRITEBACK_GRANULE);
__BAKERY_LOCK_START__ = .;
+ __PERCPU_BAKERY_LOCK_START__ = .;
*(bakery_lock)
. = ALIGN(CACHE_WRITEBACK_GRANULE);
- __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
+ __PERCPU_BAKERY_LOCK_END__ = .;
+ __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
__BAKERY_LOCK_END__ = .;
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index 3cd427d..83b7860 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -151,9 +151,11 @@
*/
. = ALIGN(CACHE_WRITEBACK_GRANULE);
__BAKERY_LOCK_START__ = .;
+ __PERCPU_BAKERY_LOCK_START__ = .;
*(bakery_lock)
. = ALIGN(CACHE_WRITEBACK_GRANULE);
- __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
+ __PERCPU_BAKERY_LOCK_END__ = .;
+ __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
__BAKERY_LOCK_END__ = .;
#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
diff --git a/docs/auth-framework.rst b/docs/auth-framework.rst
index e0b569f..7e401b7 100644
--- a/docs/auth-framework.rst
+++ b/docs/auth-framework.rst
@@ -209,7 +209,7 @@
#. Tracking which images have been verified. In case an image is a part of
multiple CoTs then it should be verified only once e.g. the Trusted World
Key Certificate in the TBBR-Client spec. contains information to verify
- SCP\_BL2, BL31, BL32 each of which have a separate CoT. (This
+ SCP_BL2, BL31, BL32 each of which have a separate CoT. (This
responsibility has not been described in this document but should be
trivial to implement).
@@ -627,7 +627,7 @@
The CoT can be found in ``drivers/auth/tbbr/tbbr_cot.c``. This CoT consists of an
array of image descriptors and it is registered in the framework using the macro
-``REGISTER_COT(cot_desc)``, where 'cot\_desc' must be the name of the array
+``REGISTER_COT(cot_desc)``, where 'cot_desc' must be the name of the array
(passing a pointer or any other type of indirection will cause the registration
process to fail).
@@ -720,7 +720,7 @@
Four image descriptors form the BL31 Chain of Trust:
-.. code:: asm
+.. code:: c
[TRUSTED_KEY_CERT_ID] = {
.img_id = TRUSTED_KEY_CERT_ID,
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 11fcf21..728790a 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -973,7 +973,7 @@
- Updated PSCI support:
- - Added support for PSCI NODE\_HW\_STATE API for Arm platforms.
+ - Added support for PSCI NODE_HW_STATE API for Arm platforms.
- New optional platform hook, ``pwr_domain_pwr_down_wfi()``, in
``plat_psci_ops`` to enable platforms to perform platform-specific actions
@@ -1000,14 +1000,14 @@
This can be useful to map a non-cacheable memory region, such as a DMA
buffer.
- - Introduced the MT\_EXECUTE/MT\_EXECUTE\_NEVER memory mapping attributes to
+ - Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to
specify the access permissions for instruction execution of a memory
region.
- Enabled support to isolate code and read-only data on separate memory pages,
allowing independent access control to be applied to each.
-- Enabled SCR\_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common
+- Enabled SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common
architectural setup code, preventing fetching instructions from non-secure
memory when in secure state.
@@ -1025,7 +1025,7 @@
the working directory.
- Aligned command line options for specifying images to use same naming
- convention as specified by TBBR and already used in cert\_create tool.
+ convention as specified by TBBR and already used in cert_create tool.
- Refactored the TZC-400 driver to also support memory controllers that
integrate TZC functionality, for example Arm CoreLink DMC-500. Also added
@@ -1036,7 +1036,7 @@
- Enhanced support for Arm platforms:
- - Updated image loading support to make SCP images (SCP\_BL2 and SCP\_BL2U)
+ - Updated image loading support to make SCP images (SCP_BL2 and SCP_BL2U)
optional.
- Enhanced topology description support to allow multi-cluster topology
@@ -1104,7 +1104,7 @@
**Note** the default build of TF-A will not be able to boot
Linux kernel with GICv2 FDT blob.
- - Enabled wake-up from CPU\_SUSPEND to stand-by by temporarily re-routing
+ - Enabled wake-up from CPU_SUSPEND to stand-by by temporarily re-routing
interrupts and then restoring after resume.
Issues resolved since last release
@@ -1219,7 +1219,7 @@
- Better alignment with version 1.0 of the PSCI specification.
-- Added support for the SYSTEM\_SUSPEND PSCI API on Arm platforms. When invoked
+- Added support for the SYSTEM_SUSPEND PSCI API on Arm platforms. When invoked
on the last running core on a supported platform, this puts the system
into a low power mode with memory retention.
@@ -1615,7 +1615,7 @@
<SimName>System Generator:FVP_Base_A57x4_A53x4</SimName>
to
- System Generator:FVP\_Base\_Cortex-A57x4\_A53x4
+ System Generator:FVP_Base_Cortex-A57x4_A53x4
A similar change can be made to the other Cortex-A57-A53 Base FVP variants.
@@ -1643,7 +1643,7 @@
- Moved architectural timer setup to platform-specific code.
-- Added standby state support to PSCI cpu\_suspend implementation.
+- Added standby state support to PSCI cpu_suspend implementation.
- SRAM usage improvements:
@@ -1669,7 +1669,7 @@
default configuration is provided for the Base FVPs. This means the model
parameter ``-C bp.secure_memory=1`` is now supported.
-- Started saving the PSCI cpu\_suspend 'power\_state' parameter prior to
+- Started saving the PSCI cpu_suspend 'power_state' parameter prior to
suspending a CPU. This allows platforms that implement multiple power-down
states at the same affinity level to identify a specific state.
@@ -1767,13 +1767,13 @@
instructions for how to contribute and updated copyright text in all files
to acknowledge contributors.
-- The PSCI CPU\_SUSPEND API has been stabilised to the extent where it can be
+- The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be
used for entry into power down states with the following restrictions:
- Entry into standby states is not supported.
- The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs.
-- The PSCI AFFINITY\_INFO api has undergone limited testing on the Base FVPs to
+- The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to
allow experimental use.
- Required C library and runtime header files are now included locally in
@@ -1803,7 +1803,7 @@
particular code modules to DRAM itself.
- Reworked BL2 to BL3-1 handover interface. A new composite structure
- (bl31\_args) holds the superset of information that needs to be passed from
+ (bl31_args) holds the superset of information that needs to be passed from
BL2 to BL3-1, including information on how handover execution control to
BL3-2 (if present) and BL3-3 (non-trusted firmware).
@@ -1817,7 +1817,7 @@
- Added a framework for implementing EL3 runtime services. Reworked the PSCI
implementation to be one such runtime service.
-- Reworked the exception handling logic, making use of both SP\_EL0 and SP\_EL3
+- Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3
stack pointers for determining the type of exception, managing general
purpose and system register context on exception entry/exit, and handling
SMCs. SMCs are directed to the correct EL3 runtime service.
diff --git a/docs/coding-guidelines.rst b/docs/coding-guidelines.rst
index d5ac978..e8f365b 100644
--- a/docs/coding-guidelines.rst
+++ b/docs/coding-guidelines.rst
@@ -85,7 +85,7 @@
#include "./a_header.h"
Include statement variants
-^^^^^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^
Two variants of the ``#include`` directive are acceptable in the TF codebase.
Correct use of the two styles improves readability by suggesting the location
@@ -125,7 +125,7 @@
------------------
Use of built-in *C* and *libc* data types
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The TF codebase should be kept as portable as possible, especially since both
64-bit and 32-bit platforms are supported. To help with this, the following data
@@ -214,9 +214,8 @@
u_register_t arg7;
} aapcs64_params_t;
-
- If some code wants to operate on ``arg0`` and knows that it represents a
- 32-bit unsigned integer on all systems, cast it to ``unsigned int``.
+If some code wants to operate on ``arg0`` and knows that it represents a 32-bit
+unsigned integer on all systems, cast it to ``unsigned int``.
These guidelines should be updated if additional types are needed.
diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst
index 077d470..40128ed 100644
--- a/docs/cpu-specific-build-macros.rst
+++ b/docs/cpu-specific-build-macros.rst
@@ -93,7 +93,7 @@
- ``ERRATA_A53_855873``: This applies errata 855873 workaround to Cortex-A53
CPUs. Though the erratum is present in every revision of the CPU,
this workaround is only applied to CPUs from r0p3 onwards, which feature
- a chicken bit in CPUACTLR\_EL1 to enable a hardware workaround.
+ a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
Earlier revisions of the CPU have other errata which require the same
workaround in software, so they should be covered anyway.
@@ -194,4 +194,4 @@
.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html
.. _Firmware Design guide: firmware-design.rst
.. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf
-.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html
\ No newline at end of file
+.. _Arm DSU Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm138168/index.html
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index 06fdbac..617cbb8 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -404,16 +404,16 @@
configuration files can be passed to next Boot Loader stages as arguments
by updating the corresponding entrypoint information in this function.
-SCP\_BL2 (System Control Processor Firmware) image load
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+SCP_BL2 (System Control Processor Firmware) image load
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Some systems have a separate System Control Processor (SCP) for power, clock,
-reset and system control. BL2 loads the optional SCP\_BL2 image from platform
+reset and system control. BL2 loads the optional SCP_BL2 image from platform
storage into a platform-specific region of secure memory. The subsequent
-handling of SCP\_BL2 is platform specific. For example, on the Juno Arm
+handling of SCP_BL2 is platform specific. For example, on the Juno Arm
development platform port the image is transferred into SCP's internal memory
using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
-memory. The SCP executes SCP\_BL2 and signals to the Application Processor (AP)
+memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
for BL2 execution to continue.
EL3 Runtime Software image load
@@ -688,7 +688,7 @@
These structures are designed to support compatibility and independent
evolution of the structures and the firmware images. For example, a version of
BL31 that can interpret the BL3x image information from different versions of
-BL2, a platform that uses an extended entry\_point\_info structure to convey
+BL2, a platform that uses an extended entry_point_info structure to convey
additional register information to BL31, or a ELF image loader that can convey
more details about the firmware images.
@@ -803,10 +803,10 @@
When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
Runtime Software must ensure execution of a warm boot initialization entrypoint.
-If TF-A BL1 is used and the PROGRAMMABLE\_RESET\_ADDRESS build flag is false,
+If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
boot entrypoint by arranging for the BL1 platform function,
-plat\_get\_my\_entrypoint(), to return a non-zero value.
+plat_get_my_entrypoint(), to return a non-zero value.
In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
data access and all interrupt sources masked:
@@ -996,7 +996,7 @@
`Power State Coordination Interface PDD`_ are implemented. The table lists
the PSCI v1.1 APIs and their support in generic code.
-An API implementation might have a dependency on platform code e.g. CPU\_SUSPEND
+An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
requires the platform to export a part of the implementation. Hence the level
of support of the mandatory APIs depends upon the support exported by the
platform port as well. The Juno and FVP (all variants) platforms export all the
@@ -1657,13 +1657,13 @@
- BL2 is loaded below BL1 RW
-- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP\_MIN),
+- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
overwrite BL1 R/W data and BL2. This implies that BL1 global variables
remain valid only until execution reaches the EL3 Runtime Software entry
point during a cold boot.
-- On Juno, SCP\_BL2 is loaded temporarily into the EL3 Runtime Software memory
+- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
region and transfered to the SCP before being overwritten by EL3 Runtime
Software.
@@ -2089,11 +2089,11 @@
To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
has been redesigned. The changes utilise the characteristic of Lamport's Bakery
-algorithm mentioned earlier. The bakery\_lock structure only allocates the memory
+algorithm mentioned earlier. The bakery_lock structure only allocates the memory
for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
-for other cores by using the total size allocated for the bakery\_lock section
-and multiplying it with (PLATFORM\_CORE\_COUNT - 1). This enables software to
+for other cores by using the total size allocated for the bakery_lock section
+and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
perform software cache maintenance on the lock data structure without running
into coherency issues associated with mismatched attributes.
@@ -2155,7 +2155,7 @@
------------------
Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
-operation on Lock\_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
+operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
``bakery_lock`` section need to be fetched and appropriate cache operations need
to be performed for each access.
@@ -2343,18 +2343,18 @@
A subscriber that wants to subscribe to event ``foo`` published above would
implement:
-::
+.. code:: c
- void *foo_handler(const void *arg)
- {
- void *result;
+ void *foo_handler(const void *arg)
+ {
+ void *result;
- /* Do handling ... */
+ /* Do handling ... */
- return result;
- }
+ return result;
+ }
- SUBSCRIBE_TO_EVENT(foo, foo_handler);
+ SUBSCRIBE_TO_EVENT(foo, foo_handler);
Reclaiming the BL31 initialization code
@@ -2619,8 +2619,8 @@
lib Yes Yes Yes
services No No Yes
-The build system provides a non configurable build option IMAGE\_BLx for each
-boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE\_BL1 will be
+The build system provides a non configurable build option IMAGE_BLx for each
+boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
defined by the build system. This enables TF-A to compile certain code only
for specific boot loader stages
diff --git a/docs/firmware-update.rst b/docs/firmware-update.rst
index 3ee57bc..1f07f76 100644
--- a/docs/firmware-update.rst
+++ b/docs/firmware-update.rst
@@ -135,8 +135,8 @@
BL1 SMC Interface
-----------------
-BL1\_SMC\_CALL\_COUNT
-~~~~~~~~~~~~~~~~~~~~~
+BL1_SMC_CALL_COUNT
+~~~~~~~~~~~~~~~~~~
::
@@ -148,8 +148,8 @@
This SMC returns the number of SMCs supported by BL1.
-BL1\_SMC\_UID
-~~~~~~~~~~~~~
+BL1_SMC_UID
+~~~~~~~~~~~
::
@@ -162,8 +162,8 @@
This SMC returns the 128-bit `Universally Unique Identifier`_ for the
BL1 SMC service.
-BL1\_SMC\_VERSION
-~~~~~~~~~~~~~~~~~
+BL1_SMC_VERSION
+~~~~~~~~~~~~~~~
::
@@ -176,8 +176,8 @@
This SMC returns the current version of the BL1 SMC service.
-BL1\_SMC\_RUN\_IMAGE
-~~~~~~~~~~~~~~~~~~~~
+BL1_SMC_RUN_IMAGE
+~~~~~~~~~~~~~~~~~
::
@@ -196,8 +196,8 @@
``entry_point_info_t`` structure. In the normal TF-A boot flow, BL2 invokes
this SMC for BL1 to pass execution control to BL31.
-FWU\_SMC\_IMAGE\_COPY
-~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_IMAGE_COPY
+~~~~~~~~~~~~~~~~~~
::
@@ -245,8 +245,8 @@
Once the SMC is handled, BL1 returns from exception to the normal world caller.
-FWU\_SMC\_IMAGE\_AUTH
-~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_IMAGE_AUTH
+~~~~~~~~~~~~~~~~~~
::
@@ -285,8 +285,8 @@
sets the image state to AUTHENTICATED. If authentication fails then BL1 returns
the -EAUTH error and sets the image state back to RESET.
-FWU\_SMC\_IMAGE\_EXECUTE
-~~~~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_IMAGE_EXECUTE
+~~~~~~~~~~~~~~~~~~~~~
::
@@ -313,8 +313,8 @@
BL1 saves the normal world caller's context, sets the secure image state to
EXECUTED, and returns from exception to the secure image.
-FWU\_SMC\_IMAGE\_RESUME
-~~~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_IMAGE_RESUME
+~~~~~~~~~~~~~~~~~~~~
::
@@ -340,8 +340,8 @@
``image_param`` is returned to the resumed world, otherwise an error code is
returned to the caller.
-FWU\_SMC\_SEC\_IMAGE\_DONE
-~~~~~~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_SEC_IMAGE_DONE
+~~~~~~~~~~~~~~~~~~~~~~
::
@@ -361,8 +361,8 @@
restores the normal world context and returns from exception into the normal
world.
-FWU\_SMC\_UPDATE\_DONE
-~~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_UPDATE_DONE
+~~~~~~~~~~~~~~~~~~~
::
@@ -377,8 +377,8 @@
function ``bl1_plat_fwu_done``, passing the optional argument ``client_cookie`` as
a ``void *``. The SMC does not return.
-FWU\_SMC\_IMAGE\_RESET
-~~~~~~~~~~~~~~~~~~~~~~
+FWU_SMC_IMAGE_RESET
+~~~~~~~~~~~~~~~~~~~
::
diff --git a/docs/interrupt-framework-design.rst b/docs/interrupt-framework-design.rst
index 4247f1f..52d1ed4 100644
--- a/docs/interrupt-framework-design.rst
+++ b/docs/interrupt-framework-design.rst
@@ -451,7 +451,7 @@
The handover agreement between the TSP and the TSPD requires that the TSPD
masks all interrupts (``PSTATE.DAIF`` bits) when it calls
``tsp_sel1_intr_entry()``. The TSP has to preserve the callee saved general
- purpose, SP\_EL1/Secure-EL0, LR, VFP and system registers. It can use
+ purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use
``x0-x18`` to enable its C runtime.
#. The TSPD implements a handler function for Secure-EL1 interrupts. This
@@ -595,7 +595,7 @@
``early_exceptions`` variable, with a vector table capable of handling FIQ and IRQ
exceptions taken at the same (Secure-EL1) exception level. This table is
referenced through the ``tsp_exceptions`` variable and programmed into the
-VBAR\_EL1. It caters for the asynchronous handling model.
+VBAR_EL1. It caters for the asynchronous handling model.
The TSP also programs the Secure Physical Timer in the Arm Generic Timer block
to raise a periodic interrupt (every half a second) for the purpose of testing
@@ -904,7 +904,7 @@
receiving control from the SPD service at an entrypoint agreed upon during build
time or during the registration phase. Before handling the interrupt, the SP
should save any Secure-EL1 system register context which is needed for resuming
-normal execution in the SP later e.g. ``SPSR_EL1,``\ ELR\_EL1\`. After handling the
+normal execution in the SP later e.g. ``SPSR_EL1,``\ ELR_EL1\`. After handling the
interrupt, the SP could return control back to the exception level and security
state where the interrupt was originally taken from. The SP should use an SMC32
or SMC64 to ask the SPD service to do this.
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst
index 90d2ae1..7ed0f2c 100644
--- a/docs/plat/nvidia-tegra.rst
+++ b/docs/plat/nvidia-tegra.rst
@@ -1,6 +1,23 @@
Tegra SoCs - Overview
=====================
+- .. rubric:: T186
+ :name: t186
+
+The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
+multi-processing (HMP) solution designed to optimize performance and
+efficiency.
+
+T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
+in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
+support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
+including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
+Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
+unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
+Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
+high speed coherency fabric connects these two processor complexes and allows
+heterogeneous multi-processing with all six cores if required.
+
- .. rubric:: T210
:name: t210
@@ -49,11 +66,21 @@
Trusted OS dispatcher
=====================
+Tegra supports multiple Trusted OS'.
+
-Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of
-them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd'
-on the command line while preparing a bl31 image. This allows other Trusted OS
-vendors to use the upstream code and include their dispatchers in the image
-without changing any makefiles.
+- Trusted Little Kernel (TLK): In order to include the 'tlkd' dispatcher in
+ the image, pass 'SPD=tlkd' on the command line while preparing a bl31 image.
+- Trusty: In order to include the 'trusty' dispatcher in the image, pass
+ 'SPD=trusty' on the command line while preparing a bl31 image.
+
+This allows other Trusted OS vendors to use the upstream code and include
+their dispatchers in the image without changing any makefiles.
+
+These are the supported Trusted OS' by Tegra platforms.
+
+Tegra132: TLK
+Tegra210: TLK and Trusty
+Tegra186: Trusty
Preparing the BL31 image to run on Tegra SoCs
=============================================
@@ -61,7 +88,8 @@
.. code:: shell
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
- TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31
+ TARGET_SOC=<target-soc e.g. t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
+ bl31
Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
to the build command line.
diff --git a/docs/platform-compatibility-policy.rst b/docs/platform-compatibility-policy.rst
index b33c4e7..b23d539 100644
--- a/docs/platform-compatibility-policy.rst
+++ b/docs/platform-compatibility-policy.rst
@@ -1,5 +1,5 @@
TF-A Platform Compatibility Policy
-======================================================
+==================================
.. section-numbering::
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 655c720..422c340 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -28,7 +28,7 @@
default implementation is inadequate.
Platform ports that want to be aligned with standard Arm platforms (for example
-FVP and Juno) may also use `include/plat/arm/common/plat\_arm.h`_ and the
+FVP and Juno) may also use `include/plat/arm/common/plat_arm.h`_ and the
corresponding source files in ``plat/arm/common/``. These provide standard
implementations for some of the required platform porting functions. However,
using these functions requires the platform port to implement additional
@@ -99,56 +99,56 @@
The following variables, functions and constants must be defined by the platform
for the firmware to work correctly.
-File : platform\_def.h [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+File : platform_def.h [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure that a header file of this name is in the system
include path with the following constants defined. This will require updating
the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
-Platform ports may optionally use the file `include/plat/common/common\_def.h`_,
+Platform ports may optionally use the file `include/plat/common/common_def.h`_,
which provides typical values for some of the constants below. These values are
likely to be suitable for all platform ports.
-- **#define : PLATFORM\_LINKER\_FORMAT**
+- **#define : PLATFORM_LINKER_FORMAT**
Defines the linker format used by the platform, for example
``elf64-littleaarch64``.
-- **#define : PLATFORM\_LINKER\_ARCH**
+- **#define : PLATFORM_LINKER_ARCH**
Defines the processor architecture for the linker by the platform, for
example ``aarch64``.
-- **#define : PLATFORM\_STACK\_SIZE**
+- **#define : PLATFORM_STACK_SIZE**
Defines the normal stack memory available to each CPU. This constant is used
- by `plat/common/aarch64/platform\_mp\_stack.S`_ and
- `plat/common/aarch64/platform\_up\_stack.S`_.
+ by `plat/common/aarch64/platform_mp_stack.S`_ and
+ `plat/common/aarch64/platform_up_stack.S`_.
-- **define : CACHE\_WRITEBACK\_GRANULE**
+- **define : CACHE_WRITEBACK_GRANULE**
Defines the size in bits of the largest cache line across all the cache
levels in the platform.
-- **#define : FIRMWARE\_WELCOME\_STR**
+- **#define : FIRMWARE_WELCOME_STR**
Defines the character string printed by BL1 upon entry into the ``bl1_main()``
function.
-- **#define : PLATFORM\_CORE\_COUNT**
+- **#define : PLATFORM_CORE_COUNT**
Defines the total number of CPUs implemented by the platform across all
clusters in the system.
-- **#define : PLAT\_NUM\_PWR\_DOMAINS**
+- **#define : PLAT_NUM_PWR_DOMAINS**
Defines the total number of nodes in the power domain topology
tree at all the power domain levels used by the platform.
This macro is used by the PSCI implementation to allocate
data structures to represent power domain topology.
-- **#define : PLAT\_MAX\_PWR\_LVL**
+- **#define : PLAT_MAX_PWR_LVL**
Defines the maximum power domain level that the power management operations
should apply to. More often, but not always, the power domain level
@@ -158,24 +158,24 @@
example, the Base AEM FVP implements two clusters with a configurable
number of CPUs and it reports the maximum power domain level as 1.
-- **#define : PLAT\_MAX\_OFF\_STATE**
+- **#define : PLAT_MAX_OFF_STATE**
Defines the local power state corresponding to the deepest power down
possible at every power domain level in the platform. The local power
states for each level may be sparsely allocated between 0 and this value
with 0 being reserved for the RUN state. The PSCI implementation uses this
value to initialize the local power states of the power domain nodes and
- to specify the requested power state for a PSCI\_CPU\_OFF call.
+ to specify the requested power state for a PSCI_CPU_OFF call.
-- **#define : PLAT\_MAX\_RET\_STATE**
+- **#define : PLAT_MAX_RET_STATE**
Defines the local power state corresponding to the deepest retention state
possible at every power domain level in the platform. This macro should be
- a value less than PLAT\_MAX\_OFF\_STATE and greater than 0. It is used by the
+ a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the
PSCI implementation to distinguish between retention and power down local
- power states within PSCI\_CPU\_SUSPEND call.
+ power states within PSCI_CPU_SUSPEND call.
-- **#define : PLAT\_MAX\_PWR\_LVL\_STATES**
+- **#define : PLAT_MAX_PWR_LVL_STATES**
Defines the maximum number of local power states per power domain level
that the platform supports. The default value of this macro is 2 since
@@ -184,69 +184,69 @@
account for more local power states, then it must redefine this macro.
Currently, this macro is used by the Generic PSCI implementation to size
- the array used for PSCI\_STAT\_COUNT/RESIDENCY accounting.
+ the array used for PSCI_STAT_COUNT/RESIDENCY accounting.
-- **#define : BL1\_RO\_BASE**
+- **#define : BL1_RO_BASE**
Defines the base address in secure ROM where BL1 originally lives. Must be
aligned on a page-size boundary.
-- **#define : BL1\_RO\_LIMIT**
+- **#define : BL1_RO_LIMIT**
Defines the maximum address in secure ROM that BL1's actual content (i.e.
excluding any data section allocated at runtime) can occupy.
-- **#define : BL1\_RW\_BASE**
+- **#define : BL1_RW_BASE**
Defines the base address in secure RAM where BL1's read-write data will live
at runtime. Must be aligned on a page-size boundary.
-- **#define : BL1\_RW\_LIMIT**
+- **#define : BL1_RW_LIMIT**
Defines the maximum address in secure RAM that BL1's read-write data can
occupy at runtime.
-- **#define : BL2\_BASE**
+- **#define : BL2_BASE**
Defines the base address in secure RAM where BL1 loads the BL2 binary image.
Must be aligned on a page-size boundary. This constant is not applicable
when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_LIMIT**
+- **#define : BL2_LIMIT**
Defines the maximum address in secure RAM that the BL2 image can occupy.
This constant is not applicable when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RO\_BASE**
+- **#define : BL2_RO_BASE**
Defines the base address in secure XIP memory where BL2 RO section originally
lives. Must be aligned on a page-size boundary. This constant is only needed
when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RO\_LIMIT**
+- **#define : BL2_RO_LIMIT**
Defines the maximum address in secure XIP memory that BL2's actual content
(i.e. excluding any data section allocated at runtime) can occupy. This
constant is only needed when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RW\_BASE**
+- **#define : BL2_RW_BASE**
Defines the base address in secure RAM where BL2's read-write data will live
at runtime. Must be aligned on a page-size boundary. This constant is only
needed when BL2_IN_XIP_MEM is set to '1'.
-- **#define : BL2\_RW\_LIMIT**
+- **#define : BL2_RW_LIMIT**
Defines the maximum address in secure RAM that BL2's read-write data can
occupy at runtime. This constant is only needed when BL2_IN_XIP_MEM is set
to '1'.
-- **#define : BL31\_BASE**
+- **#define : BL31_BASE**
Defines the base address in secure RAM where BL2 loads the BL31 binary
image. Must be aligned on a page-size boundary.
-- **#define : BL31\_LIMIT**
+- **#define : BL31_LIMIT**
Defines the maximum address in secure RAM that the BL31 image can occupy.
@@ -258,57 +258,57 @@
authentication information, etc.). The following image identifiers are
mandatory:
-- **#define : BL2\_IMAGE\_ID**
+- **#define : BL2_IMAGE_ID**
BL2 image identifier, used by BL1 to load BL2.
-- **#define : BL31\_IMAGE\_ID**
+- **#define : BL31_IMAGE_ID**
BL31 image identifier, used by BL2 to load BL31.
-- **#define : BL33\_IMAGE\_ID**
+- **#define : BL33_IMAGE_ID**
BL33 image identifier, used by BL2 to load BL33.
If Trusted Board Boot is enabled, the following certificate identifiers must
also be defined:
-- **#define : TRUSTED\_BOOT\_FW\_CERT\_ID**
+- **#define : TRUSTED_BOOT_FW_CERT_ID**
BL2 content certificate identifier, used by BL1 to load the BL2 content
certificate.
-- **#define : TRUSTED\_KEY\_CERT\_ID**
+- **#define : TRUSTED_KEY_CERT_ID**
Trusted key certificate identifier, used by BL2 to load the trusted key
certificate.
-- **#define : SOC\_FW\_KEY\_CERT\_ID**
+- **#define : SOC_FW_KEY_CERT_ID**
BL31 key certificate identifier, used by BL2 to load the BL31 key
certificate.
-- **#define : SOC\_FW\_CONTENT\_CERT\_ID**
+- **#define : SOC_FW_CONTENT_CERT_ID**
BL31 content certificate identifier, used by BL2 to load the BL31 content
certificate.
-- **#define : NON\_TRUSTED\_FW\_KEY\_CERT\_ID**
+- **#define : NON_TRUSTED_FW_KEY_CERT_ID**
BL33 key certificate identifier, used by BL2 to load the BL33 key
certificate.
-- **#define : NON\_TRUSTED\_FW\_CONTENT\_CERT\_ID**
+- **#define : NON_TRUSTED_FW_CONTENT_CERT_ID**
BL33 content certificate identifier, used by BL2 to load the BL33 content
certificate.
-- **#define : FWU\_CERT\_ID**
+- **#define : FWU_CERT_ID**
- Firmware Update (FWU) certificate identifier, used by NS\_BL1U to load the
+ Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the
FWU content certificate.
-- **#define : PLAT\_CRYPTOCELL\_BASE**
+- **#define : PLAT_CRYPTOCELL_BASE**
This defines the base address of Arm® TrustZone® CryptoCell and must be
defined if CryptoCell crypto driver is used for Trusted Board Boot. For
@@ -318,125 +318,125 @@
If the AP Firmware Updater Configuration image, BL2U is used, the following
must also be defined:
-- **#define : BL2U\_BASE**
+- **#define : BL2U_BASE**
Defines the base address in secure memory where BL1 copies the BL2U binary
image. Must be aligned on a page-size boundary.
-- **#define : BL2U\_LIMIT**
+- **#define : BL2U_LIMIT**
Defines the maximum address in secure memory that the BL2U image can occupy.
-- **#define : BL2U\_IMAGE\_ID**
+- **#define : BL2U_IMAGE_ID**
BL2U image identifier, used by BL1 to fetch an image descriptor
corresponding to BL2U.
-If the SCP Firmware Update Configuration Image, SCP\_BL2U is used, the following
+If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following
must also be defined:
-- **#define : SCP\_BL2U\_IMAGE\_ID**
+- **#define : SCP_BL2U_IMAGE_ID**
- SCP\_BL2U image identifier, used by BL1 to fetch an image descriptor
- corresponding to SCP\_BL2U.
+ SCP_BL2U image identifier, used by BL1 to fetch an image descriptor
+ corresponding to SCP_BL2U.
NOTE: TF-A does not provide source code for this image.
-If the Non-Secure Firmware Updater ROM, NS\_BL1U is used, the following must
+If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must
also be defined:
-- **#define : NS\_BL1U\_BASE**
+- **#define : NS_BL1U_BASE**
- Defines the base address in non-secure ROM where NS\_BL1U executes.
+ Defines the base address in non-secure ROM where NS_BL1U executes.
Must be aligned on a page-size boundary.
NOTE: TF-A does not provide source code for this image.
-- **#define : NS\_BL1U\_IMAGE\_ID**
+- **#define : NS_BL1U_IMAGE_ID**
- NS\_BL1U image identifier, used by BL1 to fetch an image descriptor
- corresponding to NS\_BL1U.
+ NS_BL1U image identifier, used by BL1 to fetch an image descriptor
+ corresponding to NS_BL1U.
-If the Non-Secure Firmware Updater, NS\_BL2U is used, the following must also
+If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also
be defined:
-- **#define : NS\_BL2U\_BASE**
+- **#define : NS_BL2U_BASE**
- Defines the base address in non-secure memory where NS\_BL2U executes.
+ Defines the base address in non-secure memory where NS_BL2U executes.
Must be aligned on a page-size boundary.
NOTE: TF-A does not provide source code for this image.
-- **#define : NS\_BL2U\_IMAGE\_ID**
+- **#define : NS_BL2U_IMAGE_ID**
- NS\_BL2U image identifier, used by BL1 to fetch an image descriptor
- corresponding to NS\_BL2U.
+ NS_BL2U image identifier, used by BL1 to fetch an image descriptor
+ corresponding to NS_BL2U.
For the the Firmware update capability of TRUSTED BOARD BOOT, the following
macros may also be defined:
-- **#define : PLAT\_FWU\_MAX\_SIMULTANEOUS\_IMAGES**
+- **#define : PLAT_FWU_MAX_SIMULTANEOUS_IMAGES**
Total number of images that can be loaded simultaneously. If the platform
doesn't specify any value, it defaults to 10.
-If a SCP\_BL2 image is supported by the platform, the following constants must
+If a SCP_BL2 image is supported by the platform, the following constants must
also be defined:
-- **#define : SCP\_BL2\_IMAGE\_ID**
+- **#define : SCP_BL2_IMAGE_ID**
- SCP\_BL2 image identifier, used by BL2 to load SCP\_BL2 into secure memory
+ SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory
from platform storage before being transferred to the SCP.
-- **#define : SCP\_FW\_KEY\_CERT\_ID**
+- **#define : SCP_FW_KEY_CERT_ID**
- SCP\_BL2 key certificate identifier, used by BL2 to load the SCP\_BL2 key
+ SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key
certificate (mandatory when Trusted Board Boot is enabled).
-- **#define : SCP\_FW\_CONTENT\_CERT\_ID**
+- **#define : SCP_FW_CONTENT_CERT_ID**
- SCP\_BL2 content certificate identifier, used by BL2 to load the SCP\_BL2
+ SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2
content certificate (mandatory when Trusted Board Boot is enabled).
If a BL32 image is supported by the platform, the following constants must
also be defined:
-- **#define : BL32\_IMAGE\_ID**
+- **#define : BL32_IMAGE_ID**
BL32 image identifier, used by BL2 to load BL32.
-- **#define : TRUSTED\_OS\_FW\_KEY\_CERT\_ID**
+- **#define : TRUSTED_OS_FW_KEY_CERT_ID**
BL32 key certificate identifier, used by BL2 to load the BL32 key
certificate (mandatory when Trusted Board Boot is enabled).
-- **#define : TRUSTED\_OS\_FW\_CONTENT\_CERT\_ID**
+- **#define : TRUSTED_OS_FW_CONTENT_CERT_ID**
BL32 content certificate identifier, used by BL2 to load the BL32 content
certificate (mandatory when Trusted Board Boot is enabled).
-- **#define : BL32\_BASE**
+- **#define : BL32_BASE**
Defines the base address in secure memory where BL2 loads the BL32 binary
image. Must be aligned on a page-size boundary.
-- **#define : BL32\_LIMIT**
+- **#define : BL32_LIMIT**
Defines the maximum address that the BL32 image can occupy.
If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the
platform, the following constants must also be defined:
-- **#define : TSP\_SEC\_MEM\_BASE**
+- **#define : TSP_SEC_MEM_BASE**
Defines the base address of the secure memory used by the TSP image on the
platform. This must be at the same address or below ``BL32_BASE``.
-- **#define : TSP\_SEC\_MEM\_SIZE**
+- **#define : TSP_SEC_MEM_SIZE**
Defines the size of the secure memory used by the BL32 image on the
platform. ``TSP_SEC_MEM_BASE`` and ``TSP_SEC_MEM_SIZE`` must fully
accommodate the memory required by the BL32 image, defined by ``BL32_BASE``
and ``BL32_LIMIT``.
-- **#define : TSP\_IRQ\_SEC\_PHY\_TIMER**
+- **#define : TSP_IRQ_SEC_PHY_TIMER**
Defines the ID of the secure physical generic timer interrupt used by the
TSP's interrupt handling code.
@@ -444,14 +444,14 @@
If the platform port uses the translation table library code, the following
constants must also be defined:
-- **#define : PLAT\_XLAT\_TABLES\_DYNAMIC**
+- **#define : PLAT_XLAT_TABLES_DYNAMIC**
Optional flag that can be set per-image to enable the dynamic allocation of
regions even when the MMU is enabled. If not defined, only static
functionality will be available, if defined and set to 1 it will also
include the dynamic functionality.
-- **#define : MAX\_XLAT\_TABLES**
+- **#define : MAX_XLAT_TABLES**
Defines the maximum number of translation tables that are allocated by the
translation table library code. To minimize the amount of runtime memory
@@ -460,7 +460,7 @@
image, ``MAX_XLAT_TABLES`` must be defined to accommodate the dynamic regions
as well.
-- **#define : MAX\_MMAP\_REGIONS**
+- **#define : MAX_MMAP_REGIONS**
Defines the maximum number of regions that are allocated by the translation
table library code. A region consists of physical base address, virtual base
@@ -473,12 +473,12 @@
enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
the dynamic regions as well.
-- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE**
+- **#define : PLAT_VIRT_ADDR_SPACE_SIZE**
Defines the total size of the virtual address space in bytes. For example,
for a 32 bit virtual address space, this value should be ``(1ULL << 32)``.
-- **#define : PLAT\_PHY\_ADDR\_SPACE\_SIZE**
+- **#define : PLAT_PHY_ADDR_SPACE_SIZE**
Defines the total size of the physical address space in bytes. For example,
for a 32 bit physical address space, this value should be ``(1ULL << 32)``.
@@ -486,22 +486,22 @@
If the platform port uses the IO storage framework, the following constants
must also be defined:
-- **#define : MAX\_IO\_DEVICES**
+- **#define : MAX_IO_DEVICES**
Defines the maximum number of registered IO devices. Attempting to register
more devices than this value using ``io_register_device()`` will fail with
-ENOMEM.
-- **#define : MAX\_IO\_HANDLES**
+- **#define : MAX_IO_HANDLES**
Defines the maximum number of open IO handles. Attempting to open more IO
entities than this value using ``io_open()`` will fail with -ENOMEM.
-- **#define : MAX\_IO\_BLOCK\_DEVICES**
+- **#define : MAX_IO_BLOCK_DEVICES**
Defines the maximum number of registered IO block devices. Attempting to
register more devices this value using ``io_dev_open()`` will fail
- with -ENOMEM. MAX\_IO\_BLOCK\_DEVICES should be less than MAX\_IO\_DEVICES.
+ with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES.
With this macro, multiple block devices could be supported at the same
time.
@@ -511,7 +511,7 @@
``USE_COHERENT_MEM`` build flag. In this case, the framework allocates the
required memory within the the per-cpu data to minimize wastage.
-- **#define : PLAT\_PCPU\_DATA\_SIZE**
+- **#define : PLAT_PCPU_DATA_SIZE**
Defines the memory (in bytes) to be reserved within the per-cpu data
structure for use by the platform layer.
@@ -519,39 +519,39 @@
The following constants are optional. They should be defined when the platform
memory layout implies some image overlaying like in Arm standard platforms.
-- **#define : BL31\_PROGBITS\_LIMIT**
+- **#define : BL31_PROGBITS_LIMIT**
Defines the maximum address in secure RAM that the BL31's progbits sections
can occupy.
-- **#define : TSP\_PROGBITS\_LIMIT**
+- **#define : TSP_PROGBITS_LIMIT**
Defines the maximum address that the TSP's progbits sections can occupy.
If the platform port uses the PL061 GPIO driver, the following constant may
optionally be defined:
-- **PLAT\_PL061\_MAX\_GPIOS**
+- **PLAT_PL061_MAX_GPIOS**
Maximum number of GPIOs required by the platform. This allows control how
much memory is allocated for PL061 GPIO controllers. The default value is
- #. $(eval $(call add\_define,PLAT\_PL061\_MAX\_GPIOS))
+ #. $(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
If the platform port uses the partition driver, the following constant may
optionally be defined:
-- **PLAT\_PARTITION\_MAX\_ENTRIES**
+- **PLAT_PARTITION_MAX_ENTRIES**
Maximum number of partition entries required by the platform. This allows
control how much memory is allocated for partition entries. The default
value is 128.
`For example, define the build flag in platform.mk`_:
- PLAT\_PARTITION\_MAX\_ENTRIES := 12
- $(eval $(call add\_define,PLAT\_PARTITION\_MAX\_ENTRIES))
+ PLAT_PARTITION_MAX_ENTRIES := 12
+ $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
The following constant is optional. It should be defined to override the default
behaviour of the ``assert()`` function (for example, to save memory).
-- **PLAT\_LOG\_LEVEL\_ASSERT**
+- **PLAT_LOG_LEVEL_ASSERT**
If ``PLAT_LOG_LEVEL_ASSERT`` is higher or equal than ``LOG_LEVEL_VERBOSE``,
``assert()`` prints the name of the file, the line number and the asserted
expression. Else if it is higher than ``LOG_LEVEL_INFO``, it prints the file
@@ -562,27 +562,27 @@
If the platform port uses the Activity Monitor Unit, the following constants
may be defined:
-- **PLAT\_AMU\_GROUP1\_COUNTERS\_MASK**
+- **PLAT_AMU_GROUP1_COUNTERS_MASK**
This mask reflects the set of group counters that should be enabled. The
maximum number of group 1 counters supported by AMUv1 is 16 so the mask
can be at most 0xffff. If the platform does not define this mask, no group 1
counters are enabled. If the platform defines this mask, the following
constant needs to also be defined.
-- **PLAT\_AMU\_GROUP1\_NR\_COUNTERS**
+- **PLAT_AMU_GROUP1_NR_COUNTERS**
This value is used to allocate an array to save and restore the counters
specified by ``PLAT_AMU_GROUP1_COUNTERS_MASK`` on CPU suspend.
This value should be equal to the highest bit position set in the
mask, plus 1. The maximum number of group 1 counters in AMUv1 is 16.
-File : plat\_macros.S [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+File : plat_macros.S [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure a file of this name is in the system include path with
the following macro defined. In the Arm development platforms, this file is
found in ``plat/arm/board/<plat_name>/include/plat_macros.S``.
-- **Macro : plat\_crash\_print\_regs**
+- **Macro : plat_crash_print_regs**
This macro allows the crash reporting routine to print relevant platform
registers in case of an unhandled exception in BL31. This aids in debugging
@@ -614,8 +614,8 @@
The following functions need to be implemented by the platform port to enable
reset vector code to perform the above tasks.
-Function : plat\_get\_my\_entrypoint() [mandatory when PROGRAMMABLE\_RESET\_ADDRESS == 0]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -642,8 +642,8 @@
type of reset nor to query the warm reset entrypoint. Therefore, implementing
this function is not required on such platforms.
-Function : plat\_secondary\_cold\_boot\_setup() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -666,8 +666,8 @@
primary CPU will execute the cold boot code. Therefore, implementing this
function is not required on such platforms.
-Function : plat\_is\_my\_cpu\_primary() [mandatory when COLD\_BOOT\_SINGLE\_CPU == 0]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -684,8 +684,8 @@
distinguish between primary and secondary CPUs and implementing this function is
not required.
-Function : platform\_mem\_init() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : platform_mem_init() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -695,8 +695,8 @@
This function is called before any access to data is made by the firmware, in
order to carry out any essential memory initialization.
-Function: plat\_get\_rotpk\_info()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_get_rotpk_info()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -745,8 +745,8 @@
verifying it against the platform value. This flag
must not be used in a deployed production environment.
-Function: plat\_get\_nv\_ctr()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_get_nv_ctr()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -758,13 +758,13 @@
cookie in the first argument may be used to select the counter in case the
platform provides more than one (for example, on platforms that use the default
TBBR CoT, the cookie will correspond to the OID values defined in
-TRUSTED\_FW\_NVCOUNTER\_OID or NON\_TRUSTED\_FW\_NVCOUNTER\_OID).
+TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID).
The function returns 0 on success. Any other value means the counter value could
not be retrieved from the platform.
-Function: plat\_set\_nv\_ctr()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_set_nv_ctr()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -773,14 +773,14 @@
This function is mandatory when Trusted Board Boot is enabled. It sets a new
counter value in the platform. The cookie in the first argument may be used to
-select the counter (as explained in plat\_get\_nv\_ctr()). The second argument is
+select the counter (as explained in plat_get_nv_ctr()). The second argument is
the updated counter value to be written to the NV counter.
The function returns 0 on success. Any other value means the counter value could
not be updated.
-Function: plat\_set\_nv\_ctr2()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function: plat_set_nv_ctr2()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -806,8 +806,8 @@
The following functions are mandatory functions which need to be implemented
by the platform port.
-Function : plat\_my\_core\_pos()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_my_core_pos()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -825,8 +825,8 @@
This function plays a crucial role in the power domain topology framework in
PSCI and details of this can be found in `Power Domain Topology Design`_.
-Function : plat\_core\_pos\_by\_mpidr()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_core_pos_by_mpidr()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -848,8 +848,8 @@
common platform-specific tasks. A platform may choose to override these
definitions.
-Function : plat\_set\_my\_stack()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_set_my_stack()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -863,11 +863,11 @@
constant ``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
-provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
-`plat/common/aarch64/platform\_mp\_stack.S`_
+provided in `plat/common/aarch64/platform_up_stack.S`_ and
+`plat/common/aarch64/platform_mp_stack.S`_
-Function : plat\_get\_my\_stack()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_my_stack()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -881,11 +881,11 @@
constant ``PLATFORM_STACK_SIZE``.
Common implementations of this function for the UP and MP BL images are
-provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
-`plat/common/aarch64/platform\_mp\_stack.S`_
+provided in `plat/common/aarch64/platform_up_stack.S`_ and
+`plat/common/aarch64/platform_mp_stack.S`_
-Function : plat\_report\_exception()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_report_exception()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -905,15 +905,15 @@
For AArch64, this function receives the exception type as its argument.
Possible values for exceptions types are listed in the
-`include/common/bl\_common.h`_ header file. Note that these constants are not
+`include/common/bl_common.h`_ header file. Note that these constants are not
related to any architectural exception code; they are just a TF-A convention.
For AArch32, this function receives the exception mode as its argument.
Possible values for exception modes are listed in the
`include/lib/aarch32/arch.h`_ header file.
-Function : plat\_reset\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_reset_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -929,8 +929,8 @@
the default implementation, refer to the `Firmware Design`_ for general
guidelines.
-Function : plat\_disable\_acp()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_disable_acp()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -944,8 +944,8 @@
scratch registers. It should preserve the value in x18 register as it is used
by the caller to store the return address.
-Function : plat\_error\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_error_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -968,8 +968,8 @@
The default implementation simply spins.
-Function : plat\_panic\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_panic_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -984,8 +984,8 @@
Note: The address from where it was called is stored in x30 (Link Register).
The default implementation simply spins.
-Function : plat\_get\_bl\_image\_load\_info()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_bl_image_load_info()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -996,8 +996,8 @@
populated to load. This function is invoked in BL2 to load the
BL3xx images.
-Function : plat\_get\_next\_bl\_params()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_next_bl_params()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1009,8 +1009,8 @@
function is invoked in BL2 to pass this information to the next BL
image.
-Function : plat\_get\_stack\_protector\_canary()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_stack_protector_canary()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1018,7 +1018,7 @@
Return : u_register_t
This function returns a random value that is used to initialize the canary used
-when the stack protector is enabled with ENABLE\_STACK\_PROTECTOR. A predictable
+when the stack protector is enabled with ENABLE_STACK_PROTECTOR. A predictable
value will weaken the protection as the attacker could easily write the right
value as part of the attack most of the time. Therefore, it should return a
true random number.
@@ -1027,8 +1027,8 @@
a lower address than the stack bases. Failure to do so would allow an attacker
to overwrite the canary as part of the stack buffer overflow attack.
-Function : plat\_flush\_next\_bl\_params()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_flush_next_bl_params()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1039,8 +1039,8 @@
next image. This function is invoked in BL2 to flush this information
to the next BL image.
-Function : plat\_log\_get\_prefix()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_log_get_prefix()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1054,8 +1054,8 @@
the log output. The implementation should be robust to future changes that
increase the number of log levels.
-Function : plat\_get\_mbedtls\_heap()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_mbedtls_heap()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1116,8 +1116,8 @@
The following functions need to be implemented by the platform port to enable
BL1 to perform the above tasks.
-Function : bl1\_early\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_early_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1138,8 +1138,8 @@
the CCI slave interface corresponding to the cluster that includes the
primary CPU.
-Function : bl1\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1154,8 +1154,8 @@
This function helps fulfill requirement 2 above.
-Function : bl1\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1167,15 +1167,15 @@
MMU and data cache have been enabled.
if support for multiple boot sources is required, it initializes the boot
-sequence used by plat\_try\_next\_boot\_source().
+sequence used by plat_try_next_boot_source().
In Arm standard platforms, this function initializes the storage abstraction
layer used to load the next bootloader image.
This function helps fulfill requirement 4 above.
-Function : bl1\_plat\_sec\_mem\_layout() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_sec_mem_layout() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1198,8 +1198,8 @@
This function helps fulfill requirements 4 and 5 above.
-Function : bl1\_plat\_prepare\_exit() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_prepare_exit() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1212,8 +1212,8 @@
control to the next image. It receives the address of the ``entry_point_info_t``
structure passed from BL2. This function runs with MMU disabled.
-Function : bl1\_plat\_set\_ep\_info() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_set_ep_info() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1224,8 +1224,8 @@
The default implementation just returns.
-Function : bl1\_plat\_get\_next\_image\_id() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_get_next_image_id() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1243,8 +1243,8 @@
platforms override this function to detect if firmware update is required, and
if so, return the first image in the firmware update process.
-Function : bl1\_plat\_get\_image\_desc() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_get_image_desc() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1259,8 +1259,8 @@
the firmware update images defined in the Trusted Board Boot Requirements
specification.
-Function : bl1\_plat\_handle\_pre\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_handle_pre_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1271,8 +1271,8 @@
corresponding to ``image_id``. This function is invoked in BL1, both in cold
boot and FWU code path, before loading the image.
-Function : bl1\_plat\_handle\_post\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_handle_post_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1289,8 +1289,8 @@
of ``meminfo_t`` structure is updated in ``arg1`` of the entrypoint
information to BL2.
-Function : bl1\_plat\_fwu\_done() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_fwu_done() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1304,8 +1304,8 @@
The default implementation spins forever.
-Function : bl1\_plat\_mem\_check() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl1_plat_mem_check() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1342,8 +1342,8 @@
The following functions must be implemented by the platform port to enable BL2
to perform the above tasks.
-Function : bl2\_early\_platform\_setup2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_early_platform_setup2() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1367,11 +1367,11 @@
family of functions in BL2.
- Initializes the storage abstraction layer used to load further bootloader
- images. It is necessary to do this early on platforms with a SCP\_BL2 image,
- since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded.
+ images. It is necessary to do this early on platforms with a SCP_BL2 image,
+ since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
-Function : bl2\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1386,8 +1386,8 @@
On Arm standard platforms, this function enables the MMU.
-Function : bl2\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1405,8 +1405,8 @@
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
-Function : bl2\_plat\_handle\_pre\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_handle_pre_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1417,8 +1417,8 @@
for given ``image_id``. This function is currently invoked in BL2 before
loading each image.
-Function : bl2\_plat\_handle\_post\_image\_load() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_handle_post_image_load() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1429,8 +1429,8 @@
for given ``image_id``. This function is currently invoked in BL2 after
loading each image.
-Function : bl2\_plat\_preload\_setup [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_plat_preload_setup [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1439,12 +1439,12 @@
This optional function performs any BL2 platform initialization
required before image loading, that is not done later in
-bl2\_platform\_setup(). Specifically, if support for multiple
+bl2_platform_setup(). Specifically, if support for multiple
boot sources is required, it initializes the boot sequence used by
-plat\_try\_next\_boot\_source().
+plat_try_next_boot_source().
-Function : plat\_try\_next\_boot\_source() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_try_next_boot_source() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1468,14 +1468,14 @@
Design`_ for more information.
All mandatory functions of BL2 must be implemented, except the functions
-bl2\_early\_platform\_setup and bl2\_el3\_plat\_arch\_setup, because
-their work is done now by bl2\_el3\_early\_platform\_setup and
-bl2\_el3\_plat\_arch\_setup. These functions should generally implement
-the bl1\_plat\_xxx() and bl2\_plat\_xxx() functionality combined.
+bl2_early_platform_setup and bl2_el3_plat_arch_setup, because
+their work is done now by bl2_el3_early_platform_setup and
+bl2_el3_plat_arch_setup. These functions should generally implement
+the bl1_plat_xxx() and bl2_plat_xxx() functionality combined.
-Function : bl2\_el3\_early\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_el3_early_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1492,13 +1492,13 @@
family of functions in BL2.
- Initializes the storage abstraction layer used to load further bootloader
- images. It is necessary to do this early on platforms with a SCP\_BL2 image,
- since the later ``bl2_platform_setup`` must be done after SCP\_BL2 is loaded.
+ images. It is necessary to do this early on platforms with a SCP_BL2 image,
+ since the later ``bl2_platform_setup`` must be done after SCP_BL2 is loaded.
- Initializes the private variables that define the memory layout used.
-Function : bl2\_el3\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_el3_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1513,8 +1513,8 @@
On Arm standard platforms, this function enables the MMU.
-Function : bl2\_el3\_plat\_prepare\_exit() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2_el3_plat_prepare_exit() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1533,10 +1533,10 @@
process and is executed only by the primary CPU. BL1 passes control to BL2U at
``BL2U_BASE``. BL2U executes in Secure-EL1 and is responsible for:
-#. (Optional) Transferring the optional SCP\_BL2U binary image from AP secure
- memory to SCP RAM. BL2U uses the SCP\_BL2U ``image_info`` passed by BL1.
- ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP\_BL2U
- should be copied from. Subsequent handling of the SCP\_BL2U image is
+#. (Optional) Transferring the optional SCP_BL2U binary image from AP secure
+ memory to SCP RAM. BL2U uses the SCP_BL2U ``image_info`` passed by BL1.
+ ``SCP_BL2U_BASE`` defines the address in AP secure memory where SCP_BL2U
+ should be copied from. Subsequent handling of the SCP_BL2U image is
implemented by the platform specific ``bl2u_plat_handle_scp_bl2u()`` function.
If ``SCP_BL2U_BASE`` is not defined then this step is not performed.
@@ -1547,8 +1547,8 @@
The following functions must be implemented by the platform port to enable
BL2U to perform the tasks mentioned above.
-Function : bl2u\_early\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_early_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1563,11 +1563,11 @@
private storage as the original memory may be subsequently overwritten by BL2U.
On Arm CSS platforms ``plat_info`` is interpreted as an ``image_info_t`` structure,
-to extract SCP\_BL2U image information, which is then copied into a private
+to extract SCP_BL2U image information, which is then copied into a private
variable.
-Function : bl2u\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1581,8 +1581,8 @@
that varies across platforms, for example enabling the MMU (since the memory
map differs across platforms).
-Function : bl2u\_platform\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_platform_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1600,8 +1600,8 @@
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
-Function : bl2u\_plat\_handle\_scp\_bl2u() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl2u_plat_handle_scp_bl2u() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1614,7 +1614,7 @@
Application Processor (AP) for BL2U execution to continue.
This function returns 0 on success, a negative error code otherwise.
-This function is included if SCP\_BL2U\_BASE is defined.
+This function is included if SCP_BL2U_BASE is defined.
Boot Loader Stage 3-1 (BL31)
----------------------------
@@ -1650,8 +1650,8 @@
The following functions must be implemented by the platform port to enable BL31
to perform the above tasks.
-Function : bl31\_early\_platform\_setup2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_early_platform_setup2() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1684,8 +1684,8 @@
CCI slave interface corresponding to the cluster that includes the primary
CPU.
-Function : bl31\_plat\_arch\_setup() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_plat_arch_setup() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1700,7 +1700,7 @@
On Arm standard platforms, this function enables the MMU.
-Function : bl31\_platform\_setup() [mandatory]
+Function : bl31_platform_setup() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1742,8 +1742,8 @@
In particular, initialise the locks that prevent concurrent accesses to the
power controller device.
-Function : bl31\_plat\_runtime\_setup() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_plat_runtime_setup() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1755,8 +1755,8 @@
implementation of this function will invoke ``console_switch_state()`` to switch
console output to consoles marked for use in the ``runtime`` state.
-Function : bl31\_plat\_get\_next\_image\_ep\_info() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : bl31_plat_get_next_image_ep_info() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1792,8 +1792,8 @@
On DynamIQ systems, this function must not use stack while enabling MMU, which
is how the function in xlat table library version 2 is implemented.
-Function : plat\_get\_syscnt\_freq2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_syscnt_freq2() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1806,8 +1806,8 @@
of the system counter, which is retrieved from the first entry in the frequency
modes table.
-#define : PLAT\_PERCPU\_BAKERY\_LOCK\_SIZE [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+#define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
When ``USE_COHERENT_MEM = 0``, this constant defines the total memory (in
bytes) aligned to the cache line boundary that should be allocated per-cpu to
@@ -1929,8 +1929,8 @@
The following functions form part of platform port of PSCI functionality.
-Function : plat\_psci\_stat\_accounting\_start() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_psci_stat_accounting_start() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1947,8 +1947,8 @@
statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
default implementation will use PMF to capture timestamps.
-Function : plat\_psci\_stat\_accounting\_stop() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_psci_stat_accounting_stop() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1965,8 +1965,8 @@
statistics could be tracked in software using PMF. If ``ENABLE_PMF`` is set, the
default implementation will use PMF to capture timestamps.
-Function : plat\_psci\_stat\_get\_residency() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_psci_stat_get_residency() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1985,8 +1985,8 @@
CPU in the power domain to suspend and may be needed to calculate the residency
for that power domain.
-Function : plat\_get\_target\_pwr\_state() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_target_pwr_state() [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2010,8 +2010,8 @@
coordinated target local power state for a power domain will be the minimum
of the requested local power state values.
-Function : plat\_get\_power\_domain\_tree\_desc() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_get_power_domain_tree_desc() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2023,13 +2023,13 @@
described in `Power Domain Topology Design`_. The BL31 PSCI initialization code
requires this array to be described by the platform, either statically or
dynamically, to initialize the power domain topology tree. In case the array
-is populated dynamically, then plat\_core\_pos\_by\_mpidr() and
-plat\_my\_core\_pos() should also be implemented suitably so that the topology
+is populated dynamically, then plat_core_pos_by_mpidr() and
+plat_my_core_pos() should also be implemented suitably so that the topology
tree description matches the CPU indices returned by these APIs. These APIs
together form the platform interface for the PSCI topology framework.
-Function : plat\_setup\_psci\_ops() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_setup_psci_ops() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2048,15 +2048,15 @@
A description of each member of this structure is given below. Please refer to
the Arm FVP specific implementation of these handlers in
-`plat/arm/board/fvp/fvp\_pm.c`_ as an example. For each PSCI function that the
+`plat/arm/board/fvp/fvp_pm.c`_ as an example. For each PSCI function that the
platform wants to support, the associated operation or operations in this
structure must be provided and implemented (Refer section 4 of
`Firmware Design`_ for the PSCI API supported in TF-A). To disable a PSCI
function in a platform port, the operation should be removed from this
structure instead of providing an empty implementation.
-plat\_psci\_ops.cpu\_standby()
-..............................
+plat_psci_ops.cpu_standby()
+...........................
Perform the platform-specific actions to enter the standby state for a cpu
indicated by the passed argument. This provides a fast path for CPU standby
@@ -2068,15 +2068,15 @@
issuing a wfi instruction) and ensure that it can be woken up from that
state by a normal interrupt. The generic code expects the handler to succeed.
-plat\_psci\_ops.pwr\_domain\_on()
-.................................
+plat_psci_ops.pwr_domain_on()
+.............................
Perform the platform specific actions to power on a CPU, specified
by the ``MPIDR`` (first argument). The generic code expects the platform to
-return PSCI\_E\_SUCCESS on success or PSCI\_E\_INTERN\_FAIL for any failure.
+return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure.
-plat\_psci\_ops.pwr\_domain\_off()
-..................................
+plat_psci_ops.pwr_domain_off()
+..............................
Perform the platform specific actions to prepare to power off the calling CPU
and its higher parent power domain levels as indicated by the ``target_state``
@@ -2092,8 +2092,8 @@
for the higher power domain levels depending on the result of state
coordination. The generic code expects the handler to succeed.
-plat\_psci\_ops.pwr\_domain\_suspend\_pwrdown\_early() [optional]
-.................................................................
+plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]
+...........................................................
This optional function may be used as a performance optimization to replace
or complement pwr_domain_suspend() on some platforms. Its calling semantics
@@ -2109,8 +2109,8 @@
= 1, data caches remain enabled throughout, and so there is no advantage to
moving platform specific actions to this function.
-plat\_psci\_ops.pwr\_domain\_suspend()
-......................................
+plat_psci_ops.pwr_domain_suspend()
+..................................
Perform the platform specific actions to prepare to suspend the calling
CPU and its higher parent power domain levels as indicated by the
@@ -2150,8 +2150,8 @@
data, for example in DRAM. The Distributor can then be powered down using an
implementation-defined sequence.
-plat\_psci\_ops.pwr\_domain\_pwr\_down\_wfi()
-.............................................
+plat_psci_ops.pwr_domain_pwr_down_wfi()
+.......................................
This is an optional function and, if implemented, is expected to perform
platform specific actions including the ``wfi`` invocation which allows the
@@ -2167,8 +2167,8 @@
If this function is not implemented by the platform, PSCI generic
implementation invokes ``psci_power_down_wfi()`` for power down.
-plat\_psci\_ops.pwr\_domain\_on\_finish()
-.........................................
+plat_psci_ops.pwr_domain_on_finish()
+....................................
This function is called by the PSCI implementation after the calling CPU is
powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
@@ -2181,8 +2181,8 @@
above the CPU might require initialization due to having previously been in
low power states. The generic code expects the handler to succeed.
-plat\_psci\_ops.pwr\_domain\_suspend\_finish()
-..............................................
+plat_psci_ops.pwr_domain_suspend_finish()
+.........................................
This function is called by the PSCI implementation after the calling CPU is
powered on and released from reset in response to an asynchronous wakeup
@@ -2199,41 +2199,41 @@
suspend, their context must be restored in this function in the reverse order
to how they were saved during suspend sequence.
-plat\_psci\_ops.system\_off()
-.............................
+plat_psci_ops.system_off()
+..........................
This function is called by PSCI implementation in response to a ``SYSTEM_OFF``
call. It performs the platform-specific system poweroff sequence after
notifying the Secure Payload Dispatcher.
-plat\_psci\_ops.system\_reset()
-...............................
+plat_psci_ops.system_reset()
+............................
This function is called by PSCI implementation in response to a ``SYSTEM_RESET``
call. It performs the platform-specific system reset sequence after
notifying the Secure Payload Dispatcher.
-plat\_psci\_ops.validate\_power\_state()
-........................................
+plat_psci_ops.validate_power_state()
+....................................
This function is called by the PSCI implementation during the ``CPU_SUSPEND``
call to validate the ``power_state`` parameter of the PSCI API and if valid,
populate it in ``req_state`` (second argument) array as power domain level
specific local states. If the ``power_state`` is invalid, the platform must
-return PSCI\_E\_INVALID\_PARAMS as error, which is propagated back to the
+return PSCI_E_INVALID_PARAMS as error, which is propagated back to the
normal world PSCI client.
-plat\_psci\_ops.validate\_ns\_entrypoint()
-..........................................
+plat_psci_ops.validate_ns_entrypoint()
+......................................
This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the non-secure ``entry_point``
parameter passed by the normal world. If the ``entry_point`` is invalid,
-the platform must return PSCI\_E\_INVALID\_ADDRESS as error, which is
+the platform must return PSCI_E_INVALID_ADDRESS as error, which is
propagated back to the normal world PSCI client.
-plat\_psci\_ops.get\_sys\_suspend\_power\_state()
-.................................................
+plat_psci_ops.get_sys_suspend_power_state()
+...........................................
This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
call to get the ``req_state`` parameter from platform which encodes the power
@@ -2242,8 +2242,8 @@
``pwr_domain_suspend()`` will be invoked with the coordinated target state to
enter system suspend.
-plat\_psci\_ops.get\_pwr\_lvl\_state\_idx()
-...........................................
+plat_psci_ops.get_pwr_lvl_state_idx()
+.....................................
This is an optional function and, if implemented, is invoked by the PSCI
implementation to convert the ``local_state`` (first argument) at a specified
@@ -2253,8 +2253,8 @@
``PLAT_MAX_PWR_LVL_STATES`` is greater than 2, and needs to account for these
local power states.
-plat\_psci\_ops.translate\_power\_state\_by\_mpidr()
-....................................................
+plat_psci_ops.translate_power_state_by_mpidr()
+..............................................
This is an optional function and, if implemented, verifies the ``power_state``
(second argument) parameter of the PSCI API corresponding to a target power
@@ -2265,16 +2265,16 @@
is similar to the ``validate_power_state`` function described above and is
envisaged to be used in case the validity of ``power_state`` depend on the
targeted power domain. If the ``power_state`` is invalid for the targeted power
-domain, the platform must return PSCI\_E\_INVALID\_PARAMS as error. If this
+domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this
function is not implemented, then the generic implementation relies on
``validate_power_state`` function to translate the ``power_state``.
This function can also be used in case the platform wants to support local
-power state encoding for ``power_state`` parameter of PSCI\_STAT\_COUNT/RESIDENCY
+power state encoding for ``power_state`` parameter of PSCI_STAT_COUNT/RESIDENCY
APIs as described in Section 5.18 of `PSCI`_.
-plat\_psci\_ops.get\_node\_hw\_state()
-......................................
+plat_psci_ops.get_node_hw_state()
+.................................
This is an optional function. If implemented this function is intended to return
the power state of a node (identified by the first parameter, the ``MPIDR``) in
@@ -2288,8 +2288,8 @@
Implementations are not expected to handle ``power_levels`` greater than
``PLAT_MAX_PWR_LVL``.
-plat\_psci\_ops.system\_reset2()
-................................
+plat_psci_ops.system_reset2()
+.............................
This is an optional function. If implemented this function is
called during the ``SYSTEM_RESET2`` call to perform a reset
@@ -2301,8 +2301,8 @@
and vendor reset can return other PSCI error codes as defined
in `PSCI`_. On success this function will not return.
-plat\_psci\_ops.write\_mem\_protect()
-....................................
+plat_psci_ops.write_mem_protect()
+.................................
This is an optional function. If implemented it enables or disables the
``MEM_PROTECT`` functionality based on the value of ``val``.
@@ -2310,16 +2310,16 @@
disables it. Upon encountering failures it must return a negative value
and on success it must return 0.
-plat\_psci\_ops.read\_mem\_protect()
-.....................................
+plat_psci_ops.read_mem_protect()
+................................
This is an optional function. If implemented it returns the current
state of ``MEM_PROTECT`` via the ``val`` parameter. Upon encountering
failures it must return a negative value and on success it must
return 0.
-plat\_psci\_ops.mem\_protect\_chk()
-...................................
+plat_psci_ops.mem_protect_chk()
+...............................
This is an optional function. If implemented it checks if a memory
region defined by a base address ``base`` and with a size of ``length``
@@ -2348,8 +2348,8 @@
.. __: platform-interrupt-controller-API.rst
-Function : plat\_interrupt\_type\_to\_line() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_interrupt_type_to_line() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2384,8 +2384,8 @@
- The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2
context.
-Function : plat\_ic\_get\_pending\_interrupt\_type() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_get_pending_interrupt_type() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2417,8 +2417,8 @@
#. id = ``GIC_SPURIOUS_INTERRUPT`` (1023) is reported as an invalid interrupt type.
#. All other interrupt id's are reported as EL3 interrupt.
-Function : plat\_ic\_get\_pending\_interrupt\_id() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_get_pending_interrupt_id() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2456,11 +2456,11 @@
When the API invoked from S-EL1 for GICv3 systems, the id read from system
register ``ICC_HPPIR1_EL1``, *Highest Priority Pending group 1 Interrupt
-Register*, is returned if is not equal to GIC\_SPURIOUS\_INTERRUPT (1023) else
+Register*, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else
``INTR_ID_UNAVAILABLE`` is returned.
-Function : plat\_ic\_acknowledge\_interrupt() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_acknowledge_interrupt() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2491,8 +2491,8 @@
The TSP uses this API to start processing of the secure physical timer
interrupt.
-Function : plat\_ic\_end\_of\_interrupt() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_end_of_interrupt() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2513,8 +2513,8 @@
The TSP uses this API to finish processing of the secure physical timer
interrupt.
-Function : plat\_ic\_get\_interrupt\_type() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_ic_get_interrupt_type() [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2564,8 +2564,8 @@
that are designed to be used by these functions. See Arm platforms (like juno)
for an example of this.
-Function : plat\_crash\_console\_init [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_crash_console_init [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2576,8 +2576,8 @@
console. It must only use the general purpose registers x0 through x7 to do the
initialization and returns 1 on success.
-Function : plat\_crash\_console\_putc [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_crash_console_putc [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2589,8 +2589,8 @@
x2 to do its work. The parameter and the return value are in general purpose
register x0.
-Function : plat\_crash\_console\_flush [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Function : plat_crash_console_flush [mandatory]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -2710,7 +2710,7 @@
need to be defined in the platform makefile which will get included by the
build system.
-- **NEED\_BL33**
+- **NEED_BL33**
By default, this flag is defined ``yes`` by the build system and ``BL33``
build option should be supplied as a build option. The platform has the
option of excluding the BL33 image in the ``fip`` image by defining this flag
@@ -2733,8 +2733,8 @@
from `FreeBSD`_, others have been written specifically for TF-A as well. The
files can be found in ``include/lib/libc`` and ``lib/libc``.
-SCC can be found in `http://www.simple-cc.org/`_. A copy of the `FreeBSD`_
-sources can be obtained from `http://github.com/freebsd/freebsd`_.
+SCC can be found in http://www.simple-cc.org/. A copy of the `FreeBSD`_ sources
+can be obtained from http://github.com/freebsd/freebsd.
Storage abstraction layer
-------------------------
@@ -2770,7 +2770,7 @@
The current implementation only allows for known images to be loaded by the
firmware. These images are specified by using their identifiers, as defined in
-[include/plat/common/platform\_def.h] (or a separate header file included from
+[include/plat/common/platform_def.h] (or a separate header file included from
there). The platform layer (``plat_get_image_source()``) then returns a reference
to a device and a driver-specific ``spec`` which will be understood by the driver
to allow access to the image data.
@@ -2791,19 +2791,19 @@
*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
.. _include/plat/common/platform.h: ../include/plat/common/platform.h
-.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D
+.. _include/plat/arm/common/plat_arm.h: ../include/plat/arm/common/plat_arm.h%5D
.. _User Guide: user-guide.rst
-.. _include/plat/common/common\_def.h: ../include/plat/common/common_def.h
-.. _include/plat/arm/common/arm\_def.h: ../include/plat/arm/common/arm_def.h
-.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S
-.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S
+.. _include/plat/common/common_def.h: ../include/plat/common/common_def.h
+.. _include/plat/arm/common/arm_def.h: ../include/plat/arm/common/arm_def.h
+.. _plat/common/aarch64/platform_mp_stack.S: ../plat/common/aarch64/platform_mp_stack.S
+.. _plat/common/aarch64/platform_up_stack.S: ../plat/common/aarch64/platform_up_stack.S
.. _For example, define the build flag in platform.mk: PLAT_PL061_MAX_GPIOS%20:=%20160
.. _Power Domain Topology Design: psci-pd-tree.rst
-.. _include/common/bl\_common.h: ../include/common/bl_common.h
+.. _include/common/bl_common.h: ../include/common/bl_common.h
.. _include/lib/aarch32/arch.h: ../include/lib/aarch32/arch.h
.. _Firmware Design: firmware-design.rst
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
-.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
+.. _plat/arm/board/fvp/fvp_pm.c: ../plat/arm/board/fvp/fvp_pm.c
.. _Platform compatibility policy: ./platform-compatibility-policy.rst
.. _IMF Design Guide: interrupt-framework-design.rst
.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
diff --git a/docs/psci-lib-integration-guide.rst b/docs/psci-lib-integration-guide.rst
index 1be2240..555d347 100644
--- a/docs/psci-lib-integration-guide.rst
+++ b/docs/psci-lib-integration-guide.rst
@@ -140,7 +140,7 @@
void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info);
-The CPU context data 'cpu\_context\_t' is programmed to the registers differently
+The CPU context data 'cpu_context_t' is programmed to the registers differently
when PSCI is integrated with an AArch32 EL3 Runtime Software compared to
when the PSCI is integrated with an AArch64 EL3 Runtime Software (BL31). For
example, in the case of AArch64, there is no need to retrieve ``cpu_context_t``
@@ -159,7 +159,7 @@
PSCI library needs the flexibility to access both secure and non-secure
copies of banked registers. Hence it needs to be invoked in Monitor mode
-for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR\_EL3
+for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
(in AArch64) must be set to 0. Additional requirements for the PSCI library
interfaces are:
@@ -175,8 +175,8 @@
Further requirements for each interface can be found in the interface
description.
-Interface : psci\_setup()
-~~~~~~~~~~~~~~~~~~~~~~~~~
+Interface : psci_setup()
+~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -212,8 +212,8 @@
`CPU Context management API`_) for all the CPUs in the
platform
-Interface : psci\_prepare\_next\_non\_secure\_ctx()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Interface : psci_prepare_next_non_secure_ctx()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -225,11 +225,11 @@
context. The non-secure world entrypoint information ``next_image_info`` (first
argument) will be used to determine the non-secure context. After this function
returns, the EL3 Runtime Software must retrieve the ``cpu_context_t`` (using
-cm\_get\_context()) for the current CPU and program the registers prior to exit
+cm_get_context()) for the current CPU and program the registers prior to exit
to the non-secure world.
-Interface : psci\_register\_spd\_pm\_hook()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Interface : psci_register_spd_pm_hook()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -244,8 +244,8 @@
need to be called by the primary CPU during the cold boot sequence after
``psci_setup()`` has completed.
-Interface : psci\_smc\_handler()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Interface : psci_smc_handler()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -270,8 +270,8 @@
caller if PSCI API causes power down of the CPU. In this case, when the CPU
wakes up, it will start execution from the warm reset address.
-Interface : psci\_warmboot\_entrypoint()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Interface : psci_warmboot_entrypoint()
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -302,7 +302,7 @@
---------------------------------
The PSCI Library includes supporting frameworks like context management,
-cpu operations (cpu\_ops) and per-cpu data framework. Other helper library
+cpu operations (cpu_ops) and per-cpu data framework. Other helper library
functions like bakery locks and spin locks are also included in the library.
The dependencies which must be fulfilled by the EL3 Runtime Software
for integration with PSCI library are described below.
@@ -323,7 +323,7 @@
These must be implemented as described in ISO C Standard.
-**Function : flush\_dcache\_range()**
+**Function : flush_dcache_range()**
::
@@ -333,7 +333,7 @@
This function cleans and invalidates (flushes) the data cache for memory
at address ``addr`` (first argument) address and of size ``size`` (second argument).
-**Function : inv\_dcache\_range()**
+**Function : inv_dcache_range()**
::
@@ -343,7 +343,7 @@
This function invalidates (flushes) the data cache for memory at address
``addr`` (first argument) address and of size ``size`` (second argument).
-**Function : do\_panic()**
+**Function : do_panic()**
::
@@ -363,7 +363,7 @@
choose a more optimal implementation (like dedicating the secure TPIDRPRW
system register (in AArch32) for storing these pointers).
-**Function : cm\_set\_context\_by\_index()**
+**Function : cm_set_context_by_index()**
::
@@ -384,7 +384,7 @@
For example, SP-MIN stores the pointers in the array ``sp_min_cpu_ctx_ptr``
declared in ``sp_min_main.c``.
-**Function : cm\_get\_context()**
+**Function : cm_get_context()**
::
@@ -398,7 +398,7 @@
will always be non-secure when called by PSCI library and this argument
is retained for compatibility with BL31.
-**Function : cm\_get\_context\_by\_index()**
+**Function : cm_get_context_by_index()**
::
@@ -423,25 +423,25 @@
The mandatory platform APIs are:
-- plat\_my\_core\_pos
-- plat\_core\_pos\_by\_mpidr
-- plat\_get\_syscnt\_freq2
-- plat\_get\_power\_domain\_tree\_desc
-- plat\_setup\_psci\_ops
-- plat\_reset\_handler
-- plat\_panic\_handler
-- plat\_get\_my\_stack
+- plat_my_core_pos
+- plat_core_pos_by_mpidr
+- plat_get_syscnt_freq2
+- plat_get_power_domain_tree_desc
+- plat_setup_psci_ops
+- plat_reset_handler
+- plat_panic_handler
+- plat_get_my_stack
The mandatory platform macros are:
-- PLATFORM\_CORE\_COUNT
-- PLAT\_MAX\_PWR\_LVL
-- PLAT\_NUM\_PWR\_DOMAINS
-- CACHE\_WRITEBACK\_GRANULE
-- PLAT\_MAX\_OFF\_STATE
-- PLAT\_MAX\_RET\_STATE
-- PLAT\_MAX\_PWR\_LVL\_STATES (optional)
-- PLAT\_PCPU\_DATA\_SIZE (optional)
+- PLATFORM_CORE_COUNT
+- PLAT_MAX_PWR_LVL
+- PLAT_NUM_PWR_DOMAINS
+- CACHE_WRITEBACK_GRANULE
+- PLAT_MAX_OFF_STATE
+- PLAT_MAX_RET_STATE
+- PLAT_MAX_PWR_LVL_STATES (optional)
+- PLAT_PCPU_DATA_SIZE (optional)
The details of these APIs/macros can be found in `Porting Guide`_.
@@ -486,50 +486,50 @@
A brief description of each callback is given below:
-- svc\_on, svc\_off, svc\_on\_finish
+- svc_on, svc_off, svc_on_finish
- The ``svc_on``, ``svc_off`` callbacks are called during PSCI\_CPU\_ON,
- PSCI\_CPU\_OFF APIs respectively. The ``svc_on_finish`` is called when the
- target CPU of PSCI\_CPU\_ON API powers up and executes the
+ The ``svc_on``, ``svc_off`` callbacks are called during PSCI_CPU_ON,
+ PSCI_CPU_OFF APIs respectively. The ``svc_on_finish`` is called when the
+ target CPU of PSCI_CPU_ON API powers up and executes the
``psci_warmboot_entrypoint()`` PSCI library interface.
-- svc\_suspend, svc\_suspend\_finish
+- svc_suspend, svc_suspend_finish
The ``svc_suspend`` callback is called during power down bu either
- PSCI\_SUSPEND or PSCI\_SYSTEM\_SUSPEND APIs. The ``svc_suspend_finish`` is
+ PSCI_SUSPEND or PSCI_SYSTEM_SUSPEND APIs. The ``svc_suspend_finish`` is
called when the CPU wakes up from suspend and executes the
``psci_warmboot_entrypoint()`` PSCI library interface. The ``max_off_pwrlvl``
(first parameter) denotes the highest power domain level being powered down
to or woken up from suspend.
-- svc\_system\_off, svc\_system\_reset
+- svc_system_off, svc_system_reset
- These callbacks are called during PSCI\_SYSTEM\_OFF and PSCI\_SYSTEM\_RESET
+ These callbacks are called during PSCI_SYSTEM_OFF and PSCI_SYSTEM_RESET
PSCI APIs respectively.
-- svc\_migrate\_info
+- svc_migrate_info
- This callback is called in response to PSCI\_MIGRATE\_INFO\_TYPE or
- PSCI\_MIGRATE\_INFO\_UP\_CPU APIs. The return value of this callback must
- correspond to the return value of PSCI\_MIGRATE\_INFO\_TYPE API as described
+ This callback is called in response to PSCI_MIGRATE_INFO_TYPE or
+ PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must
+ correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described
in `PSCI spec`_. If the secure payload is a Uniprocessor (UP)
implementation, then it must update the mpidr of the CPU it is resident in
via ``resident_cpu`` (first argument). The updates to ``resident_cpu`` is
ignored if the secure payload is a multiprocessor (MP) implementation.
-- svc\_migrate
+- svc_migrate
This callback is only relevant if the secure payload in EL3 Runtime
Software is a Uniprocessor (UP) implementation and supports migration from
the current CPU ``from_cpu`` (first argument) to another CPU ``to_cpu``
- (second argument). This callback is called in response to PSCI\_MIGRATE
+ (second argument). This callback is called in response to PSCI_MIGRATE
API. This callback is never called if the secure payload is a
Multiprocessor (MP) implementation.
CPU operations
~~~~~~~~~~~~~~
-The CPU operations (cpu\_ops) framework implement power down sequence specific
+The CPU operations (cpu_ops) framework implement power down sequence specific
to the CPU and the details of which can be found in the
``CPU specific operations framework`` section of `Firmware Design`_. The TF-A
tree implements the ``cpu_ops`` for various supported CPUs and the EL3 Runtime
diff --git a/docs/rt-svc-writers-guide.rst b/docs/rt-svc-writers-guide.rst
index cec2ae7..4d4066c 100644
--- a/docs/rt-svc-writers-guide.rst
+++ b/docs/rt-svc-writers-guide.rst
@@ -91,7 +91,7 @@
each owning entity can place the implementation of its runtime service. The
`PSCI`_ implementation is located here in the `lib/psci`_ directory.
-Runtime service sources will need to include the `runtime\_svc.h`_ header file.
+Runtime service sources will need to include the `runtime_svc.h`_ header file.
Registering a runtime service
-----------------------------
@@ -140,7 +140,7 @@
#. The ``_type`` is one of ``SMC_TYPE_FAST`` or ``SMC_TYPE_YIELD``
#. ``_setup`` and ``_smch`` routines have been specified
-`std\_svc\_setup.c`_ provides an example of registering a runtime service:
+`std_svc_setup.c`_ provides an example of registering a runtime service:
.. code:: c
@@ -310,6 +310,6 @@
.. _Firmware Design: ./firmware-design.rst
.. _services: ../services
.. _lib/psci: ../lib/psci
-.. _runtime\_svc.h: ../include/common/runtime_svc.h
+.. _runtime_svc.h: ../include/common/runtime_svc.h
.. _smccc.h: ../include/lib/smccc.h
-.. _std\_svc\_setup.c: ../services/std_svc/std_svc_setup.c
+.. _std_svc_setup.c: ../services/std_svc/std_svc_setup.c
diff --git a/docs/trusted-board-boot.rst b/docs/trusted-board-boot.rst
index 5ab32fe..33005e3 100644
--- a/docs/trusted-board-boot.rst
+++ b/docs/trusted-board-boot.rst
@@ -59,7 +59,7 @@
- **Trusted world key**
The private part is used to sign the key certificates corresponding to the
- secure world images (SCP\_BL2, BL31 and BL32). The public part is stored in
+ secure world images (SCP_BL2, BL31 and BL32). The public part is stored in
one of the extension fields in the trusted world certificate.
- **Non-trusted world key**
@@ -70,7 +70,7 @@
- **BL3-X keys**
- For each of SCP\_BL2, BL31, BL32 and BL33, the private part is used to
+ For each of SCP_BL2, BL31, BL32 and BL33, the private part is used to
sign the content certificate for the BL3-X image. The public part is stored
in one of the extension fields in the corresponding key certificate.
@@ -78,7 +78,7 @@
- BL1
- BL2
-- SCP\_BL2 (optional)
+- SCP_BL2 (optional)
- BL31
- BL33
- BL32 (optional)
@@ -96,14 +96,14 @@
public part of the trusted world key and the public part of the non-trusted
world key.
-- **SCP\_BL2 key certificate**
+- **SCP_BL2 key certificate**
It is self-signed with the trusted world key. It contains the public part of
- the SCP\_BL2 key.
+ the SCP_BL2 key.
-- **SCP\_BL2 content certificate**
+- **SCP_BL2 content certificate**
- It is self-signed with the SCP\_BL2 key. It contains a hash of the SCP\_BL2
+ It is self-signed with the SCP_BL2 key. It contains a hash of the SCP_BL2
image.
- **BL31 key certificate**
@@ -133,8 +133,8 @@
It is self-signed with the BL33 key. It contains a hash of the BL33 image.
-The SCP\_BL2 and BL32 certificates are optional, but they must be present if the
-corresponding SCP\_BL2 or BL32 images are present.
+The SCP_BL2 and BL32 certificates are optional, but they must be present if the
+corresponding SCP_BL2 or BL32 images are present.
Trusted Board Boot Sequence
---------------------------
@@ -160,8 +160,8 @@
registers. If the comparison succeeds, BL2 reads and saves the trusted and
non-trusted world public keys from the verified certificate.
-The next two steps are executed for each of the SCP\_BL2, BL31 & BL32 images.
-The steps for the optional SCP\_BL2 and BL32 images are skipped if these images
+The next two steps are executed for each of the SCP_BL2, BL31 & BL32 images.
+The steps for the optional SCP_BL2 and BL32 images are skipped if these images
are not present.
- BL2 loads and verifies the BL3x key certificate. The certificate signature
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 320bb1d..386c28e 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -197,7 +197,7 @@
- (AArch32 only) Currently only ``PLAT=fvp`` is supported.
- (AArch32 only) ``AARCH32_SP`` is the AArch32 EL3 Runtime Software and it
- corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp\_min, is
+ corresponds to the BL32 image. A minimal ``AARCH32_SP``, sp_min, is
provided by TF-A to demonstrate how PSCI Library can be integrated with
an AArch32 EL3 Runtime Software. Some AArch32 EL3 Runtime Software may
include other runtime services, for example Trusted OS services. A guide
@@ -324,7 +324,7 @@
where applicable). Defaults to a string that contains the time and date of
the compilation.
-- ``BUILD_STRING``: Input string for VERSION\_STRING, which allows the TF-A
+- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A
build to be uniquely identified. Defaults to the current git commit id.
- ``CFLAGS``: Extra user options appended on the compiler's command line in
@@ -479,12 +479,12 @@
- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create``
tool to create certificates as per the Chain of Trust described in
`Trusted Board Boot`_. The build system then calls ``fiptool`` to
- include the certificates in the FIP and FWU\_FIP. Default value is '0'.
+ include the certificates in the FIP and FWU_FIP. Default value is '0'.
Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support
for the Trusted Board Boot feature in the BL1 and BL2 images, to generate
the corresponding certificates, and to include those certificates in the
- FIP and FWU\_FIP.
+ FIP and FWU_FIP.
Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2
images will not include support for Trusted Board Boot. The FIP will still
@@ -492,7 +492,7 @@
Chain of Trust on the host machine through other mechanisms.
Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2
- images will include support for Trusted Board Boot, but the FIP and FWU\_FIP
+ images will include support for Trusted Board Boot, but the FIP and FWU_FIP
will not include the corresponding certificates, causing a boot failure.
- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have
@@ -566,7 +566,7 @@
specifies the file that contains the Non-Trusted World private key in PEM
format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
-- ``NS_BL2U``: Path to NS\_BL2U image in the host file system. This image is
+- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is
optional. It is only needed if the platform makefile specifies that it
is required in order to build the ``fwu_fip`` target.
@@ -575,6 +575,10 @@
1 (do save and restore). 0 is the default. An SPD may set this to 1 if it
wants the timer registers to be saved and restored.
+- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc
+ for the BL image. It can be either 0 (include) or 1 (remove). The default
+ value is 0.
+
- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that
the underlying hardware is not a full PL011 UART but a minimally compliant
generic UART, which is a subset of the PL011. The driver will not access
@@ -607,7 +611,7 @@
to use the extended format. The default value of this flag is 0, which
means by default the original power-state format is used by the PSCI
implementation. This flag should be specified by the platform makefile
- and it governs the return value of PSCI\_FEATURES API for CPU\_SUSPEND
+ and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND
smc function id. When this option is enabled on Arm platforms, the
option ``ARM_RECOM_STATE_ID_ENC`` needs to be set to 1 as well.
@@ -625,10 +629,10 @@
entrypoint) or 1 (CPU reset to BL31 entrypoint).
The default value is 0.
-- ``RESET_TO_SP_MIN``: SP\_MIN is the minimal AArch32 Secure Payload provided
- in TF-A. This flag configures SP\_MIN entrypoint as the CPU reset vector
+- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided
+ in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector
instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
- entrypoint) or 1 (CPU reset to SP\_MIN entrypoint). The default value is 0.
+ entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
file that contains the ROT private key in PEM format. If ``SAVE_KEYS=1``, this
@@ -638,15 +642,15 @@
certificate generation tool to save the keys used to establish the Chain of
Trust. Allowed options are '0' or '1'. Default is '0' (do not save).
-- ``SCP_BL2``: Path to SCP\_BL2 image in the host file system. This image is optional.
- If a SCP\_BL2 image is present then this option must be passed for the ``fip``
+- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional.
+ If a SCP_BL2 image is present then this option must be passed for the ``fip``
target.
- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies the
- file that contains the SCP\_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
+ file that contains the SCP_BL2 private key in PEM format. If ``SAVE_KEYS=1``,
this file name will be used to save the key.
-- ``SCP_BL2U``: Path to SCP\_BL2U image in the host file system. This image is
+- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is
optional. It is only needed if the platform makefile specifies that it
is required in order to build the ``fwu_fip`` target.
@@ -685,7 +689,7 @@
Boot feature. When set to '1', BL1 and BL2 images include support to load
and verify the certificates and images in a FIP, and BL1 includes support
for the Firmware Update. The default value is '0'. Generation and inclusion
- of certificates in the FIP and FWU\_FIP depends upon the value of the
+ of certificates in the FIP and FWU_FIP depends upon the value of the
``GENERATE_COT`` option.
Note: This option depends on ``CREATE_KEYS`` to be enabled. If the keys
@@ -828,8 +832,8 @@
TF-A no longer supports earlier SCP versions. If this option is set to 1
then TF-A will detect if an earlier version is in use. Default is 1.
-- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP\_BL2 and
- SCP\_BL2U to the FIP and FWU\_FIP respectively, and enables them to be loaded
+- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and
+ SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
during boot. Default is 1.
- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers
@@ -1083,7 +1087,7 @@
- Image Authentication, described in `Trusted Board Boot`_, and
- Firmware Update, described in `Firmware Update`_
-The following steps should be followed to build FIP and (optionally) FWU\_FIP
+The following steps should be followed to build FIP and (optionally) FWU_FIP
images with support for these features:
#. Fulfill the dependencies of the ``mbedtls`` cryptographic and image parser
@@ -1146,13 +1150,13 @@
described in the TBBR-client document. These certificates can also be found
in the output build directory.
-#. The optional FWU\_FIP contains any additional images to be loaded from
+#. The optional FWU_FIP contains any additional images to be loaded from
Non-Volatile storage during the `Firmware Update`_ process. To build the
- FWU\_FIP, any FWU images required by the platform must be specified on the
+ FWU_FIP, any FWU images required by the platform must be specified on the
command line. On Arm development platforms like Juno, these are:
- - NS\_BL2U. The AP non-secure Firmware Updater image.
- - SCP\_BL2U. The SCP Firmware Update Configuration image.
+ - NS_BL2U. The AP non-secure Firmware Updater image.
+ - SCP_BL2U. The SCP Firmware Update Configuration image.
Example of Juno command line for generating both ``fwu`` and ``fwu_fip``
targets using RSA development:
@@ -1169,15 +1173,15 @@
NS_BL2U=<path-to>/<ns_bl2u_image> \
all fip fwu_fip
- Note: The BL2U image will be built by default and added to the FWU\_FIP.
+ Note: The BL2U image will be built by default and added to the FWU_FIP.
The user may override this by adding ``BL2U=<path-to>/<bl2u_image>``
to the command line above.
- Note: Building and installing the non-secure and SCP FWU images (NS\_BL1U,
- NS\_BL2U and SCP\_BL2U) is outside the scope of this document.
+ Note: Building and installing the non-secure and SCP FWU images (NS_BL1U,
+ NS_BL2U and SCP_BL2U) is outside the scope of this document.
- The result of this build will be bl1.bin, fip.bin and fwu\_fip.bin binaries.
- Both the FIP and FWU\_FIP will include the certificates corresponding to the
+ The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries.
+ Both the FIP and FWU_FIP will include the certificates corresponding to the
Chain of Trust described in the TBBR-client document. These certificates
can also be found in the output build directory.
@@ -1194,7 +1198,7 @@
make PLAT=<platform> [DEBUG=1] [V=1] certtool
For platforms that require their own IDs in certificate files, the generic
-'cert\_create' tool can be built with the following command:
+'cert_create' tool can be built with the following command:
::
@@ -1236,9 +1240,9 @@
make realclean
-#. Obtain SCP\_BL2 (Juno) and BL33 (all platforms)
+#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
- Use the fiptool to extract the SCP\_BL2 and BL33 images from the FIP
+ Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
package included in the Linaro release:
::
@@ -1251,7 +1255,7 @@
<path/to/linaro/release>/fip.bin
The unpack operation will result in a set of binary images extracted to the
- current working directory. The SCP\_BL2 image corresponds to
+ current working directory. The SCP_BL2 image corresponds to
``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
Note: The fiptool will complain if the images to be unpacked already
@@ -1402,7 +1406,7 @@
- putting the system into a known architectural state;
- taking care of platform secure world initialization;
-- loading the SCP\_BL2 image if required by the platform.
+- loading the SCP_BL2 image if required by the platform.
When booting an EL3 payload on Arm standard platforms, the configuration of the
TrustZone controller is simplified such that only region 0 is enabled and is
@@ -1919,8 +1923,8 @@
``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
``BL32_BASE``.
-Running on the AEMv8 Base FVP (AArch32) with reset to SP\_MIN entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
with 8 CPUs using the AArch32 build of TF-A.
@@ -1987,8 +1991,8 @@
--data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
-Running on the Cortex-A32 Base FVP (AArch32) with reset to SP\_MIN entrypoint
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
boot Linux with 4 CPUs using the AArch32 build of TF-A.
diff --git a/docs/xlat-tables-lib-v2-design.rst b/docs/xlat-tables-lib-v2-design.rst
index f07dfab..dbed7f8 100644
--- a/docs/xlat-tables-lib-v2-design.rst
+++ b/docs/xlat-tables-lib-v2-design.rst
@@ -37,8 +37,8 @@
-----------------------------
This document focuses on version 2 of the library, whose sources are available
-in the `lib/xlat\_tables\_v2`_ directory. Version 1 of the library can still be
-found in `lib/xlat\_tables`_ directory but it is less flexible and doesn't
+in the `lib/xlat_tables_v2`_ directory. Version 1 of the library can still be
+found in `lib/xlat_tables`_ directory but it is less flexible and doesn't
support dynamic mapping. Although potential bug fixes will be applied to both
versions, future features enhancements will focus on version 2 and might not be
back-ported to version 1. Therefore, it is recommended to use version 2,
@@ -69,7 +69,7 @@
- its attributes;
- its mapping granularity (optional).
-See the ``struct mmap_region`` type in `xlat\_tables\_v2.h`_.
+See the ``struct mmap_region`` type in `xlat_tables_v2.h`_.
The user usually provides a list of such mmap regions to map and lets the
library transpose that in a set of translation tables. As a result, the library
@@ -80,7 +80,7 @@
read-write, executable or not, secure or non-secure, and so on). In the case of
the EL1&0 translation regime, the attributes also specify whether the region is
a User region (EL0) or Privileged region (EL1). See the ``MT_xxx`` definitions
-in `xlat\_tables\_v2.h`_. Note that for the EL1&0 translation regime the Execute
+in `xlat_tables_v2.h`_. Note that for the EL1&0 translation regime the Execute
Never attribute is set simultaneously for both EL1 and EL0.
The granularity controls the translation table level to go down to when mapping
@@ -208,7 +208,7 @@
------------
The external APIs exposed by this library are declared and documented in the
-`xlat\_tables\_v2.h`_ header file. This should be the reference point for
+`xlat_tables_v2.h`_ header file. This should be the reference point for
getting information about the usage of the different APIs this library
provides. This section just provides some extra details and clarifications.
@@ -291,7 +291,7 @@
provides functions such as ``mmap_add_region_ctx`` that let the caller specify
the translation tables context affected by them.
- See `xlat\_tables\_core.c`_.
+ See `xlat_tables_core.c`_.
- **Active context module**
@@ -300,14 +300,14 @@
This module provides functions such as ``mmap_add_region``, that directly
affect the BL image using them.
- See `xlat\_tables\_context.c`_.
+ See `xlat_tables_context.c`_.
- **Utilities module**
Provides additional functionality like debug print of the current state of the
translation tables and helpers to query memory attributes and to modify them.
- See `xlat\_tables\_utils.c`_.
+ See `xlat_tables_utils.c`_.
- **Architectural module**
@@ -316,7 +316,7 @@
MMU, or calculate the Physical Address Space size. They do not need a
translation context to work on.
- See `aarch32/xlat\_tables\_arch.c`_ and `aarch64/xlat\_tables\_arch.c`_.
+ See `aarch32/xlat_tables_arch.c`_ and `aarch64/xlat_tables_arch.c`_.
From mmap regions to translation tables
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -416,13 +416,13 @@
*Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.*
-.. _lib/xlat\_tables\_v2: ../lib/xlat_tables_v2
-.. _lib/xlat\_tables: ../lib/xlat_tables
-.. _xlat\_tables\_v2.h: ../include/lib/xlat_tables/xlat_tables_v2.h
-.. _xlat\_tables\_context.c: ../lib/xlat_tables_v2/xlat_tables_context.c
-.. _xlat\_tables\_core.c: ../lib/xlat_tables_v2/xlat_tables_core.c
-.. _xlat\_tables\_utils.c: ../lib/xlat_tables_v2/xlat_tables_utils.c
-.. _aarch32/xlat\_tables\_arch.c: ../lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
-.. _aarch64/xlat\_tables\_arch.c: ../lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+.. _lib/xlat_tables_v2: ../lib/xlat_tables_v2
+.. _lib/xlat_tables: ../lib/xlat_tables
+.. _xlat_tables_v2.h: ../include/lib/xlat_tables/xlat_tables_v2.h
+.. _xlat_tables_context.c: ../lib/xlat_tables_v2/xlat_tables_context.c
+.. _xlat_tables_core.c: ../lib/xlat_tables_v2/xlat_tables_core.c
+.. _xlat_tables_utils.c: ../lib/xlat_tables_v2/xlat_tables_utils.c
+.. _aarch32/xlat_tables_arch.c: ../lib/xlat_tables_v2/aarch32/xlat_tables_arch.c
+.. _aarch64/xlat_tables_arch.c: ../lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
.. _Porting Guide: porting-guide.rst
.. |Alignment Example| image:: ./diagrams/xlat_align.png?raw=true
diff --git a/drivers/delay_timer/generic_delay_timer.c b/drivers/delay_timer/generic_delay_timer.c
index 4b67ed0..3d0a11f 100644
--- a/drivers/delay_timer/generic_delay_timer.c
+++ b/drivers/delay_timer/generic_delay_timer.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -43,6 +44,8 @@
void generic_delay_timer_init(void)
{
+ assert(is_armv7_gentimer_present());
+
/* Value in ticks */
unsigned int mult = MHZ_TICKS_PER_SEC;
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index 4af3e90..3421e04 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -114,6 +114,8 @@
#define ID_PFR1_VIRTEXT_MASK U(0xf)
#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
& ID_PFR1_VIRTEXT_MASK)
+#define ID_PFR1_GENTIMER_SHIFT U(16)
+#define ID_PFR1_GENTIMER_MASK U(0xf)
#define ID_PFR1_GIC_SHIFT U(28)
#define ID_PFR1_GIC_MASK U(0xf)
diff --git a/include/arch/aarch32/arch_features.h b/include/arch/aarch32/arch_features.h
index d934102..ddf0968 100644
--- a/include/arch/aarch32/arch_features.h
+++ b/include/arch/aarch32/arch_features.h
@@ -11,6 +11,12 @@
#include <arch_helpers.h>
+static inline bool is_armv7_gentimer_present(void)
+{
+ return ((read_id_pfr1() >> ID_PFR1_GENTIMER_SHIFT) &
+ ID_PFR1_GENTIMER_MASK) != 0U;
+}
+
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_mmfr4() >> ID_MMFR4_CNP_SHIFT) &
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 9bf43bf..da8b6e4 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -11,6 +11,12 @@
#include <arch_helpers.h>
+static inline bool is_armv7_gentimer_present(void)
+{
+ /* The Generic Timer is always present in an ARMv8-A implementation */
+ return true;
+}
+
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h
index 2c12633..ce8e3e8 100644
--- a/include/bl32/payloads/tlk.h
+++ b/include/bl32/payloads/tlk.h
@@ -20,7 +20,9 @@
*/
#define TLK_REGISTER_LOGBUF TLK_TOS_YIELD_FID(0x1)
#define TLK_REGISTER_REQBUF TLK_TOS_YIELD_FID(0x2)
-#define TLK_REGISTER_NS_DRAM TLK_TOS_YIELD_FID(0x4)
+#define TLK_SS_REGISTER_HANDLER TLK_TOS_YIELD_FID(0x3)
+#define TLK_REGISTER_NS_DRAM_RANGES TLK_TOS_YIELD_FID(0x4)
+#define TLK_SET_ROOT_OF_TRUST TLK_TOS_YIELD_FID(0x5)
#define TLK_RESUME_FID TLK_TOS_YIELD_FID(0x100)
#define TLK_SYSTEM_SUSPEND TLK_TOS_YIELD_FID(0xE001)
#define TLK_SYSTEM_RESUME TLK_TOS_YIELD_FID(0xE002)
diff --git a/lib/aarch64/armclang_printf.S b/lib/aarch64/armclang_printf.S
index 2b87bf7..52a6976 100644
--- a/lib/aarch64/armclang_printf.S
+++ b/lib/aarch64/armclang_printf.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,7 +13,13 @@
.globl __2printf
func __0printf
-__1printf:
-__2printf:
- b printf
+ b printf
endfunc __0printf
+
+func __1printf
+ b printf
+endfunc __1printf
+
+func __2printf
+ b printf
+endfunc __2printf
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 9aac8cf..de11583 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
+#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#if !ERROR_DEPRECATED
@@ -18,16 +19,13 @@
.globl zero_normalmem
.globl zeromem
- .globl zeromem16
.globl memcpy16
.globl disable_mmu_el1
.globl disable_mmu_el3
.globl disable_mmu_icache_el1
.globl disable_mmu_icache_el3
-
.globl fixup_gdt_reloc
-
#if SUPPORT_VFP
.globl enable_vfp
#endif
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 867da92..cc13fc1 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -51,7 +51,9 @@
* Use the linker defined symbol which has evaluated the size reqiurement.
* This is not as efficient as using a platform defined constant
*/
-IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
+IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_START__, BAKERY_LOCK_START);
+IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_END__, BAKERY_LOCK_END);
+#define PERCPU_BAKERY_LOCK_SIZE (BAKERY_LOCK_END - BAKERY_LOCK_START)
#endif
static inline bakery_lock_t *get_bakery_info(unsigned int cpu_ix,
diff --git a/lib/xlat_tables_v2/xlat_tables_core.c b/lib/xlat_tables_v2/xlat_tables_core.c
index 4820b4f..d7d8c22 100644
--- a/lib/xlat_tables_v2/xlat_tables_core.c
+++ b/lib/xlat_tables_v2/xlat_tables_core.c
@@ -21,7 +21,7 @@
#include "xlat_tables_private.h"
/* Helper function that cleans the data cache only if it is enabled. */
-static inline void xlat_clean_dcache_range(uintptr_t addr, size_t size)
+static inline __attribute__((unused)) void xlat_clean_dcache_range(uintptr_t addr, size_t size)
{
if (is_dcache_enabled())
clean_dcache_range(addr, size);
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index c1aa320..76a9fd4 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -122,6 +122,9 @@
# NS timer register save and restore
NS_TIMER_SWITCH := 0
+# Include lib/libc in the final image
+OVERRIDE_LIBC := 0
+
# Build PL011 UART driver in minimal generic UART mode
PL011_GENERIC_UART := 0
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index b5788fb..b8fd3a2 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,8 +26,6 @@
.weak plat_handle_double_fault
.weak plat_handle_el3_ea
- .globl platform_get_core_pos
-
#define MPIDR_RES_BIT_MASK 0xff000000
/* -----------------------------------------------------
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index f1cc6be..972a118 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,8 +12,6 @@
.local platform_normal_stacks
.weak plat_get_my_stack
.weak plat_set_my_stack
- .globl platform_get_stack
- .globl platform_set_stack
/* ---------------------------------------------------------------------
* When the compatility layer is disabled, the new platform APIs
diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S
index 0ff6930..c6e5e2d 100644
--- a/plat/common/aarch64/platform_up_stack.S
+++ b/plat/common/aarch64/platform_up_stack.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,8 +12,6 @@
.local platform_normal_stacks
.weak plat_set_my_stack
.weak plat_get_my_stack
- .weak platform_set_stack
- .weak platform_get_stack
/* -----------------------------------------------------
* uintptr_t plat_get_my_stack ()
diff --git a/plat/mediatek/mt6795/bl31.ld.S b/plat/mediatek/mt6795/bl31.ld.S
index 6ec7a1a..cf68b71 100644
--- a/plat/mediatek/mt6795/bl31.ld.S
+++ b/plat/mediatek/mt6795/bl31.ld.S
@@ -113,9 +113,11 @@
*/
. = ALIGN(CACHE_WRITEBACK_GRANULE);
__BAKERY_LOCK_START__ = .;
+ __PERCPU_BAKERY_LOCK_START__ = .;
*(bakery_lock)
. = ALIGN(CACHE_WRITEBACK_GRANULE);
- __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
+ __PERCPU_BAKERY_LOCK_END__ = .;
+ __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
. = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
__BAKERY_LOCK_END__ = .;
#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
diff --git a/plat/nvidia/tegra/common/drivers/bpmp/bpmp.c b/plat/nvidia/tegra/common/drivers/bpmp/bpmp.c
index 1c5d2e1..29dc267 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp/bpmp.c
+++ b/plat/nvidia/tegra/common/drivers/bpmp/bpmp.c
@@ -16,7 +16,7 @@
#include <string.h>
#include <tegra_def.h>
-#define BPMP_TIMEOUT 2
+#define BPMP_TIMEOUT 500 /* 500ms */
static uint32_t channel_base[NR_CHANNELS];
static uint32_t bpmp_init_state = BPMP_INIT_PENDING;
@@ -115,58 +115,117 @@
int tegra_bpmp_init(void)
{
- uint32_t val, base;
+ uint32_t val, base, timeout = BPMP_TIMEOUT;
unsigned int ch;
int ret = 0;
- if (bpmp_init_state != BPMP_INIT_COMPLETE) {
+ if (bpmp_init_state == BPMP_INIT_PENDING) {
/* check if the bpmp processor is alive. */
- val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
- if (val != SIGN_OF_LIFE) {
- ERROR("BPMP precessor not available\n");
- return -ENOTSUP;
- }
+ do {
+ val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
+ if (val != SIGN_OF_LIFE) {
+ mdelay(1);
+ timeout--;
+ }
- /* check if clock for the atomics block is enabled */
- val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_ENB_V);
- if ((val & CAR_ENABLE_ATOMICS) == 0) {
- ERROR("Clock to the atomics block is disabled\n");
- }
+ } while ((val != SIGN_OF_LIFE) && (timeout > 0U));
- /* check if the atomics block is out of reset */
- val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_CLR_V);
- if ((val & CAR_ENABLE_ATOMICS) == CAR_ENABLE_ATOMICS) {
- ERROR("Reset to the atomics block is asserted\n");
- }
+ if (val == SIGN_OF_LIFE) {
- /* base address to get the result from Atomics */
- base = TEGRA_ATOMICS_BASE + RESULT0_REG_OFFSET;
+ /* check if clock for the atomics block is enabled */
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_ENB_V);
+ if ((val & CAR_ENABLE_ATOMICS) == 0) {
+ ERROR("Clock to the atomics block is disabled\n");
+ }
+
+ /* check if the atomics block is out of reset */
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_CLR_V);
+ if ((val & CAR_ENABLE_ATOMICS) == CAR_ENABLE_ATOMICS) {
+ ERROR("Reset to the atomics block is asserted\n");
+ }
- /* channel area is setup by BPMP before signaling handshake */
- for (ch = 0; ch < NR_CHANNELS; ch++) {
+ /* base address to get the result from Atomics */
+ base = TEGRA_ATOMICS_BASE + RESULT0_REG_OFFSET;
- /* issue command to get the channel base address */
- mmio_write_32(base, (ch << TRIGGER_ID_SHIFT) |
- ATOMIC_CMD_GET);
+ /* channel area is setup by BPMP before signaling handshake */
+ for (ch = 0; ch < NR_CHANNELS; ch++) {
- /* get the base address for the channel */
- channel_base[ch] = mmio_read_32(base);
+ /* issue command to get the channel base address */
+ mmio_write_32(base, (ch << TRIGGER_ID_SHIFT) |
+ ATOMIC_CMD_GET);
- /* increment result register offset */
- base += 4U;
+ /* get the base address for the channel */
+ channel_base[ch] = mmio_read_32(base);
+
+ /* increment result register offset */
+ base += 4U;
+ }
+
+ /* mark state as "initialized" */
+ bpmp_init_state = BPMP_INIT_COMPLETE;
+
+ /* the channel values have to be visible across all cpus */
+ flush_dcache_range((uint64_t)channel_base,
+ sizeof(channel_base));
+ flush_dcache_range((uint64_t)&bpmp_init_state,
+ sizeof(bpmp_init_state));
+
+ INFO("%s: done\n", __func__);
+
+ } else {
+ ERROR("BPMP not powered on\n");
+
+ /* bpmp is not present in the system */
+ bpmp_init_state = BPMP_NOT_PRESENT;
+
+ /* communication timed out */
+ ret = -ETIMEDOUT;
}
+ }
- /* mark state as "initialized" */
- bpmp_init_state = BPMP_INIT_COMPLETE;
+ return ret;
+}
- /* the channel values have to be visible across all cpus */
- flush_dcache_range((uint64_t)channel_base, sizeof(channel_base));
+void tegra_bpmp_suspend(void)
+{
+ /* freeze the interface */
+ if (bpmp_init_state == BPMP_INIT_COMPLETE) {
+ bpmp_init_state = BPMP_SUSPEND_ENTRY;
flush_dcache_range((uint64_t)&bpmp_init_state,
sizeof(bpmp_init_state));
-
- INFO("%s: done\n", __func__);
}
+}
- return ret;
+void tegra_bpmp_resume(void)
+{
+ uint32_t val, timeout = 0;
+
+ if (bpmp_init_state == BPMP_SUSPEND_ENTRY) {
+
+ /* check if the bpmp processor is alive. */
+ do {
+
+ val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
+ if (val != SIGN_OF_LIFE) {
+ mdelay(1);
+ timeout++;
+ }
+
+ } while ((val != SIGN_OF_LIFE) && (timeout < BPMP_TIMEOUT));
+
+ if (val == SIGN_OF_LIFE) {
+
+ INFO("%s: BPMP took %d ms to resume\n", __func__, timeout);
+
+ /* mark state as "initialized" */
+ bpmp_init_state = BPMP_INIT_COMPLETE;
+
+ /* state has to be visible across all cpus */
+ flush_dcache_range((uint64_t)&bpmp_init_state,
+ sizeof(bpmp_init_state));
+ } else {
+ ERROR("BPMP not powered on\n");
+ }
+ }
}
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
index 7faa2f0..2efa1bd 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -302,3 +302,49 @@
return ret;
}
+
+int tegra_bpmp_ipc_enable_clock(uint32_t clk_id)
+{
+ int ret;
+ struct mrq_clk_request req;
+
+ /* only SE clocks are supported */
+ if (clk_id != TEGRA_CLK_SE) {
+ return -ENOTSUP;
+ }
+
+ /* prepare the MRQ_CLK command */
+ req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_ENABLE, clk_id);
+
+ ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, sizeof(req),
+ NULL, 0);
+ if (ret != 0) {
+ ERROR("%s: failed for module %d with error %d\n", __func__,
+ clk_id, ret);
+ }
+
+ return ret;
+}
+
+int tegra_bpmp_ipc_disable_clock(uint32_t clk_id)
+{
+ int ret;
+ struct mrq_clk_request req;
+
+ /* only SE clocks are supported */
+ if (clk_id != TEGRA_CLK_SE) {
+ return -ENOTSUP;
+ }
+
+ /* prepare the MRQ_CLK command */
+ req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_DISABLE, clk_id);
+
+ ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, sizeof(req),
+ NULL, 0);
+ if (ret != 0) {
+ ERROR("%s: failed for module %d with error %d\n", __func__,
+ clk_id, ret);
+ }
+
+ return ret;
+}
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
index 689f8bb..7059c37 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,10 +11,10 @@
* Flags used in IPC req
*/
#define FLAG_DO_ACK (U(1) << 0)
-#define FLAG_RING_DOORBELL (U(1) << 1)
+#define FLAG_RING_DOORBELL (U(1) << 1)
/* Bit 1 is designated for CCPlex in secure world */
-#define HSP_MASTER_CCPLEX_BIT (U(1) << 1)
+#define HSP_MASTER_CCPLEX_BIT (U(1) << 1)
/* Bit 19 is designated for BPMP in non-secure world */
#define HSP_MASTER_BPMP_BIT (U(1) << 19)
/* Timeout to receive response from BPMP is 1 sec */
@@ -49,9 +49,10 @@
*/
/**
- * MRQ code to issue a module reset command to BPMP
+ * MRQ command codes
*/
#define MRQ_RESET U(20)
+#define MRQ_CLK U(22)
/**
* Reset sub-commands
@@ -71,4 +72,56 @@
uint32_t reset_id;
};
+/**
+ * MRQ_CLK sub-commands
+ *
+ */
+enum {
+ CMD_CLK_GET_RATE = 1,
+ CMD_CLK_SET_RATE = 2,
+ CMD_CLK_ROUND_RATE = 3,
+ CMD_CLK_GET_PARENT = 4,
+ CMD_CLK_SET_PARENT = 5,
+ CMD_CLK_IS_ENABLED = 6,
+ CMD_CLK_ENABLE = 7,
+ CMD_CLK_DISABLE = 8,
+ CMD_CLK_GET_ALL_INFO = 14,
+ CMD_CLK_GET_MAX_CLK_ID = 15,
+ CMD_CLK_MAX,
+};
+
+/**
+ * Used by the sender of an #MRQ_CLK message to control clocks. The
+ * clk_request is split into several sub-commands. Some sub-commands
+ * require no additional data. Others have a sub-command specific
+ * payload
+ *
+ * |sub-command |payload |
+ * |----------------------------|-----------------------|
+ * |CMD_CLK_GET_RATE |- |
+ * |CMD_CLK_SET_RATE |clk_set_rate |
+ * |CMD_CLK_ROUND_RATE |clk_round_rate |
+ * |CMD_CLK_GET_PARENT |- |
+ * |CMD_CLK_SET_PARENT |clk_set_parent |
+ * |CMD_CLK_IS_ENABLED |- |
+ * |CMD_CLK_ENABLE |- |
+ * |CMD_CLK_DISABLE |- |
+ * |CMD_CLK_GET_ALL_INFO |- |
+ * |CMD_CLK_GET_MAX_CLK_ID |- |
+ *
+ */
+struct mrq_clk_request {
+ /**
+ * sub-command and clock id concatenated to 32-bit word.
+ * - bits[31..24] is the sub-cmd.
+ * - bits[23..0] is the clock id
+ */
+ uint32_t cmd_and_id;
+};
+
+/**
+ * Macro to prepare the MRQ_CLK sub-command
+ */
+#define make_mrq_clk_cmd(cmd, id) (((cmd) << 24) | (id & 0xFFFFFF))
+
#endif /* INTF_H */
diff --git a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
index 775ad30..bdd3ee7 100644
--- a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
+++ b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,6 +15,7 @@
#include <flowctrl.h>
#include <pmc.h>
#include <tegra_def.h>
+#include <utils_def.h>
#define CLK_RST_DEV_L_SET 0x300
#define CLK_RST_DEV_L_CLR 0x304
@@ -76,6 +77,47 @@
}
/*******************************************************************************
+ * After this, no core can wake from C7 until the action is reverted.
+ * If a wake up event is asserted, the FC state machine will stall until
+ * the action is reverted.
+ ******************************************************************************/
+void tegra_fc_ccplex_pgexit_lock(void)
+{
+ unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
+ uint32_t flags = tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT) & ~INTERCEPT_IRQ_PENDING;;
+ uint32_t icept_cpu_flags[] = {
+ INTERCEPT_EXIT_PG_CORE0,
+ INTERCEPT_EXIT_PG_CORE1,
+ INTERCEPT_EXIT_PG_CORE2,
+ INTERCEPT_EXIT_PG_CORE3
+ };
+
+ /* set the intercept flags */
+ for (i = 0; i < ARRAY_SIZE(icept_cpu_flags); i++) {
+
+ /* skip current CPU */
+ if (i == cpu)
+ continue;
+
+ /* enable power gate exit intercept locks */
+ flags |= icept_cpu_flags[i];
+ }
+
+ tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, flags);
+ (void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT);
+}
+
+/*******************************************************************************
+ * Revert the ccplex powergate exit locks
+ ******************************************************************************/
+void tegra_fc_ccplex_pgexit_unlock(void)
+{
+ /* clear lock bits, clear pending interrupts */
+ tegra_fc_write_32(FLOWCTRL_FC_SEQ_INTERCEPT, INTERCEPT_IRQ_PENDING);
+ (void)tegra_fc_read_32(FLOWCTRL_FC_SEQ_INTERCEPT);
+}
+
+/*******************************************************************************
* Powerdn the current CPU
******************************************************************************/
void tegra_fc_cpu_powerdn(uint32_t mpidr)
@@ -129,6 +171,31 @@
}
/*******************************************************************************
+ * Check if cluster idle or power down state is allowed from this CPU
+ ******************************************************************************/
+bool tegra_fc_is_ccx_allowed(void)
+{
+ unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
+ uint32_t val;
+ bool ccx_allowed = true;
+
+ for (i = 0; i < ARRAY_SIZE(flowctrl_offset_cpu_csr); i++) {
+
+ /* skip current CPU */
+ if (i == cpu)
+ continue;
+
+ /* check if all other CPUs are already halted */
+ val = mmio_read_32(flowctrl_offset_cpu_csr[i]);
+ if ((val & FLOWCTRL_CSR_HALT_MASK) == 0U) {
+ ccx_allowed = false;
+ }
+ }
+
+ return ccx_allowed;
+}
+
+/*******************************************************************************
* Suspend the entire SoC
******************************************************************************/
void tegra_fc_soc_powerdn(uint32_t mpidr)
@@ -190,22 +257,19 @@
}
/*******************************************************************************
- * Reset BPMP processor
+ * Power ON BPMP processor
******************************************************************************/
-void tegra_fc_reset_bpmp(void)
+void tegra_fc_bpmp_on(uint32_t entrypoint)
{
- uint32_t val;
-
/* halt BPMP */
tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT);
/* Assert BPMP reset */
mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST);
- /* Restore reset address (stored in PMC_SCRATCH39) */
- val = tegra_pmc_read_32(PMC_SCRATCH39);
- mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, val);
- while (val != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
+ /* Set reset address (stored in PMC_SCRATCH39) */
+ mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, entrypoint);
+ while (entrypoint != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
/* Wait for 2us before de-asserting the reset signal. */
@@ -217,3 +281,42 @@
/* Un-halt BPMP */
tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0);
}
+
+/*******************************************************************************
+ * Power OFF BPMP processor
+ ******************************************************************************/
+void tegra_fc_bpmp_off(void)
+{
+ /* halt BPMP */
+ tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT);
+
+ /* Assert BPMP reset */
+ mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST);
+
+ /* Clear reset address */
+ mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, 0);
+ while (0 != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR))
+ ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
+}
+
+/*******************************************************************************
+ * Route legacy FIQ to the GICD
+ ******************************************************************************/
+void tegra_fc_enable_fiq_to_ccplex_routing(void)
+{
+ uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
+
+ /* set the bit to pass FIQs to the GICD */
+ tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val | FLOWCTRL_FIQ2CCPLEX_ENABLE);
+}
+
+/*******************************************************************************
+ * Disable routing legacy FIQ to the GICD
+ ******************************************************************************/
+void tegra_fc_disable_fiq_to_ccplex_routing(void)
+{
+ uint32_t val = tegra_fc_read_32(FLOW_CTLR_FLOW_DBG_QUAL);
+
+ /* clear the bit to pass FIQs to the GICD */
+ tegra_fc_write_32(FLOW_CTLR_FLOW_DBG_QUAL, val & ~FLOWCTRL_FIQ2CCPLEX_ENABLE);
+}
diff --git a/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/plat/nvidia/tegra/common/drivers/pmc/pmc.c
index b9ff511..6c5a73b 100644
--- a/plat/nvidia/tegra/common/drivers/pmc/pmc.c
+++ b/plat/nvidia/tegra/common/drivers/pmc/pmc.c
@@ -17,7 +17,7 @@
/* Module IDs used during power ungate procedure */
static const uint32_t pmc_cpu_powergate_id[4] = {
- 0, /* CPU 0 */
+ 14, /* CPU 0 */
9, /* CPU 1 */
10, /* CPU 2 */
11 /* CPU 3 */
@@ -98,6 +98,45 @@
}
/*******************************************************************************
+ * Find out if this is the last standing CPU
+ ******************************************************************************/
+bool tegra_pmc_is_last_on_cpu(void)
+{
+ int i, cpu = read_mpidr() & MPIDR_CPU_MASK;
+ uint32_t val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);;
+ bool status = true;
+
+ /* check if this is the last standing CPU */
+ for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+
+ /* skip the current CPU */
+ if (i == cpu)
+ continue;
+
+ /* are other CPUs already power gated? */
+ if ((val & ((uint32_t)1 << pmc_cpu_powergate_id[i])) != 0U) {
+ status = false;
+ }
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+ * Handler to be called on exiting System suspend. Right now only DPD registers
+ * are cleared.
+ ******************************************************************************/
+void tegra_pmc_resume(void)
+{
+
+ /* Clear DPD sample */
+ mmio_write_32((TEGRA_PMC_BASE + PMC_IO_DPD_SAMPLE), 0x0);
+
+ /* Clear DPD Enable */
+ mmio_write_32((TEGRA_PMC_BASE + PMC_DPD_ENABLE_0), 0x0);
+}
+
+/*******************************************************************************
* Restart the system
******************************************************************************/
__dead2 void tegra_pmc_system_reset(void)
diff --git a/plat/nvidia/tegra/common/drivers/spe/shared_console.S b/plat/nvidia/tegra/common/drivers/spe/shared_console.S
index a9f0334..c1fbc84 100644
--- a/plat/nvidia/tegra/common/drivers/spe/shared_console.S
+++ b/plat/nvidia/tegra/common/drivers/spe/shared_console.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,12 +63,28 @@
/* Check the input parameter */
cbz x1, putc_error
+ /* Prepend '\r' to '\n' */
+ cmp w0, #0xA
+ b.ne 2f
+
/* wait until spe is ready */
1: ldr w2, [x1]
and w2, w2, #CONSOLE_IS_BUSY
cbnz w2, 1b
/* spe is ready */
+ mov w2, #0xD /* '\r' */
+ and w2, w2, #0xFF
+ mov w3, #(CONSOLE_WRITE | (1 << CONSOLE_NUM_BYTES_SHIFT))
+ orr w2, w2, w3
+ str w2, [x1]
+
+ /* wait until spe is ready */
+2: ldr w2, [x1]
+ and w2, w2, #CONSOLE_IS_BUSY
+ cbnz w2, 2b
+
+ /* spe is ready */
mov w2, w0
and w2, w2, #0xFF
mov w3, #(CONSOLE_WRITE | (1 << CONSOLE_NUM_BYTES_SHIFT))
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 908e4f2..c9beb14 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -162,13 +162,15 @@
}
/*
- * Parse platform specific parameters - TZDRAM aperture base and size
+ * Parse platform specific parameters
*/
assert(plat_params != NULL);
plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
+ plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
+ plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
/*
* It is very important that we run either from TZDRAM or TZSRAM base.
@@ -404,6 +406,14 @@
*/
boot_profiler_add_record("[TF] arch setup entry");
+ /* add MMIO space */
+ plat_mmio_map = plat_get_mmio_map();
+ if (plat_mmio_map != NULL) {
+ mmap_add(plat_mmio_map);
+ } else {
+ WARN("MMIO map not available\n");
+ }
+
/* add memory regions */
mmap_add_region(rw_start, rw_start,
rw_size,
@@ -415,14 +425,6 @@
code_size,
MT_CODE | MT_SECURE);
- /* map TZDRAM used by BL31 as coherent memory */
- if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
- mmap_add_region(params_from_bl2->tzdram_base,
- params_from_bl2->tzdram_base,
- BL31_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE);
- }
-
#if USE_COHERENT_MEM
coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
@@ -432,18 +434,12 @@
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
#endif
- /* map on-chip free running uS timer */
- mmap_add_region(page_align(TEGRA_TMRUS_BASE, 0),
- page_align(TEGRA_TMRUS_BASE, 0),
- TEGRA_TMRUS_SIZE,
- (uint8_t)MT_DEVICE | (uint8_t)MT_RO | (uint8_t)MT_SECURE);
-
- /* add MMIO space */
- plat_mmio_map = plat_get_mmio_map();
- if (plat_mmio_map != NULL) {
- mmap_add(plat_mmio_map);
- } else {
- WARN("MMIO map not available\n");
+ /* map TZDRAM used by BL31 as coherent memory */
+ if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
+ mmap_add_region(params_from_bl2->tzdram_base,
+ params_from_bl2->tzdram_base,
+ BL31_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE);
}
/* set up translation tables */
diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c
index cab2e5e..60b5595 100644
--- a/plat/nvidia/tegra/common/tegra_fiq_glue.c
+++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,9 +16,15 @@
#include <lib/el3_runtime/context_mgmt.h>
#include <plat/common/platform.h>
+#if ENABLE_WDT_LEGACY_FIQ_HANDLING
+#include <flowctrl.h>
+#endif
#include <tegra_def.h>
#include <tegra_private.h>
+/* Legacy FIQ used by earlier Tegra platforms */
+#define LEGACY_FIQ_PPI_WDT 28U
+
static DEFINE_BAKERY_LOCK(tegra_fiq_lock);
/*******************************************************************************
@@ -46,33 +52,58 @@
(void)handle;
(void)cookie;
- bakery_lock_get(&tegra_fiq_lock);
-
/*
- * The FIQ was generated when the execution was in the non-secure
- * world. Save the context registers to start with.
+ * Read the pending interrupt ID
*/
- cm_el1_sysregs_context_save(NON_SECURE);
+ irq = plat_ic_get_pending_interrupt_id();
+
+ bakery_lock_get(&tegra_fiq_lock);
/*
- * Save elr_el3 and spsr_el3 from the saved context, and overwrite
- * the context with the NS fiq_handler_addr and SPSR value.
+ * Jump to NS world only if the NS world's FIQ handler has
+ * been registered
*/
- fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3));
- fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
+ if (ns_fiq_handler_addr != 0U) {
+
+ /*
+ * The FIQ was generated when the execution was in the non-secure
+ * world. Save the context registers to start with.
+ */
+ cm_el1_sysregs_context_save(NON_SECURE);
+ /*
+ * Save elr_el3 and spsr_el3 from the saved context, and overwrite
+ * the context with the NS fiq_handler_addr and SPSR value.
+ */
+ fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3));
+ fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
+
+ /*
+ * Set the new ELR to continue execution in the NS world using the
+ * FIQ handler registered earlier.
+ */
+ cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr);
+ }
+
+#if ENABLE_WDT_LEGACY_FIQ_HANDLING
/*
- * Set the new ELR to continue execution in the NS world using the
- * FIQ handler registered earlier.
+ * Tegra platforms that use LEGACY_FIQ as the watchdog timer FIQ
+ * need to issue an IPI to other CPUs, to allow them to handle
+ * the "system hung" scenario. This interrupt is passed to the GICD
+ * via the Flow Controller. So, once we receive this interrupt,
+ * disable the routing so that we can mark it as "complete" in the
+ * GIC later.
*/
- assert(ns_fiq_handler_addr != 0ULL);
- write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr));
+ if (irq == LEGACY_FIQ_PPI_WDT) {
+ tegra_fc_disable_fiq_to_ccplex_routing();
+ }
+#endif
/*
* Mark this interrupt as complete to avoid a FIQ storm.
*/
- irq = plat_ic_acknowledge_interrupt();
if (irq < 1022U) {
+ (void)plat_ic_acknowledge_interrupt();
plat_ic_end_of_interrupt(irq);
}
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 2805272..e06a116 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -41,6 +41,7 @@
* provide typical implementations that will be overridden by a SoC.
*/
#pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early
+#pragma weak tegra_soc_cpu_standby
#pragma weak tegra_soc_pwr_domain_suspend
#pragma weak tegra_soc_pwr_domain_on
#pragma weak tegra_soc_pwr_domain_off
@@ -55,6 +56,12 @@
return PSCI_E_NOT_SUPPORTED;
}
+int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
+{
+ (void)cpu_state;
+ return PSCI_E_SUCCESS;
+}
+
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
(void)target_state;
@@ -139,14 +146,37 @@
******************************************************************************/
void tegra_cpu_standby(plat_local_state_t cpu_state)
{
+ u_register_t saved_scr_el3;
+
(void)cpu_state;
+ /* Tegra SoC specific handler */
+ if (tegra_soc_cpu_standby(cpu_state) != PSCI_E_SUCCESS)
+ ERROR("%s failed\n", __func__);
+
+ saved_scr_el3 = read_scr_el3();
+
+ /*
+ * As per ARM ARM D1.17.2, any physical IRQ interrupt received by the
+ * PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
+ * irrespective of the value of the PSTATE.I bit value.
+ */
+ write_scr_el3(saved_scr_el3 | SCR_IRQ_BIT);
+
/*
* Enter standby state
- * dsb is good practice before using wfi to enter low power states
+ *
+ * dsb & isb is good practice before using wfi to enter low power states
*/
dsb();
+ isb();
wfi();
+
+ /*
+ * Restore saved scr_el3 that has IRQ bit cleared as we don't want EL3
+ * handling any further interrupts
+ */
+ write_scr_el3(saved_scr_el3);
}
/*******************************************************************************
@@ -244,7 +274,7 @@
/*
* Initialize the GIC cpu and distributor interfaces
*/
- plat_gic_setup();
+ tegra_gic_init();
/*
* Check if we are exiting from deep sleep.
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c
index 4955b2f..957300e 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/common/tegra_sip_calls.c
@@ -116,6 +116,16 @@
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, local_x2_32);
+ /*
+ * Ensure again that GPU is still in reset after VPR resize
+ */
+ regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
+ TEGRA_GPU_RESET_REG_OFFSET);
+ if ((regval & GPU_RESET_BIT) == 0U) {
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_GPU_SET_OFFSET,
+ GPU_SET_BIT);
+ }
+
SMC_RET1(handle, 0);
/*
diff --git a/plat/nvidia/tegra/include/drivers/bpmp.h b/plat/nvidia/tegra/include/drivers/bpmp.h
index 03da6f6..dc3fb6b 100644
--- a/plat/nvidia/tegra/include/drivers/bpmp.h
+++ b/plat/nvidia/tegra/include/drivers/bpmp.h
@@ -27,8 +27,10 @@
#define SIGN_OF_LIFE 0xAAAAAAAAU
/* flags to indicate bpmp driver's state */
+#define BPMP_NOT_PRESENT 0xF00DBEEFU
#define BPMP_INIT_COMPLETE 0xBEEFF00DU
#define BPMP_INIT_PENDING 0xDEADBEEFU
+#define BPMP_SUSPEND_ENTRY 0xF00DCAFEU
/* requests serviced by the bpmp */
#define MRQ_PING 0
@@ -107,6 +109,16 @@
int tegra_bpmp_init(void);
/**
+ * Function to suspend the interface with the bpmp
+ */
+void tegra_bpmp_suspend(void);
+
+/**
+ * Function to resume the interface with the bpmp
+ */
+void tegra_bpmp_resume(void);
+
+/**
* Handler to send a MRQ_* command to the bpmp
*/
int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
diff --git a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
index 9304150..d487956 100644
--- a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
+++ b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,6 +18,11 @@
#define TEGRA_RESET_ID_GPCDMA U(70)
/**
+ * Clock identifier for the SE device
+ */
+#define TEGRA_CLK_SE U(124)
+
+/**
* Function to initialise the IPC with the bpmp
*/
int32_t tegra_bpmp_ipc_init(void);
@@ -27,4 +32,16 @@
*/
int32_t tegra_bpmp_ipc_reset_module(uint32_t rst_id);
+/**
+ * Handler to enable clock to a module. Only SE device is
+ * supported for now.
+ */
+int tegra_bpmp_ipc_enable_clock(uint32_t clk_id);
+
+/**
+ * Handler to disable clock to a module. Only SE device is
+ * supported for now.
+ */
+int tegra_bpmp_ipc_disable_clock(uint32_t clk_id);
+
#endif /* __BPMP_IPC_H__ */
diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h
index 3122181..54336b0 100644
--- a/plat/nvidia/tegra/include/drivers/flowctrl.h
+++ b/plat/nvidia/tegra/include/drivers/flowctrl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,7 @@
#include <tegra_def.h>
-#define FLOWCTRL_HALT_CPU0_EVENTS 0x0U
+#define FLOWCTRL_HALT_CPU0_EVENTS (0x0U)
#define FLOWCTRL_WAITEVENT (2U << 29)
#define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29)
#define FLOWCTRL_JTAG_RESUME (1U << 28)
@@ -20,19 +20,46 @@
#define FLOWCTRL_HALT_LIC_FIQ (1U << 10)
#define FLOWCTRL_HALT_GIC_IRQ (1U << 9)
#define FLOWCTRL_HALT_GIC_FIQ (1U << 8)
-#define FLOWCTRL_HALT_BPMP_EVENTS 0x4U
-#define FLOWCTRL_CPU0_CSR 0x8U
-#define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16)
+#define FLOWCTRL_HALT_BPMP_EVENTS (0x4U)
+#define FLOWCTRL_CPU0_CSR (0x8U)
+#define FLOWCTRL_CSR_HALT_MASK (1U << 22)
+#define FLOWCTRL_CSR_PWR_OFF_STS (1U << 16)
#define FLOWCTRL_CSR_INTR_FLAG (1U << 15)
#define FLOWCTRL_CSR_EVENT_FLAG (1U << 14)
#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3)
#define FLOWCTRL_CSR_ENABLE (1U << 0)
-#define FLOWCTRL_HALT_CPU1_EVENTS 0x14U
-#define FLOWCTRL_CPU1_CSR 0x18U
-#define FLOWCTRL_CC4_CORE0_CTRL 0x6cU
-#define FLOWCTRL_WAIT_WFI_BITMAP 0x100U
-#define FLOWCTRL_L2_FLUSH_CONTROL 0x94U
-#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U
+#define FLOWCTRL_HALT_CPU1_EVENTS (0x14U)
+#define FLOWCTRL_CPU1_CSR (0x18U)
+#define FLOW_CTLR_FLOW_DBG_QUAL (0x50U)
+#define FLOWCTRL_FIQ2CCPLEX_ENABLE (1U << 28)
+#define FLOWCTRL_FC_SEQ_INTERCEPT (0x5cU)
+#define INTERCEPT_IRQ_PENDING (0xffU)
+#define INTERCEPT_HVC (U(1) << 21)
+#define INTERCEPT_ENTRY_CC4 (U(1) << 20)
+#define INTERCEPT_ENTRY_PG_NONCPU (U(1) << 19)
+#define INTERCEPT_EXIT_PG_NONCPU (U(1) << 18)
+#define INTERCEPT_ENTRY_RG_CPU (U(1) << 17)
+#define INTERCEPT_EXIT_RG_CPU (U(1) << 16)
+#define INTERCEPT_ENTRY_PG_CORE0 (U(1) << 15)
+#define INTERCEPT_EXIT_PG_CORE0 (U(1) << 14)
+#define INTERCEPT_ENTRY_PG_CORE1 (U(1) << 13)
+#define INTERCEPT_EXIT_PG_CORE1 (U(1) << 12)
+#define INTERCEPT_ENTRY_PG_CORE2 (U(1) << 11)
+#define INTERCEPT_EXIT_PG_CORE2 (U(1) << 10)
+#define INTERCEPT_ENTRY_PG_CORE3 (U(1) << 9)
+#define INTERCEPT_EXIT_PG_CORE3 (U(1) << 8)
+#define INTERRUPT_PENDING_NONCPU (U(1) << 7)
+#define INTERRUPT_PENDING_CRAIL (U(1) << 6)
+#define INTERRUPT_PENDING_CORE0 (U(1) << 5)
+#define INTERRUPT_PENDING_CORE1 (U(1) << 4)
+#define INTERRUPT_PENDING_CORE2 (U(1) << 3)
+#define INTERRUPT_PENDING_CORE3 (U(1) << 2)
+#define CC4_INTERRUPT_PENDING (U(1) << 1)
+#define HVC_INTERRUPT_PENDING (U(1) << 0)
+#define FLOWCTRL_CC4_CORE0_CTRL (0x6cU)
+#define FLOWCTRL_WAIT_WFI_BITMAP (0x100U)
+#define FLOWCTRL_L2_FLUSH_CONTROL (0x94U)
+#define FLOWCTRL_BPMP_CLUSTER_CONTROL (0x98U)
#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2)
#define FLOWCTRL_ENABLE_EXT 12U
@@ -50,13 +77,19 @@
mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val);
}
+void tegra_fc_bpmp_on(uint32_t entrypoint);
+void tegra_fc_bpmp_off(void);
+void tegra_fc_ccplex_pgexit_lock(void);
+void tegra_fc_ccplex_pgexit_unlock(void);
void tegra_fc_cluster_idle(uint32_t midr);
void tegra_fc_cpu_powerdn(uint32_t mpidr);
void tegra_fc_cluster_powerdn(uint32_t midr);
-void tegra_fc_soc_powerdn(uint32_t midr);
void tegra_fc_cpu_on(int cpu);
void tegra_fc_cpu_off(int cpu);
+void tegra_fc_disable_fiq_to_ccplex_routing(void);
+void tegra_fc_enable_fiq_to_ccplex_routing(void);
+bool tegra_fc_is_ccx_allowed(void);
void tegra_fc_lock_active_cluster(void);
-void tegra_fc_reset_bpmp(void);
+void tegra_fc_soc_powerdn(uint32_t midr);
#endif /* FLOWCTRL_H */
diff --git a/plat/nvidia/tegra/include/drivers/pmc.h b/plat/nvidia/tegra/include/drivers/pmc.h
index a01a4b6..32252a2 100644
--- a/plat/nvidia/tegra/include/drivers/pmc.h
+++ b/plat/nvidia/tegra/include/drivers/pmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,22 +9,37 @@
#include <lib/mmio.h>
#include <lib/utils_def.h>
+#include <stdbool.h>
#include <tegra_def.h>
#define PMC_CONFIG U(0x0)
+#define PMC_IO_DPD_SAMPLE U(0x20)
+#define PMC_DPD_ENABLE_0 U(0x24)
#define PMC_PWRGATE_STATUS U(0x38)
#define PMC_PWRGATE_TOGGLE U(0x30)
+#define PMC_SECURE_SCRATCH0 U(0xb0)
+#define PMC_SECURE_SCRATCH5 U(0xc4)
+#define PMC_CRYPTO_OP_0 U(0xf4)
#define PMC_TOGGLE_START U(0x100)
#define PMC_SCRATCH39 U(0x138)
+#define PMC_SCRATCH41 U(0x140)
+#define PMC_SECURE_SCRATCH6 U(0x224)
+#define PMC_SECURE_SCRATCH7 U(0x228)
#define PMC_SECURE_DISABLE2 U(0x2c4)
#define PMC_SECURE_DISABLE2_WRITE22_ON (U(1) << 28)
+#define PMC_SECURE_SCRATCH8 U(0x300)
+#define PMC_SECURE_SCRATCH79 U(0x41c)
+#define PMC_FUSE_CONTROL_0 U(0x450)
#define PMC_SECURE_SCRATCH22 U(0x338)
#define PMC_SECURE_DISABLE3 U(0x2d8)
#define PMC_SECURE_DISABLE3_WRITE34_ON (U(1) << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (U(1) << 22)
#define PMC_SECURE_SCRATCH34 U(0x368)
#define PMC_SECURE_SCRATCH35 U(0x36c)
+#define PMC_SECURE_SCRATCH80 U(0xa98)
+#define PMC_SECURE_SCRATCH119 U(0xb34)
+#define PMC_SCRATCH201 U(0x844)
static inline uint32_t tegra_pmc_read_32(uint32_t off)
{
@@ -36,9 +51,11 @@
mmio_write_32(TEGRA_PMC_BASE + off, val);
}
+void tegra_pmc_cpu_on(int32_t cpu);
void tegra_pmc_cpu_setup(uint64_t reset_addr);
+bool tegra_pmc_is_last_on_cpu(void);
void tegra_pmc_lock_cpu_vectors(void);
-void tegra_pmc_cpu_on(int32_t cpu);
+void tegra_pmc_resume(void);
__dead2 void tegra_pmc_system_reset(void);
#endif /* PMC_H */
diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h
index 41b0c51..424a91a 100644
--- a/plat/nvidia/tegra/include/drivers/smmu.h
+++ b/plat/nvidia/tegra/include/drivers/smmu.h
@@ -618,9 +618,9 @@
.val = 0x00000000U, \
}
-#define smmu_make_gnsr0_sec_cfg(name) \
+#define smmu_make_gnsr0_sec_cfg(base_addr, name) \
{ \
- .reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_ ## name, \
+ .reg = base_addr + SMMU_GNSR0_ ## name, \
.val = 0x00000000U, \
}
@@ -628,60 +628,199 @@
* On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
* is 0x400. So, add it to register address
*/
-#define smmu_make_gnsr0_nsec_cfg(name) \
+#define smmu_make_gnsr0_nsec_cfg(base_addr, name) \
{ \
- .reg = TEGRA_SMMU0_BASE + 0x400U + SMMU_GNSR0_ ## name, \
+ .reg = base_addr + 0x400U + SMMU_GNSR0_ ## name, \
.val = 0x00000000U, \
}
-#define smmu_make_gnsr0_smr_cfg(n) \
+#define smmu_make_gnsr0_smr_cfg(base_addr, n) \
{ \
- .reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_SMR ## n, \
+ .reg = base_addr + SMMU_GNSR0_SMR ## n, \
.val = 0x00000000U, \
}
-#define smmu_make_gnsr0_s2cr_cfg(n) \
+#define smmu_make_gnsr0_s2cr_cfg(base_addr, n) \
{ \
- .reg = TEGRA_SMMU0_BASE + SMMU_GNSR0_S2CR ## n, \
+ .reg = base_addr + SMMU_GNSR0_S2CR ## n, \
.val = 0x00000000U, \
}
-#define smmu_make_gnsr1_cbar_cfg(n) \
+#define smmu_make_gnsr1_cbar_cfg(base_addr, n) \
{ \
- .reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
+ .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
.val = 0x00000000U, \
}
-#define smmu_make_gnsr1_cba2r_cfg(n) \
+#define smmu_make_gnsr1_cba2r_cfg(base_addr, n) \
{ \
- .reg = TEGRA_SMMU0_BASE + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
+ .reg = base_addr + (1U << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
.val = 0x00000000U, \
}
-#define make_smmu_cb_cfg(name, n) \
+#define smmu_make_cb_cfg(base_addr, name, n) \
{ \
- .reg = TEGRA_SMMU0_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
+ .reg = base_addr + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
+ SMMU_CBn_ ## name, \
.val = 0x00000000U, \
}
-#define smmu_make_smrg_group(n) \
- smmu_make_gnsr0_smr_cfg(n), \
- smmu_make_gnsr0_s2cr_cfg(n), \
- smmu_make_gnsr1_cbar_cfg(n), \
- smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */
+#define smmu_make_smrg_group(base_addr, n) \
+ smmu_make_gnsr0_smr_cfg(base_addr, n), \
+ smmu_make_gnsr0_s2cr_cfg(base_addr, n), \
+ smmu_make_gnsr1_cbar_cfg(base_addr, n), \
+ smmu_make_gnsr1_cba2r_cfg(base_addr, n) /* don't put "," here. */
+
+#define smmu_make_cb_group(base_addr, n) \
+ smmu_make_cb_cfg(base_addr, SCTLR, n), \
+ smmu_make_cb_cfg(base_addr, TCR2, n), \
+ smmu_make_cb_cfg(base_addr, TTBR0_LO, n), \
+ smmu_make_cb_cfg(base_addr, TTBR0_HI, n), \
+ smmu_make_cb_cfg(base_addr, TCR, n), \
+ smmu_make_cb_cfg(base_addr, PRRR_MAIR0, n),\
+ smmu_make_cb_cfg(base_addr, FSR, n), \
+ smmu_make_cb_cfg(base_addr, FAR_LO, n), \
+ smmu_make_cb_cfg(base_addr, FAR_HI, n), \
+ smmu_make_cb_cfg(base_addr, FSYNR0, n) /* don't put "," here. */
-#define smmu_make_cb_group(n) \
- make_smmu_cb_cfg(SCTLR, n), \
- make_smmu_cb_cfg(TCR2, n), \
- make_smmu_cb_cfg(TTBR0_LO, n), \
- make_smmu_cb_cfg(TTBR0_HI, n), \
- make_smmu_cb_cfg(TCR, n), \
- make_smmu_cb_cfg(PRRR_MAIR0, n),\
- make_smmu_cb_cfg(FSR, n), \
- make_smmu_cb_cfg(FAR_LO, n), \
- make_smmu_cb_cfg(FAR_HI, n), \
- make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */
+#define smmu_make_cfg(base_addr) \
+ smmu_make_gnsr0_nsec_cfg(base_addr, CR0), \
+ smmu_make_gnsr0_sec_cfg(base_addr, IDR0), \
+ smmu_make_gnsr0_sec_cfg(base_addr, IDR1), \
+ smmu_make_gnsr0_sec_cfg(base_addr, IDR2), \
+ smmu_make_gnsr0_nsec_cfg(base_addr, GFSR), \
+ smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR0), \
+ smmu_make_gnsr0_nsec_cfg(base_addr, GFSYNR1), \
+ smmu_make_gnsr0_nsec_cfg(base_addr, TLBGSTATUS),\
+ smmu_make_gnsr0_nsec_cfg(base_addr, PIDR2), \
+ smmu_make_smrg_group(base_addr, 0), \
+ smmu_make_smrg_group(base_addr, 1), \
+ smmu_make_smrg_group(base_addr, 2), \
+ smmu_make_smrg_group(base_addr, 3), \
+ smmu_make_smrg_group(base_addr, 4), \
+ smmu_make_smrg_group(base_addr, 5), \
+ smmu_make_smrg_group(base_addr, 6), \
+ smmu_make_smrg_group(base_addr, 7), \
+ smmu_make_smrg_group(base_addr, 8), \
+ smmu_make_smrg_group(base_addr, 9), \
+ smmu_make_smrg_group(base_addr, 10), \
+ smmu_make_smrg_group(base_addr, 11), \
+ smmu_make_smrg_group(base_addr, 12), \
+ smmu_make_smrg_group(base_addr, 13), \
+ smmu_make_smrg_group(base_addr, 14), \
+ smmu_make_smrg_group(base_addr, 15), \
+ smmu_make_smrg_group(base_addr, 16), \
+ smmu_make_smrg_group(base_addr, 17), \
+ smmu_make_smrg_group(base_addr, 18), \
+ smmu_make_smrg_group(base_addr, 19), \
+ smmu_make_smrg_group(base_addr, 20), \
+ smmu_make_smrg_group(base_addr, 21), \
+ smmu_make_smrg_group(base_addr, 22), \
+ smmu_make_smrg_group(base_addr, 23), \
+ smmu_make_smrg_group(base_addr, 24), \
+ smmu_make_smrg_group(base_addr, 25), \
+ smmu_make_smrg_group(base_addr, 26), \
+ smmu_make_smrg_group(base_addr, 27), \
+ smmu_make_smrg_group(base_addr, 28), \
+ smmu_make_smrg_group(base_addr, 29), \
+ smmu_make_smrg_group(base_addr, 30), \
+ smmu_make_smrg_group(base_addr, 31), \
+ smmu_make_smrg_group(base_addr, 32), \
+ smmu_make_smrg_group(base_addr, 33), \
+ smmu_make_smrg_group(base_addr, 34), \
+ smmu_make_smrg_group(base_addr, 35), \
+ smmu_make_smrg_group(base_addr, 36), \
+ smmu_make_smrg_group(base_addr, 37), \
+ smmu_make_smrg_group(base_addr, 38), \
+ smmu_make_smrg_group(base_addr, 39), \
+ smmu_make_smrg_group(base_addr, 40), \
+ smmu_make_smrg_group(base_addr, 41), \
+ smmu_make_smrg_group(base_addr, 42), \
+ smmu_make_smrg_group(base_addr, 43), \
+ smmu_make_smrg_group(base_addr, 44), \
+ smmu_make_smrg_group(base_addr, 45), \
+ smmu_make_smrg_group(base_addr, 46), \
+ smmu_make_smrg_group(base_addr, 47), \
+ smmu_make_smrg_group(base_addr, 48), \
+ smmu_make_smrg_group(base_addr, 49), \
+ smmu_make_smrg_group(base_addr, 50), \
+ smmu_make_smrg_group(base_addr, 51), \
+ smmu_make_smrg_group(base_addr, 52), \
+ smmu_make_smrg_group(base_addr, 53), \
+ smmu_make_smrg_group(base_addr, 54), \
+ smmu_make_smrg_group(base_addr, 55), \
+ smmu_make_smrg_group(base_addr, 56), \
+ smmu_make_smrg_group(base_addr, 57), \
+ smmu_make_smrg_group(base_addr, 58), \
+ smmu_make_smrg_group(base_addr, 59), \
+ smmu_make_smrg_group(base_addr, 60), \
+ smmu_make_smrg_group(base_addr, 61), \
+ smmu_make_smrg_group(base_addr, 62), \
+ smmu_make_smrg_group(base_addr, 63), \
+ smmu_make_cb_group(base_addr, 0), \
+ smmu_make_cb_group(base_addr, 1), \
+ smmu_make_cb_group(base_addr, 2), \
+ smmu_make_cb_group(base_addr, 3), \
+ smmu_make_cb_group(base_addr, 4), \
+ smmu_make_cb_group(base_addr, 5), \
+ smmu_make_cb_group(base_addr, 6), \
+ smmu_make_cb_group(base_addr, 7), \
+ smmu_make_cb_group(base_addr, 8), \
+ smmu_make_cb_group(base_addr, 9), \
+ smmu_make_cb_group(base_addr, 10), \
+ smmu_make_cb_group(base_addr, 11), \
+ smmu_make_cb_group(base_addr, 12), \
+ smmu_make_cb_group(base_addr, 13), \
+ smmu_make_cb_group(base_addr, 14), \
+ smmu_make_cb_group(base_addr, 15), \
+ smmu_make_cb_group(base_addr, 16), \
+ smmu_make_cb_group(base_addr, 17), \
+ smmu_make_cb_group(base_addr, 18), \
+ smmu_make_cb_group(base_addr, 19), \
+ smmu_make_cb_group(base_addr, 20), \
+ smmu_make_cb_group(base_addr, 21), \
+ smmu_make_cb_group(base_addr, 22), \
+ smmu_make_cb_group(base_addr, 23), \
+ smmu_make_cb_group(base_addr, 24), \
+ smmu_make_cb_group(base_addr, 25), \
+ smmu_make_cb_group(base_addr, 26), \
+ smmu_make_cb_group(base_addr, 27), \
+ smmu_make_cb_group(base_addr, 28), \
+ smmu_make_cb_group(base_addr, 29), \
+ smmu_make_cb_group(base_addr, 30), \
+ smmu_make_cb_group(base_addr, 31), \
+ smmu_make_cb_group(base_addr, 32), \
+ smmu_make_cb_group(base_addr, 33), \
+ smmu_make_cb_group(base_addr, 34), \
+ smmu_make_cb_group(base_addr, 35), \
+ smmu_make_cb_group(base_addr, 36), \
+ smmu_make_cb_group(base_addr, 37), \
+ smmu_make_cb_group(base_addr, 38), \
+ smmu_make_cb_group(base_addr, 39), \
+ smmu_make_cb_group(base_addr, 40), \
+ smmu_make_cb_group(base_addr, 41), \
+ smmu_make_cb_group(base_addr, 42), \
+ smmu_make_cb_group(base_addr, 43), \
+ smmu_make_cb_group(base_addr, 44), \
+ smmu_make_cb_group(base_addr, 45), \
+ smmu_make_cb_group(base_addr, 46), \
+ smmu_make_cb_group(base_addr, 47), \
+ smmu_make_cb_group(base_addr, 48), \
+ smmu_make_cb_group(base_addr, 49), \
+ smmu_make_cb_group(base_addr, 50), \
+ smmu_make_cb_group(base_addr, 51), \
+ smmu_make_cb_group(base_addr, 52), \
+ smmu_make_cb_group(base_addr, 53), \
+ smmu_make_cb_group(base_addr, 54), \
+ smmu_make_cb_group(base_addr, 55), \
+ smmu_make_cb_group(base_addr, 56), \
+ smmu_make_cb_group(base_addr, 57), \
+ smmu_make_cb_group(base_addr, 58), \
+ smmu_make_cb_group(base_addr, 59), \
+ smmu_make_cb_group(base_addr, 60), \
+ smmu_make_cb_group(base_addr, 61), \
+ smmu_make_cb_group(base_addr, 62), \
+ smmu_make_cb_group(base_addr, 63) /* don't put "," here. */
#define smmu_bypass_cfg \
{ \
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S
index 01ae821..2796c5d 100644
--- a/plat/nvidia/tegra/include/plat_macros.S
+++ b/plat/nvidia/tegra/include/plat_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -50,7 +50,7 @@
bl asm_print_hex
adr x4, spacer
bl asm_print_str
- ldr x4, [x7], #8
+ ldr w4, [x7], #4
bl asm_print_hex
adr x4, newline
bl asm_print_str
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index 0a0126b..f68b898 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,10 +9,15 @@
#include <arch.h>
#include <lib/utils_def.h>
-#include <plat/common/common_def.h>
#include <tegra_def.h>
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
/*******************************************************************************
* Generic platform constants
******************************************************************************/
@@ -54,17 +59,11 @@
#define BL32_LIMIT TZDRAM_END
/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
-
-/*******************************************************************************
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
-#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
+#define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
#endif /* PLATFORM_DEF_H */
diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
index fd75fbc..dfed2aa 100644
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ b/plat/nvidia/tegra/include/t132/tegra_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,12 @@
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
+ * Chip specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
+
+/*******************************************************************************
* GIC memory map
******************************************************************************/
#define TEGRA_GICD_BASE U(0x50041000)
@@ -41,7 +47,9 @@
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
+#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
#define GPU_RESET_BIT (U(1) << 24)
+#define GPU_SET_BIT (U(1) << 24)
/*******************************************************************************
* Tegra Flow Controller constants
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 231f93a..da050a8 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -58,6 +58,12 @@
#define PLAT_MAX_OFF_STATE U(8)
/*******************************************************************************
+ * Chip specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
+
+/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA186_TOP_WDT_IRQ U(49)
@@ -210,7 +216,9 @@
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x05000000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
+#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34)
#define GPU_RESET_BIT (U(1) << 0)
+#define GPU_SET_BIT (U(1) << 0)
#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index 75919e1..bbcfdc5 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,7 +14,6 @@
******************************************************************************/
#define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_CLUSTER_IDLE U(16)
-#define PSTATE_ID_CLUSTER_POWERDN U(17)
#define PSTATE_ID_SOC_POWERDN U(27)
/*******************************************************************************
@@ -33,9 +32,22 @@
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
+ * Chip specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
+
+/*******************************************************************************
+ * SC7 entry firmware's header size
+ ******************************************************************************/
+#define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400)
+
+/*******************************************************************************
* iRAM memory constants
******************************************************************************/
-#define TEGRA_IRAM_BASE 0x40000000
+#define TEGRA_IRAM_BASE U(0x40000000)
+#define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */
+#define TEGRA_IRAM_SIZE U(40000) /* 256KB */
/*******************************************************************************
* GIC memory map
@@ -44,6 +56,11 @@
#define TEGRA_GICC_BASE U(0x50042000)
/*******************************************************************************
+ * Secure IRQ definitions
+ ******************************************************************************/
+#define TEGRA210_WDT_CPU_LEGACY_FIQ U(28)
+
+/*******************************************************************************
* Tegra Memory Select Switch Controller constants
******************************************************************************/
#define TEGRA_MSELECT_BASE U(0x50060000)
@@ -84,21 +101,55 @@
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000)
+#define TEGRA_BOND_OUT_H U(0x74)
+#define APB_DMA_LOCK_BIT (U(1) << 2)
+#define AHB_DMA_LOCK_BIT (U(1) << 1)
+#define TEGRA_BOND_OUT_U U(0x78)
+#define IRAM_D_LOCK_BIT (U(1) << 23)
+#define IRAM_C_LOCK_BIT (U(1) << 22)
+#define IRAM_B_LOCK_BIT (U(1) << 21)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
+#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
#define GPU_RESET_BIT (U(1) << 24)
+#define GPU_SET_BIT (U(1) << 24)
+#define TEGRA_RST_DEV_SET_Y U(0x2a8)
+#define NVENC_RESET_BIT (U(1) << 27)
+#define TSECB_RESET_BIT (U(1) << 14)
+#define APE_RESET_BIT (U(1) << 6)
+#define NVJPG_RESET_BIT (U(1) << 3)
+#define NVDEC_RESET_BIT (U(1) << 2)
+#define TEGRA_RST_DEV_SET_L U(0x300)
+#define HOST1X_RESET_BIT (U(1) << 28)
+#define ISP_RESET_BIT (U(1) << 23)
+#define USBD_RESET_BIT (U(1) << 22)
+#define VI_RESET_BIT (U(1) << 20)
+#define SDMMC4_RESET_BIT (U(1) << 15)
+#define SDMMC1_RESET_BIT (U(1) << 14)
+#define SDMMC2_RESET_BIT (U(1) << 9)
+#define TEGRA_RST_DEV_SET_H U(0x308)
+#define USB2_RESET_BIT (U(1) << 26)
+#define APBDMA_RESET_BIT (U(1) << 2)
+#define AHBDMA_RESET_BIT (U(1) << 1)
+#define TEGRA_RST_DEV_SET_U U(0x310)
+#define XUSB_DEV_RESET_BIT (U(1) << 31)
+#define XUSB_HOST_RESET_BIT (U(1) << 25)
+#define TSEC_RESET_BIT (U(1) << 19)
+#define PCIE_RESET_BIT (U(1) << 6)
+#define SDMMC3_RESET_BIT (U(1) << 5)
+#define TEGRA_RST_DEVICES_V U(0x358)
+#define TEGRA_RST_DEVICES_W U(0x35C)
+#define ENTROPY_CLK_ENB_BIT (U(1) << 21)
+#define TEGRA_CLK_OUT_ENB_V U(0x360)
+#define SE_CLK_ENB_BIT (U(1) << 31)
+#define TEGRA_CLK_OUT_ENB_W U(0x364)
+#define ENTROPY_RESET_BIT (U(1) << 21)
+#define TEGRA_RST_DEV_SET_V U(0x430)
+#define SE_RESET_BIT (U(1) << 31)
+#define HDA_RESET_BIT (U(1) << 29)
+#define SATA_RESET_BIT (U(1) << 28)
#define TEGRA_RST_DEV_CLR_V U(0x434)
#define TEGRA_CLK_ENB_V U(0x440)
-/* SE Clock Offsets */
-#define TEGRA_RST_DEVICES_V 0x358UL
-#define SE_RESET_BIT (0x1UL << 31)
-#define TEGRA_RST_DEVICES_W 0x35CUL
-#define ENTROPY_CLK_ENB_BIT (0x1UL << 21)
-#define TEGRA_CLK_OUT_ENB_V 0x360UL
-#define SE_CLK_ENB_BIT (0x1UL << 31)
-#define TEGRA_CLK_OUT_ENB_W 0x364UL
-#define ENTROPY_RESET_BIT (0x1UL << 21)
-
/*******************************************************************************
* Tegra Flow Controller constants
******************************************************************************/
@@ -124,6 +175,10 @@
******************************************************************************/
#define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET U(0x804)
+#define APB_SLAVE_SECURITY_ENABLE U(0xC00)
+#define PMC_SECURITY_EN_BIT (U(1) << 13)
+#define PINMUX_AUX_DVFS_PWM U(0x3184)
+#define PINMUX_PWM_TRISTATE (U(1) << 4)
/*******************************************************************************
* Tegra UART controller base addresses
@@ -148,6 +203,7 @@
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE U(0x7000E400)
+#define TEGRA_PMC_SIZE U(0xC00) /* 3k */
/*******************************************************************************
* Tegra Atomics constants
@@ -181,6 +237,17 @@
#define PPCS_SMMU_ENABLE (0x1U << 31)
/*******************************************************************************
+ * Tegra CLDVFS constants
+ ******************************************************************************/
+#define TEGRA_CL_DVFS_BASE U(0x70110000)
+#define DVFS_DFLL_CTRL U(0x00)
+#define ENABLE_OPEN_LOOP U(1)
+#define ENABLE_CLOSED_LOOP U(2)
+#define DVFS_DFLL_OUTPUT_CFG U(0x20)
+#define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30)
+#define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6)
+
+/*******************************************************************************
* Tegra SE constants
******************************************************************************/
#define TEGRA_SE1_BASE U(0x70012000)
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 68b4624..cdd9e08 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -46,6 +46,10 @@
int32_t l2_ecc_parity_prot_dis;
/* SHMEM base address for storing the boot logs */
uint64_t boot_profiler_shmem_base;
+ /* System Suspend Entry Firmware size */
+ uint64_t sc7entry_fw_size;
+ /* System Suspend Entry Firmware base address */
+ uint64_t sc7entry_fw_base;
} plat_params_from_bl2_t;
/*******************************************************************************
@@ -97,6 +101,7 @@
void tegra_pm_system_suspend_entry(void);
void tegra_pm_system_suspend_exit(void);
int32_t tegra_system_suspended(void);
+int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index 614d2a2..6ef1900 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -34,6 +34,9 @@
# enable D-cache early during CPU warmboot
WARMBOOT_ENABLE_DCACHE_EARLY := 1
+# remove the standard libc
+OVERRIDE_LIBC := 1
+
include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
@@ -42,3 +45,17 @@
# platform cflags (enable signed comparisons, disable stdlib)
TF_CFLAGS += -Wsign-compare -nostdlib
+
+# override with necessary libc files for the Tegra platform
+override LIBC_SRCS := $(addprefix lib/libc/, \
+ assert.c \
+ memcpy.c \
+ memmove.c \
+ memset.c \
+ printf.c \
+ putchar.c \
+ strlen.c \
+ snprintf.c)
+
+INCLUDES += -Iinclude/lib/libc \
+ -Iinclude/lib/libc/$(ARCH) \
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index 3f9cda9..fef5e0a 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -101,4 +101,5 @@
void plat_gic_setup(void)
{
tegra_gic_setup(NULL, 0);
+ tegra_gic_init();
}
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 376ee86..df94396 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -94,7 +94,7 @@
* Array to hold the security configs for stream IDs
******************************************************************************/
const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
- mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
@@ -109,17 +109,17 @@
mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
@@ -129,20 +129,20 @@
mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
@@ -151,7 +151,7 @@
mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
@@ -162,10 +162,10 @@
mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
};
/*******************************************************************************
@@ -219,9 +219,7 @@
assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
-#if ENABLE_AFI_DEVICE
MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
-#endif
MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
@@ -271,9 +269,7 @@
* MC clients with default SO_DEV override still enabled at TSA:
* AONW, BPMPW, SCEW, APEW
*/
-#if ENABLE_AFI_DEVICE
mc_set_tsa_passthrough(AFIW);
-#endif
mc_set_tsa_passthrough(HDAW);
mc_set_tsa_passthrough(SATAW);
mc_set_tsa_passthrough(XUSB_HOSTW);
@@ -413,9 +409,7 @@
* boot and strongly ordered MSS clients
*/
val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
-#if ENABLE_AFI_DEVICE
mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
-#endif
mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 09e257d..11394c0 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -283,7 +283,7 @@
val = params_from_bl2->tzdram_base +
tegra186_get_cpu_reset_handler_size();
memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
- (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
+ (uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
}
return PSCI_E_SUCCESS;
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index fd109e5..ef0ba4e 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -91,6 +91,8 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
+ MT_DEVICE | MT_RO | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
@@ -194,14 +196,13 @@
void plat_gic_setup(void)
{
tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
+ tegra_gic_init();
/*
* Initialize the FIQ handler only if the platform supports any
* FIQ interrupt sources.
*/
- if (sizeof(tegra186_interrupt_props) > 0U) {
- tegra_fiq_handler_setup();
- }
+ tegra_fiq_handler_setup();
}
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t186/plat_smmu.c b/plat/nvidia/tegra/soc/t186/plat_smmu.c
index 95f6def..b4a7fe5 100644
--- a/plat/nvidia/tegra/soc/t186/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t186/plat_smmu.c
@@ -161,143 +161,7 @@
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(AFIW),
- smmu_make_gnsr0_nsec_cfg(CR0),
- smmu_make_gnsr0_sec_cfg(IDR0),
- smmu_make_gnsr0_sec_cfg(IDR1),
- smmu_make_gnsr0_sec_cfg(IDR2),
- smmu_make_gnsr0_nsec_cfg(GFSR),
- smmu_make_gnsr0_nsec_cfg(GFSYNR0),
- smmu_make_gnsr0_nsec_cfg(GFSYNR1),
- smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
- smmu_make_gnsr0_nsec_cfg(PIDR2),
- smmu_make_smrg_group(0),
- smmu_make_smrg_group(1),
- smmu_make_smrg_group(2),
- smmu_make_smrg_group(3),
- smmu_make_smrg_group(4),
- smmu_make_smrg_group(5),
- smmu_make_smrg_group(6),
- smmu_make_smrg_group(7),
- smmu_make_smrg_group(8),
- smmu_make_smrg_group(9),
- smmu_make_smrg_group(10),
- smmu_make_smrg_group(11),
- smmu_make_smrg_group(12),
- smmu_make_smrg_group(13),
- smmu_make_smrg_group(14),
- smmu_make_smrg_group(15),
- smmu_make_smrg_group(16),
- smmu_make_smrg_group(17),
- smmu_make_smrg_group(18),
- smmu_make_smrg_group(19),
- smmu_make_smrg_group(20),
- smmu_make_smrg_group(21),
- smmu_make_smrg_group(22),
- smmu_make_smrg_group(23),
- smmu_make_smrg_group(24),
- smmu_make_smrg_group(25),
- smmu_make_smrg_group(26),
- smmu_make_smrg_group(27),
- smmu_make_smrg_group(28),
- smmu_make_smrg_group(29),
- smmu_make_smrg_group(30),
- smmu_make_smrg_group(31),
- smmu_make_smrg_group(32),
- smmu_make_smrg_group(33),
- smmu_make_smrg_group(34),
- smmu_make_smrg_group(35),
- smmu_make_smrg_group(36),
- smmu_make_smrg_group(37),
- smmu_make_smrg_group(38),
- smmu_make_smrg_group(39),
- smmu_make_smrg_group(40),
- smmu_make_smrg_group(41),
- smmu_make_smrg_group(42),
- smmu_make_smrg_group(43),
- smmu_make_smrg_group(44),
- smmu_make_smrg_group(45),
- smmu_make_smrg_group(46),
- smmu_make_smrg_group(47),
- smmu_make_smrg_group(48),
- smmu_make_smrg_group(49),
- smmu_make_smrg_group(50),
- smmu_make_smrg_group(51),
- smmu_make_smrg_group(52),
- smmu_make_smrg_group(53),
- smmu_make_smrg_group(54),
- smmu_make_smrg_group(55),
- smmu_make_smrg_group(56),
- smmu_make_smrg_group(57),
- smmu_make_smrg_group(58),
- smmu_make_smrg_group(59),
- smmu_make_smrg_group(60),
- smmu_make_smrg_group(61),
- smmu_make_smrg_group(62),
- smmu_make_smrg_group(63),
- smmu_make_cb_group(0),
- smmu_make_cb_group(1),
- smmu_make_cb_group(2),
- smmu_make_cb_group(3),
- smmu_make_cb_group(4),
- smmu_make_cb_group(5),
- smmu_make_cb_group(6),
- smmu_make_cb_group(7),
- smmu_make_cb_group(8),
- smmu_make_cb_group(9),
- smmu_make_cb_group(10),
- smmu_make_cb_group(11),
- smmu_make_cb_group(12),
- smmu_make_cb_group(13),
- smmu_make_cb_group(14),
- smmu_make_cb_group(15),
- smmu_make_cb_group(16),
- smmu_make_cb_group(17),
- smmu_make_cb_group(18),
- smmu_make_cb_group(19),
- smmu_make_cb_group(20),
- smmu_make_cb_group(21),
- smmu_make_cb_group(22),
- smmu_make_cb_group(23),
- smmu_make_cb_group(24),
- smmu_make_cb_group(25),
- smmu_make_cb_group(26),
- smmu_make_cb_group(27),
- smmu_make_cb_group(28),
- smmu_make_cb_group(29),
- smmu_make_cb_group(30),
- smmu_make_cb_group(31),
- smmu_make_cb_group(32),
- smmu_make_cb_group(33),
- smmu_make_cb_group(34),
- smmu_make_cb_group(35),
- smmu_make_cb_group(36),
- smmu_make_cb_group(37),
- smmu_make_cb_group(38),
- smmu_make_cb_group(39),
- smmu_make_cb_group(40),
- smmu_make_cb_group(41),
- smmu_make_cb_group(42),
- smmu_make_cb_group(43),
- smmu_make_cb_group(44),
- smmu_make_cb_group(45),
- smmu_make_cb_group(46),
- smmu_make_cb_group(47),
- smmu_make_cb_group(48),
- smmu_make_cb_group(49),
- smmu_make_cb_group(50),
- smmu_make_cb_group(51),
- smmu_make_cb_group(52),
- smmu_make_cb_group(53),
- smmu_make_cb_group(54),
- smmu_make_cb_group(55),
- smmu_make_cb_group(56),
- smmu_make_cb_group(57),
- smmu_make_cb_group(58),
- smmu_make_cb_group(59),
- smmu_make_cb_group(60),
- smmu_make_cb_group(61),
- smmu_make_cb_group(62),
- smmu_make_cb_group(63),
+ smmu_make_cfg(TEGRA_SMMU0_BASE),
smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index e3393e9..db69234 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
+#include <common/bl_common.h>
#include <memctrl_v2.h>
#include <plat/common/common_def.h>
#include <tegra_def.h>
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index fdeb886..fe15853 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -1,13 +1,10 @@
#
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# platform configs
-ENABLE_AFI_DEVICE := 1
-$(eval $(call add_define,ENABLE_AFI_DEVICE))
-
ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
@@ -33,7 +30,7 @@
MAX_XLAT_TABLES := 24
$(eval $(call add_define,MAX_XLAT_TABLES))
-MAX_MMAP_REGIONS := 24
+MAX_MMAP_REGIONS := 25
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index f52d975..b7d10af 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,12 +15,14 @@
#include <bpmp.h>
#include <flowctrl.h>
+#include <memctrl.h>
#include <pmc.h>
#include <platform_def.h>
#include <security_engine.h>
#include <tegra_def.h>
#include <tegra_private.h>
#include <tegra_platform.h>
+#include <utils.h>
/*
* Register used to clear CPU reset signals. Each CPU has two reset
@@ -35,11 +37,13 @@
#define SCLK_BURST_POLICY_DEFAULT 0x10000000
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
+static bool tegra_bpmp_available = true;
int32_t tegra_soc_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int state_id = psci_get_pstate_id(power_state);
+ const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
/* Sanity check the requested state id */
switch (state_id) {
@@ -52,16 +56,24 @@
break;
case PSTATE_ID_CLUSTER_IDLE:
- case PSTATE_ID_CLUSTER_POWERDN:
+
/*
- * Cluster powerdown/idle request only for afflvl 1
+ * Cluster idle request for afflvl 0
*/
- req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN;
-
+ req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
break;
case PSTATE_ID_SOC_POWERDN:
+
+ /*
+ * sc7entry-fw must be present in the system when the bpmp
+ * firmware is not present, for a successful System Suspend
+ * entry.
+ */
+ if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base)
+ return PSCI_E_NOT_SUPPORTED;
+
/*
* System powerdown request only for afflvl 2
*/
@@ -83,7 +95,7 @@
/*******************************************************************************
* Platform handler to calculate the proper target power level at the
- * specified affinity level
+ * specified affinity level.
******************************************************************************/
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states,
@@ -92,7 +104,7 @@
plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
int cpu = plat_my_core_pos();
int core_pos = read_mpidr() & MPIDR_CPU_MASK;
- uint32_t bpmp_reply, data[3];
+ uint32_t bpmp_reply, data[3], val;
int ret;
/* get the power state at this level */
@@ -107,40 +119,44 @@
ret = tegra_bpmp_init();
if (ret != 0U) {
+ /*
+ * flag to indicate that BPMP firmware is not
+ * available and the CPU has to handle entry/exit
+ * for all power states
+ */
+ tegra_bpmp_available = false;
+
/* Cluster idle not allowed */
target = PSCI_LOCAL_STATE_RUN;
- } else {
- /* Cluster idle */
- data[0] = (uint32_t)cpu;
- data[1] = TEGRA_PM_CC6;
- data[2] = TEGRA_PM_SC1;
- ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
- (void *)&data, (int)sizeof(data),
- (void *)&bpmp_reply,
- (int)sizeof(bpmp_reply));
+ /*******************************************
+ * BPMP is not present, so handle CC6 entry
+ * from the CPU
+ ******************************************/
- /* check if cluster idle entry is allowed */
- if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
+ /* check if cluster idle state has been enabled */
+ val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL);
+ if (val == ENABLE_CLOSED_LOOP) {
+ /*
+ * Acquire the cluster idle lock to stop
+ * other CPUs from powering up.
+ */
+ tegra_fc_ccplex_pgexit_lock();
- /* Cluster idle not allowed */
- target = PSCI_LOCAL_STATE_RUN;
+ /* Cluster idle only from the last standing CPU */
+ if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) {
+ /* Cluster idle allowed */
+ target = PSTATE_ID_CLUSTER_IDLE;
+ } else {
+ /* release cluster idle lock */
+ tegra_fc_ccplex_pgexit_unlock();
+ }
}
- }
-
- } else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) {
-
- /* initialize the bpmp interface */
- ret = tegra_bpmp_init();
- if (ret != 0U) {
-
- /* Cluster power down not allowed */
- target = PSCI_LOCAL_STATE_RUN;
} else {
/* Cluster power-down */
data[0] = (uint32_t)cpu;
- data[1] = TEGRA_PM_CC7;
+ data[1] = TEGRA_PM_CC6;
data[2] = TEGRA_PM_SC1;
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
(void *)&data, (int)sizeof(data),
@@ -176,7 +192,9 @@
unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2];
unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1];
unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0];
+ uint32_t cfg;
int ret = PSCI_E_SUCCESS;
+ uint32_t val;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
@@ -197,15 +215,42 @@
assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN);
- /* Prepare for cluster idle */
- tegra_fc_cluster_idle(mpidr);
+ if (!tegra_bpmp_available) {
- } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) {
+ /*
+ * When disabled, DFLL loses its state. Enable
+ * open loop state for the DFLL as we dont want
+ * garbage values being written to the pmic
+ * when we enter cluster idle state.
+ */
+ mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
+ ENABLE_OPEN_LOOP);
- assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN);
+ /* Find if the platform uses OVR2/MAX77621 PMIC */
+ cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
+ if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
+ /* OVR2 */
+
+ /* PWM tristate */
+ val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
+ val |= PINMUX_PWM_TRISTATE;
+ mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
+
+ /*
+ * SCRATCH201[1] is being used to identify CPU
+ * PMIC in warmboot code.
+ * 0 : OVR2
+ * 1 : MAX77621
+ */
+ tegra_pmc_write_32(PMC_SCRATCH201, 0x0);
+ } else {
+ /* MAX77621 */
+ tegra_pmc_write_32(PMC_SCRATCH201, 0x2);
+ }
+ }
- /* Prepare for cluster powerdn */
- tegra_fc_cluster_powerdn(mpidr);
+ /* Prepare for cluster idle */
+ tegra_fc_cluster_idle(mpidr);
} else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
@@ -221,12 +266,82 @@
return ret;
}
+static void tegra_reset_all_dma_masters(void)
+{
+ uint32_t val, mask;
+
+ /*
+ * Reset all possible DMA masters in the system.
+ */
+ val = GPU_RESET_BIT;
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val);
+
+ val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
+ NVJPG_RESET_BIT | NVDEC_RESET_BIT;
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val);
+
+ val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
+ VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
+ SDMMC2_RESET_BIT;
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val);
+
+ val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val);
+
+ val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
+ PCIE_RESET_BIT | SDMMC3_RESET_BIT;
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val);
+
+ val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val);
+
+ /*
+ * If any of the DMA masters are still alive, assume
+ * that the system has been compromised and reboot.
+ */
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
+ mask = GPU_RESET_BIT;
+ if ((val & mask) != mask)
+ tegra_pmc_system_reset();
+
+ mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
+ NVJPG_RESET_BIT | NVDEC_RESET_BIT;
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y);
+ if ((val & mask) != mask)
+ tegra_pmc_system_reset();
+
+ mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
+ VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
+ SDMMC2_RESET_BIT;
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L);
+ if ((val & mask) != mask)
+ tegra_pmc_system_reset();
+
+ mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H);
+ if ((val & mask) != mask)
+ tegra_pmc_system_reset();
+
+ mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
+ PCIE_RESET_BIT | SDMMC3_RESET_BIT;
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U);
+ if ((val & mask) != mask)
+ tegra_pmc_system_reset();
+
+ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V);
+ mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
+ if ((val & mask) != mask)
+ tegra_pmc_system_reset();
+}
+
int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
u_register_t mpidr = read_mpidr();
const plat_local_state_t *pwr_domain_state =
target_state->pwr_domain_state;
unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL];
+ const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+ uint32_t val;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
@@ -235,6 +350,61 @@
tegra_se_save_tzram();
}
+ /* de-init the interface */
+ tegra_bpmp_suspend();
+
+ /*
+ * The CPU needs to load the System suspend entry firmware
+ * if nothing is running on the BPMP.
+ */
+ if (!tegra_bpmp_available) {
+
+ /*
+ * BPMP firmware is not running on the co-processor, so
+ * we need to explicitly load the firmware to enable
+ * entry/exit to/from System Suspend and set the BPMP
+ * on its way.
+ */
+
+ /* Power off BPMP before we proceed */
+ tegra_fc_bpmp_off();
+
+ /* bond out IRAM banks B, C and D */
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U,
+ IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT |
+ IRAM_D_LOCK_BIT);
+
+ /* bond out APB/AHB DMAs */
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H,
+ APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT);
+
+ /* Power off BPMP before we proceed */
+ tegra_fc_bpmp_off();
+
+ /*
+ * Reset all the hardware blocks that can act as DMA
+ * masters on the bus.
+ */
+ tegra_reset_all_dma_masters();
+
+ /* clean up IRAM of any cruft */
+ zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
+ TEGRA_IRAM_A_SIZE);
+
+ /* Copy the firmware to BPMP's internal RAM */
+ (void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE,
+ (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES),
+ plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES);
+
+ /* Power on the BPMP and execute from IRAM base */
+ tegra_fc_bpmp_on(TEGRA_IRAM_BASE);
+
+ /* Wait until BPMP powers up */
+ do {
+ val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
+ } while (val != SIGN_OF_LIFE);
+ }
+
/* enter system suspend */
tegra_fc_soc_powerdn(mpidr);
}
@@ -245,7 +415,9 @@
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
- uint32_t val;
+ uint32_t cfg;
+ uint32_t val, entrypoint = 0;
+ uint64_t offset;
/* platform parameter passed by the previous bootloader */
if (plat_params->l2_ecc_parity_prot_dis != 1) {
@@ -284,18 +456,76 @@
/*
* Restore Boot and Power Management Processor (BPMP) reset
- * address and reset it.
+ * address and reset it, if it is supported by the platform.
*/
- tegra_fc_reset_bpmp();
+ if (!tegra_bpmp_available) {
+ tegra_fc_bpmp_off();
+ } else {
+ entrypoint = tegra_pmc_read_32(PMC_SCRATCH39);
+ tegra_fc_bpmp_on(entrypoint);
+
+ /* initialise the interface */
+ tegra_bpmp_resume();
+ }
+
+ /* sc7entry-fw is part of TZDRAM area */
+ if (plat_params->sc7entry_fw_base != 0U) {
+ offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
+ tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
+ plat_params->tzdram_size + offset);
+
+ /* restrict PMC access to secure world */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val |= PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+ }
}
/*
+ * Check if we are exiting cluster idle state
+ */
+ if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
+ PSTATE_ID_CLUSTER_IDLE) {
+
+ if (!tegra_bpmp_available) {
+
+ /* PWM un-tristate */
+ cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
+ if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
+ val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
+ val &= ~PINMUX_PWM_TRISTATE;
+ mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
+
+ /* make sure the setting took effect */
+ val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
+ assert((val & PINMUX_PWM_TRISTATE) == 0U);
+ }
+
+ /*
+ * Restore operation mode for the DFLL ring
+ * oscillator
+ */
+ mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
+ ENABLE_CLOSED_LOOP);
+
+ /* release cluster idle lock */
+ tegra_fc_ccplex_pgexit_unlock();
+ }
+ }
+
+ /*
* T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
* used for power management and boot purposes. Inform the BPMP that
* we have completed the cluster power up.
*/
tegra_fc_lock_active_cluster();
+ /*
+ * Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
+ */
+ if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
+ tegra_pmc_resume();
+
return PSCI_E_SUCCESS;
}
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index 6246dde..4a42644 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -1,15 +1,24 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
-#include <bpmp.h>
+#include <assert.h>
#include <cortex_a57.h>
#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/interrupt_props.h>
#include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv2.h>
+#include <bl31/interrupt_mgmt.h>
+
+#include <bpmp.h>
+#include <flowctrl.h>
+#include <memctrl.h>
#include <platform.h>
#include <security_engine.h>
#include <tegra_def.h>
@@ -137,10 +146,76 @@
}
}
+/* Secure IRQs for Tegra186 */
+static const interrupt_prop_t tegra210_interrupt_props[] = {
+ INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
+};
+
+void plat_late_platform_setup(void)
+{
+ const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+ uint64_t sc7entry_end, offset;
+ int ret;
+ uint32_t val;
+
+ /* memmap TZDRAM area containing the SC7 Entry Firmware */
+ if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
+
+ assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
+
+ /*
+ * Verify that the SC7 entry firmware resides inside the TZDRAM
+ * aperture, _before_ the BL31 code and the start address is
+ * exactly 1MB from BL31 base.
+ */
+
+ /* sc7entry-fw must be _before_ BL31 base */
+ assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);
+
+ sc7entry_end = plat_params->sc7entry_fw_base +
+ plat_params->sc7entry_fw_size;
+ assert(sc7entry_end < plat_params->tzdram_base);
+
+ /* sc7entry-fw start must be exactly 1MB behind BL31 base */
+ offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
+ assert(offset == 0x100000);
+
+ /* secure TZDRAM area */
+ tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
+ plat_params->tzdram_size + offset);
+
+ /* power off BPMP processor until SC7 entry */
+ tegra_fc_bpmp_off();
+
+ /* memmap SC7 entry firmware code */
+ ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
+ plat_params->sc7entry_fw_base,
+ plat_params->sc7entry_fw_size,
+ MT_SECURE | MT_RO_DATA);
+ assert(ret == 0);
+
+ /* restrict PMC access to secure world */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val |= PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+ }
+}
+
/*******************************************************************************
* Initialize the GIC and SGIs
******************************************************************************/
void plat_gic_setup(void)
{
- tegra_gic_setup(NULL, 0);
+ tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props));
+ tegra_gic_init();
+
+ /* Enable handling for FIQs */
+ tegra_fiq_handler_setup();
+
+ /*
+ * Enable routing watchdog FIQs from the flow controller to
+ * the GICD.
+ */
+ tegra_fc_enable_fiq_to_ccplex_routing();
}
diff --git a/plat/nvidia/tegra/soc/t210/plat_sip_calls.c b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
new file mode 100644
index 0000000..0e8900e
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t210/plat_sip_calls.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <errno.h>
+#include <mmio.h>
+#include <utils_def.h>
+
+#include <memctrl.h>
+#include <pmc.h>
+#include <tegra_private.h>
+#include <tegra_platform.h>
+#include <tegra_def.h>
+
+/*******************************************************************************
+ * PMC parameters
+ ******************************************************************************/
+#define PMC_READ U(0xaa)
+#define PMC_WRITE U(0xbb)
+
+/*******************************************************************************
+ * Tegra210 SiP SMCs
+ ******************************************************************************/
+#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00)
+
+/*******************************************************************************
+ * This function is responsible for handling all T210 SiP calls
+ ******************************************************************************/
+int plat_sip_handler(uint32_t smc_fid,
+ uint64_t x1,
+ uint64_t x2,
+ uint64_t x3,
+ uint64_t x4,
+ const void *cookie,
+ void *handle,
+ uint64_t flags)
+{
+ uint32_t val, ns;
+
+ /* Determine which security state this SMC originated from */
+ ns = is_caller_non_secure(flags);
+ if (!ns)
+ SMC_RET1(handle, SMC_UNK);
+
+ switch (smc_fid) {
+ case TEGRA_SIP_PMC_COMMANDS:
+
+ /* check the address is within PMC range and is 4byte aligned */
+ if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3))
+ return -EINVAL;
+
+ /* pmc_secure_scratch registers are not accessible */
+ if (((x2 >= PMC_SECURE_SCRATCH0) && (x2 <= PMC_SECURE_SCRATCH5)) ||
+ ((x2 >= PMC_SECURE_SCRATCH6) && (x2 <= PMC_SECURE_SCRATCH7)) ||
+ ((x2 >= PMC_SECURE_SCRATCH8) && (x2 <= PMC_SECURE_SCRATCH79)) ||
+ ((x2 >= PMC_SECURE_SCRATCH80) && (x2 <= PMC_SECURE_SCRATCH119)))
+ return -EFAULT;
+
+ /* PMC secure-only registers are not accessible */
+ if ((x2 == PMC_DPD_ENABLE_0) || (x2 == PMC_FUSE_CONTROL_0) ||
+ (x2 == PMC_CRYPTO_OP_0))
+ return -EFAULT;
+
+ /* Perform PMC read/write */
+ if (x1 == PMC_READ) {
+ val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2));
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val);
+ } else if (x1 == PMC_WRITE) {
+ mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3);
+ } else {
+ return -EINVAL;
+ }
+
+ break;
+
+ default:
+ ERROR("%s: unsupported function ID\n", __func__);
+ return -ENOTSUP;
+ }
+
+ return 0;
+}
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index e23d7e3..a11aef4 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -19,9 +19,12 @@
MAX_XLAT_TABLES := 10
$(eval $(call add_define,MAX_XLAT_TABLES))
-MAX_MMAP_REGIONS := 15
+MAX_MMAP_REGIONS := 16
$(eval $(call add_define,MAX_MMAP_REGIONS))
+ENABLE_WDT_LEGACY_FIQ_HANDLING := 1
+$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+
PLAT_INCLUDES += -I${SOC_DIR}/drivers/se
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
@@ -33,7 +36,8 @@
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/drivers/se/security_engine.c \
- ${SOC_DIR}/plat_secondary.c
+ ${SOC_DIR}/plat_secondary.c \
+ ${SOC_DIR}/plat_sip_calls.c
# Enable workarounds for selected Cortex-A57 erratas.
A57_DISABLE_NON_TEMPORAL_HINT := 1
@@ -48,3 +52,6 @@
ERRATA_A53_826319 := 1
ERRATA_A53_836870 := 1
ERRATA_A53_855873 := 1
+
+# Skip L1 $ flush when powering down Cortex-A57 CPUs
+SKIP_A57_L1_FLUSH_PWR_DWN := 1
diff --git a/services/spd/tlkd/tlkd_common.c b/services/spd/tlkd/tlkd_common.c
index 2f0194e..dbe6c2e 100644
--- a/services/spd/tlkd/tlkd_common.c
+++ b/services/spd/tlkd/tlkd_common.c
@@ -126,7 +126,6 @@
/* Passing a NULL context is a critical programming error */
assert(tlk_ctx);
- assert(tlk_ctx->c_rt_ctx == 0);
/* Apply the Secure EL1 system register context and switch to it */
assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx);
diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index b1a0477..f6f2af5 100644
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -195,14 +195,18 @@
* b. register shared memory with the SP for passing args
* required for maintaining sessions with the Trusted
* Applications.
- * c. register non-secure world's memory map with the OS
- * d. open/close sessions
- * e. issue commands to the Trusted Apps
- * f. resume the preempted yielding SMC call.
+ * c. register shared persistent buffers for secure storage
+ * d. register NS DRAM ranges passed by Cboot
+ * e. register Root of Trust parameters from Cboot for Verified Boot
+ * f. open/close sessions
+ * g. issue commands to the Trusted Apps
+ * h. resume the preempted yielding SMC call.
*/
case TLK_REGISTER_LOGBUF:
case TLK_REGISTER_REQBUF:
- case TLK_REGISTER_NS_DRAM:
+ case TLK_SS_REGISTER_HANDLER:
+ case TLK_REGISTER_NS_DRAM_RANGES:
+ case TLK_SET_ROOT_OF_TRUST:
case TLK_OPEN_TA_SESSION:
case TLK_CLOSE_TA_SESSION:
case TLK_TA_LAUNCH_OP:
@@ -400,6 +404,7 @@
SMC_RET2(handle, TLK_VERSION_MAJOR, TLK_VERSION_MINOR);
default:
+ WARN("%s: Unhandled SMC: 0x%x\n", __func__, smc_fid);
break;
}
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index 83c14b4..b059a43 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <stdbool.h>
#include <string.h>
+#include <xlat_tables_v2.h>
#include <arch_helpers.h>
#include <bl31/bl31.h>
@@ -352,32 +353,32 @@
}
}
-static int32_t trusty_cpu_off_handler(u_register_t unused)
+static int32_t trusty_cpu_off_handler(u_register_t max_off_lvl)
{
- trusty_cpu_suspend(1);
+ trusty_cpu_suspend(max_off_lvl);
return 0;
}
-static void trusty_cpu_on_finish_handler(u_register_t unused)
+static void trusty_cpu_on_finish_handler(u_register_t max_off_lvl)
{
struct trusty_cpu_ctx *ctx = get_trusty_ctx();
if (ctx->saved_sp == NULL) {
(void)trusty_init();
} else {
- trusty_cpu_resume(1);
+ trusty_cpu_resume(max_off_lvl);
}
}
-static void trusty_cpu_suspend_handler(u_register_t unused)
+static void trusty_cpu_suspend_handler(u_register_t max_off_lvl)
{
- trusty_cpu_suspend(0);
+ trusty_cpu_suspend(max_off_lvl);
}
-static void trusty_cpu_suspend_finish_handler(u_register_t unused)
+static void trusty_cpu_suspend_finish_handler(u_register_t max_off_lvl)
{
- trusty_cpu_resume(0);
+ trusty_cpu_resume(max_off_lvl);
}
static const spd_pm_ops_t trusty_pm = {
@@ -412,6 +413,14 @@
return -1;
}
+ /* memmap first page of trusty's code memory before peeking */
+ ret = mmap_add_dynamic_region(ep_info->pc, /* PA */
+ ep_info->pc, /* VA */
+ PAGE_SIZE, /* size */
+ MT_SECURE | MT_RW_DATA); /* attrs */
+ assert(ret == 0);
+
+ /* peek into trusty's code to see if we have a 32-bit or 64-bit image */
instr = *(uint32_t *)ep_info->pc;
if (instr >> 24 == 0xeaU) {
@@ -424,6 +433,9 @@
return -1;
}
+ /* unmap trusty's memory page */
+ (void)mmap_remove_dynamic_region(ep_info->pc, PAGE_SIZE);
+
SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
if (!aarch32)
ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
diff --git a/services/spd/trusty/trusty.mk b/services/spd/trusty/trusty.mk
index a571fa2..4f0c294 100644
--- a/services/spd/trusty/trusty.mk
+++ b/services/spd/trusty/trusty.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -13,6 +13,8 @@
SPD_SOURCES += services/spd/trusty/generic-arm64-smcall.c
endif
+BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+
NEED_BL32 := yes
CTX_INCLUDE_FPREGS := 1