zynqmp: pm: Reimplement clock disable EEMI API
Clock disable EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock disable API to reset the PLL in the
implementation of pm_clock_disable() we need to workaround this by
distinguishing two cases: 1) if the given clock ID corresponds to a PLL
output clock ID; or 2) given clock ID is truly an on-chip clock that can
be gated.
For case 1) we'll call pm_api_clock_pll_disable() implemented in
pm_api_clock.h/c. This function will reset the PLL using the system-level
PLL set mode EEMI API with the reset mode argument.
For case 2) we'll call the PMU to configure the clock gate. This is done
using system-level clock disable EEMI API.
Functions that appear to be unused after this change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
index ee8b387..542dbdc 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c
@@ -2627,58 +2627,6 @@
}
/**
- * pm_api_clk_enable_disable() - Enable/Disable the clock for given id
- * @clock_id: Id of the clock to be enabled
- * @enable: Enable(1)/Disable(0)
- *
- * This function is to enable/disable the clock which is not PLL.
- *
- * Return: Returns status, either success or error+reason.
- */
-static enum pm_ret_status pm_api_clk_enable_disable(unsigned int clock_id,
- unsigned int enable)
-{
- enum pm_ret_status ret = PM_RET_SUCCESS;
- struct pm_clock_node *nodes = *clocks[clock_id].nodes;
- uint8_t num_nodes = clocks[clock_id].num_nodes;
- unsigned int reg, val;
- uint8_t i = 0;
- uint8_t offset = NA_SHIFT, width = NA_WIDTH;
-
- if (clock_id == CLK_GEM0_TX || clock_id == CLK_GEM1_TX ||
- clock_id == CLK_GEM2_TX || clock_id == CLK_GEM3_TX)
- reg = clocks[clock_id].status_reg;
- else
- reg = clocks[clock_id].control_reg;
-
- for (i = 0; i < num_nodes; i++) {
- if (nodes->type == TYPE_GATE) {
- offset = nodes->offset;
- width = nodes->width;
- break;
- }
- nodes++;
- }
- if (width == NA_WIDTH)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- ret = pm_mmio_read(reg, &val);
- if (ret != PM_RET_SUCCESS)
- return ret;
- if ((val & BIT_MASK(offset, width)) == enable)
- return PM_RET_SUCCESS;
-
- if (enable == 0)
- val &= ~(BIT_MASK(offset, width));
- else
- val |= BIT_MASK(offset, width);
-
- ret = pm_mmio_write(reg, BIT_MASK(offset, width), val);
-
- return ret;
-}
-
-/**
* pm_clock_pll_enable() - "Enable" the PLL clock (lock the PLL)
* @pll: PLL to be locked
*
@@ -2700,33 +2648,20 @@
}
/**
- * pm_api_clock_disable - Disable the clock for given id
- * @clock_id Id of the clock to be disable
+ * pm_clock_pll_disable - "Disable" the PLL clock (bypass/reset the PLL)
+ * @pll PLL to be bypassed/reset
*
- * This function is used by master to disable the clock
- * including peripherals and PLL clocks.
+ * This function is used to map IOCTL/linux-based PLL handling to system-level
+ * EEMI APIs
*
- * Return: Returns status, either success or error+reason.
+ * Return: Error if the argument is not valid or status as returned by PMU
*/
-
-enum pm_ret_status pm_api_clock_disable(unsigned int clock_id)
+enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll)
{
- enum pm_ret_status ret = PM_RET_SUCCESS;
-
- if (!pm_clock_valid(clock_id))
+ if (!pll)
return PM_RET_ERROR_ARGS;
- if (pm_clock_type(clock_id) != CLK_TYPE_OUTPUT)
- return PM_RET_ERROR_NOTSUPPORTED;
-
- /*
- * PLL type clock should not be disabled explicitly.
- * It is done by PMUFW if required.
- */
- if (!ISPLL(clock_id))
- ret = pm_api_clk_enable_disable(clock_id, 0);
-
- return ret;
+ return pm_pll_set_mode(pll->nid, PM_PLL_MODE_RESET);
}
/**
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
index ab7a8a4..5ec4d74 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h
@@ -296,7 +296,7 @@
enum pm_ret_status pm_clock_id_is_valid(unsigned int clock_id);
enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll);
-enum pm_ret_status pm_api_clock_disable(unsigned int clock_id);
+enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll);
enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
unsigned int *state);
enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index e33761c..fe5828e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -903,12 +903,20 @@
* This function is used by master to disable the clock
* including peripherals and PLL clocks.
*
- * Return: Returns status, either success or error+reason.
+ * @return: Error if an argument is not valid or status as returned by the
+ * pm_clock_gate
*/
-
enum pm_ret_status pm_clock_disable(unsigned int clock_id)
{
- return pm_api_clock_disable(clock_id);
+ struct pm_pll *pll;
+
+ /* First try to handle it as a PLL */
+ pll = pm_clock_get_pll(clock_id);
+ if (pll)
+ return pm_clock_pll_disable(pll);
+
+ /* It's an on-chip clock, PMU should configure clock's gate */
+ return pm_clock_gate(clock_id, 0);
}
/**