Merge pull request #337 from vwadekar/tegra-misc-fixes-v3
Tegra misc fixes v3
diff --git a/docs/user-guide.md b/docs/user-guide.md
index 470c69f..006340b 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -6,22 +6,25 @@
1. [Introduction](#1--introduction)
2. [Host machine requirements](#2--host-machine-requirements)
3. [Tools](#3--tools)
-4. [Building the Trusted Firmware](#4--building-the-trusted-firmware)
-5. [Obtaining the normal world software](#5--obtaining-the-normal-world-software)
-6. [Preparing the images to run on FVP](#6--preparing-the-images-to-run-on-fvp)
-7. [Running the software on FVP](#7--running-the-software-on-fvp)
-8. [Running the software on Juno](#8--running-the-software-on-juno)
+4. [Getting the Trusted Firmware source code](#4--getting-the-trusted-firmware-source-code)
+5. [Building the Trusted Firmware](#5--building-the-trusted-firmware)
+6. [Building the rest of the software stack](#6--building-the-rest-of-the-software-stack)
+7. [Preparing the images to run on FVP](#7--preparing-the-images-to-run-on-fvp)
+8. [Running the software on FVP](#8--running-the-software-on-fvp)
+9. [Running the software on Juno](#9--running-the-software-on-juno)
1. Introduction
----------------
+
This document describes how to build ARM Trusted Firmware and run it with a
tested set of other software components using defined configurations on the Juno
ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is
possible to use other software components, configurations and platforms but that
is outside the scope of this document.
-This document should be used in conjunction with the [Firmware Design].
+This document should be used in conjunction with the [Firmware Design] and the
+[Linaro release notes][Linaro releases].
2. Host machine requirements
@@ -32,57 +35,79 @@
RAM. For best performance, use a machine with a quad-core processor running at
2.6GHz with 16GB of RAM.
-The software has been tested on Ubuntu 12.04.04 (64-bit). Packages used
-for building the software were installed from that distribution unless
-otherwise specified.
-
+The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for
+building the software were installed from that distribution unless otherwise
+specified.
3. Tools
---------
-The following tools are required to use the ARM Trusted Firmware:
-
-* `git` package to obtain source code.
-
-* `build-essential`, `uuid-dev` and `iasl` packages for building UEFI and the
- Firmware Image Package (FIP) tool.
-
-* `bc` and `ncurses-dev` packages for building Linux.
+In addition to the prerequisite tools listed on the
+[Linaro release notes][Linaro releases], the following tools are needed to use
+the ARM Trusted Firmware:
* `device-tree-compiler` package for building the Flattened Device Tree (FDT)
source files (`.dts` files) provided with this software.
-* Baremetal GNU GCC tools. Verified packages can be downloaded from [Linaro]
- [Linaro Toolchain]. The rest of this document assumes that the
- `gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz` tools are used.
-
- wget http://releases.linaro.org/14.07/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz
- tar -xf gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz
-
* `libssl-dev` package to build the certificate generation tool when support
for Trusted Board Boot is needed.
* (Optional) For debugging, ARM [Development Studio 5 (DS-5)][DS-5] v5.21.
-4. Building the Trusted Firmware
----------------------------------
+4. Getting the Trusted Firmware source code
+--------------------------------------------
+
+The Trusted Firmware source code can be obtained as part of the standard Linaro
+releases, which provide a full software stack, including the Trusted Firmware,
+normal world firmware, Linux kernel and device tree, file system as well as any
+additional micro-controller firmware required by the platform. Please follow the
+instructions on the [Linaro release notes][Linaro releases], section 2.2
+"Downloading the software sources" and section 2.3 "Downloading the filesystem
+binaries".
+
+Note: Both the LSK kernel or the latest tracking kernel can be used along the
+ARM Trusted Firmware, choose the one that best suits your needs.
-To build the Trusted Firmware images, follow these steps:
+The Trusted Firmware source code can then be found in the `arm-tf/` directory.
+This is the full git repository cloned from Github. The revision checked out by
+the `repo` tool is indicated by the manifest file. Depending on the manifest
+file you're using, this might not be the latest development version. To
+synchronize your copy of the repository and get the latest updates, use the
+following commands:
-1. Clone the ARM Trusted Firmware repository from GitHub:
+ # Change to the Trusted Firmware directory.
+ cd arm-tf
- git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ # Download the latest code from Github.
+ git fetch github
-2. Change to the trusted firmware directory:
+ # Update your working copy to the latest master.
+ # This command will create a local branch master that tracks the remote
+ # branch master from Github.
+ git checkout --track github/master
- cd arm-trusted-firmware
-3. Set the compiler path, specify a Non-trusted Firmware image (BL3-3) and
+Alternatively, the Trusted Firmware source code can be fetched on its own
+from GitHub:
+
+ git clone https://github.com/ARM-software/arm-trusted-firmware.git
+
+However, the rest of this document assumes that you got the Trusted Firmware
+as part of the Linaro release.
+
+
+5. Building the Trusted Firmware
+---------------------------------
+
+To build the Trusted Firmware images, change to the root directory of the
+Trusted Firmware source tree and follow these steps:
+
+1. Set the compiler path, specify a Non-trusted Firmware image (BL3-3) and
a valid platform, and then build:
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- BL33=<path-to>/<bl33_image> \
+ CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
+ BL33=<path-to>/<bl33_image> \
make PLAT=<platform> all fip
If `PLAT` is not specified, `fvp` is assumed by default. See the "Summary of
@@ -90,7 +115,7 @@
The BL3-3 image corresponds to the software that is executed after switching
to the non-secure world. UEFI can be used as the BL3-3 image. Refer to the
- "Obtaining the normal world software" section below.
+ "Building the rest of the software stack" section below.
The TSP (Test Secure Payload), corresponding to the BL3-2 image, is not
compiled in by default. Refer to the "Building the Test Secure Payload"
@@ -118,17 +143,17 @@
For more information on FIPs, see the "Firmware Image Package" section in
the [Firmware Design].
-4. (Optional) Some platforms may require a BL3-0 image to boot. This image can
+2. (Optional) Some platforms may require a BL3-0 image to boot. This image can
be included in the FIP when building the Trusted Firmware by specifying the
`BL30` build option:
BL30=<path-to>/<bl30_image>
-5. Output binary files `bl1.bin` and `fip.bin` are both required to boot the
+3. Output binary files `bl1.bin` and `fip.bin` are both required to boot the
system. How these files are used is platform specific. Refer to the
platform documentation on how to use the firmware images.
-6. (Optional) Build products for a specific build variant can be removed using:
+4. (Optional) Build products for a specific build variant can be removed using:
make DEBUG=<D> PLAT=<platform> clean
@@ -138,7 +163,7 @@
make realclean
-7. (Optional) Path to binary for certain BL stages (BL2, BL3-1 and BL3-2) can be
+5. (Optional) Path to binary for certain BL stages (BL2, BL3-1 and BL3-2) can be
provided by specifying the BLx=<path-to>/<blx_image> where BLx is the BL stage.
This will bypass the build of the BL component from source, but will include
the specified binary in the final FIP image. Please note that BL3-2 will be
@@ -424,8 +449,8 @@
To compile a debug version and make the build more verbose use
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- BL33=<path-to>/<bl33_image> \
+ CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
+ BL33=<path-to>/<bl33_image> \
make PLAT=<platform> DEBUG=1 V=1 all fip
AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for
@@ -443,9 +468,9 @@
Extra debug options can be passed to the build system by setting `CFLAGS`:
- CFLAGS='-O0 -gdwarf-2' \
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- BL33=<path-to>/<bl33_image> \
+ CFLAGS='-O0 -gdwarf-2' \
+ CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
+ BL33=<path-to>/<bl33_image> \
make PLAT=<platform> DEBUG=1 V=1 all fip
@@ -459,8 +484,8 @@
First clean the Trusted Firmware build directory to get rid of any previous
BL3-1 binary. Then to build the TSP image and include it into the FIP use:
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- BL33=<path-to>/<bl33_image> \
+ CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
+ BL33=<path-to>/<bl33_image> \
make PLAT=<platform> SPD=tspd all fip
An additional boot loader binary file is created in the `build` directory:
@@ -546,7 +571,7 @@
Example of command line using RSA development keys:
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
+ CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-linux-gnu- \
BL33=<path-to>/<bl33_image> \
MBEDTLS_DIR=<path of the directory containing mbedTLS sources> \
make PLAT=<platform> TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \
@@ -582,122 +607,72 @@
set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT`
is set to `origin/master`.
-
-5. Obtaining the normal world software
----------------------------------------
-
-### Obtaining EDK2
-Potentially any kind of non-trusted firmware may be used with the ARM Trusted
-Firmware but the software has only been tested with the EFI Development Kit 2
-(EDK2) open source implementation of the UEFI specification.
+6. Building the rest of the software stack
+-------------------------------------------
-To build the software to be compatible with the Foundation and Base FVPs, or the
-Juno platform, follow these steps:
+The Linaro release provides a set of scripts that automate the process of
+building all components of the software stack. However, the scripts only support
+a limited number of Trusted Firmware build options. Therefore, it is recommended
+to modify these scripts to build all components except Trusted Firmware, and
+build Trusted Firmware separately as described in the section "Building the
+Trusted Firmware" above.
-1. Clone the [EDK2 source code][EDK2] from GitHub:
+The instructions below are targeted at an OpenEmbedded filesystem.
- git clone -n https://github.com/tianocore/edk2.git
+1. To exclude Trusted Firmware from the automated build process, edit the
+ variant file `build-scripts/variants/<platform>-oe`, where `<platform>`
+ is either `fvp` or `juno`. Add the following lines at the end of the file:
- Not all required features are available in the EDK2 mainline yet. These can
- be obtained from the ARM-software EDK2 repository instead:
+ # Disable ARM Trusted Firmware build
+ ARM_TF_BUILD_ENABLED=0
- cd edk2
- git remote add -f --tags arm-software https://github.com/ARM-software/edk2.git
- git checkout --detach v3.0
+2. Launch the build script:
-2. Copy build config templates to local workspace
+ CROSS_COMPILE=aarch64-linux-gnu- \
+ build-scripts/build-all.sh <platform>-oe
- # in edk2/
- . edksetup.sh
+### Preparing the Firmware Image Package
-3. Build the EDK2 host tools
+The EDK2 binary should be specified as `BL33` in the `make` command line when
+building the Trusted Firmware. See the "Building the Trusted Firmware" section
+above. The EDK2 binary for use with the ARM Trusted Firmware can be found here:
- make -C BaseTools clean
- make -C BaseTools
+ uefi/edk2/Build/ArmVExpress-FVP-AArch64-Minimal/DEBUG_GCC49/FV/FVP_AARCH64_EFI.fd [for FVP]
+ uefi/edk2/Build/ArmJuno/DEBUG_GCC49/FV/BL33_AP_UEFI.fd [for Juno]
-4. Build the EDK2 software
+### Building an alternative EDK2
- 1. Build for FVP
+* By default, EDK2 is built in debug mode. To build a release version instead,
+ change the following line in the variant file:
- GCC49_AARCH64_PREFIX=<absolute-path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- make -f ArmPlatformPkg/Scripts/Makefile EDK2_ARCH=AARCH64 \
- EDK2_DSC=ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc \
- EDK2_TOOLCHAIN=GCC49 EDK2_BUILD=RELEASE \
- EDK2_MACROS="-n 6 -D ARM_FOUNDATION_FVP=1"
+ UEFI_BUILD_MODE=DEBUG
- The EDK2 binary for use with the ARM Trusted Firmware can then be found
- here:
+ into:
- Build/ArmVExpress-FVP-AArch64/RELEASE_GCC49/FV/FVP_AARCH64_EFI.fd
+ UEFI_BUILD_MODE=RELEASE
- 2. Build for Juno
+* On FVP, if legacy GICv2 locations are used, the EDK2 platform makefile must
+ be updated. This is required as EDK2 does not support probing for the GIC
+ location. To do this, first clean the EDK2 build directory:
- GCC49_AARCH64_PREFIX=<absolute-path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- make -f ArmPlatformPkg/ArmJunoPkg/Makefile EDK2_ARCH=AARCH64 \
- EDK2_TOOLCHAIN=GCC49 EDK2_BUILD=RELEASE
+ build-scripts/build-uefi.sh fvp-oe clean
- The EDK2 binary for use with the ARM Trusted Firmware can then be found
- here:
+ Then edit the following file:
- Build/ArmJuno/RELEASE_GCC49/FV/BL33_AP_UEFI.fd
+ uefi/edk2/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.mak
- The EDK2 binary should be specified as `BL33` in in the `make` command line
- when building the Trusted Firmware. See the "Building the Trusted Firmware"
- section above.
-
-5. (Optional) To build EDK2 in debug mode, remove `EDK2_BUILD=RELEASE` from the
- command line.
-
-6. (Optional) To boot Linux using a VirtioBlock file-system, the command line
- passed from EDK2 to the Linux kernel must be modified as described in the
- "Obtaining a root file-system" section below.
-
-7. (Optional) If legacy GICv2 locations are used, the EDK2 platform description
- must be updated. This is required as EDK2 does not support probing for the
- GIC location. To do this, first clean the EDK2 build directory.
-
- make -f ArmPlatformPkg/Scripts/Makefile EDK2_ARCH=AARCH64 \
- EDK2_DSC=ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc \
- EDK2_TOOLCHAIN=ARMGCC clean
-
- Then rebuild EDK2 as described in step 3, using the following flag:
+ and add the following build flag into the `EDK2_MACROS` variable:
-D ARM_FVP_LEGACY_GICV2_LOCATION=1
+ Then rebuild everything as described above in step 2.
+
Finally rebuild the Trusted Firmware to generate a new FIP using the
instructions in the "Building the Trusted Firmware" section.
-### Obtaining a Linux kernel
-
-Preparing a Linux kernel for use on the FVPs can be done as follows
-(GICv2 support only):
-
-1. Clone Linux:
-
- git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
-
- Not all required features are available in the kernel mainline yet. These
- can be obtained from the ARM-software Linux repository instead:
-
- cd linux
- git remote add -f --tags arm-software https://github.com/ARM-software/linux.git
- git checkout --detach 1.6-Juno
-
-2. Build with the Linaro GCC tools.
-
- # in linux/
- make mrproper
- make ARCH=arm64 defconfig
-
- CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
- make -j6 ARCH=arm64
-
-The compiled Linux image will now be found at `arch/arm64/boot/Image`.
-
-
-6. Preparing the images to run on FVP
+7. Preparing the images to run on FVP
--------------------------------------
### Obtaining the Flattened Device Trees
@@ -708,6 +683,9 @@
subset of the Base FVP components. For example, the Foundation FVP lacks CLCD
and MMC support, and has only one CPU cluster.
+Note: It is not recommended to use the FDTs built along the kernel because not
+all FDTs are available from there.
+
* `fvp-base-gicv2-psci.dtb`
(Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with
@@ -735,110 +713,16 @@
For use with Foundation FVP with Base memory map configuration and Linux
GICv3 support.
-
Copy the chosen FDT blob as `fdt.dtb` to the directory from which the FVP
is launched. Alternatively a symbolic link may be used.
### Preparing the kernel image
-Copy the kernel image file `arch/arm64/boot/Image` to the directory from which
-the FVP is launched. Alternatively a symbolic link may be used.
+Copy the kernel image file `linux/arch/arm64/boot/Image` to the directory from
+which the FVP is launched. Alternatively a symbolic link may be used.
-### Obtaining a root file-system
-To prepare a Linaro LAMP based Open Embedded file-system, the following
-instructions can be used as a guide. The file-system can be provided to Linux
-via VirtioBlock or as a RAM-disk. Both methods are described below.
-
-#### Prepare VirtioBlock
-
-To prepare a VirtioBlock file-system, do the following:
-
-1. Download and unpack the disk image.
-
- NOTE: The unpacked disk image grows to 3 GiB in size.
-
- wget http://releases.linaro.org/15.03/members/arm/openembedded/aarch64/vexpress64-openembedded_lamp-armv8-gcc-4.9_20150324-715.img.gz
- gunzip vexpress64-openembedded_lamp-armv8-gcc-4.9_20150324-715.img.gz
-
-2. Make sure the Linux kernel has Virtio support enabled using
- `make ARCH=arm64 menuconfig`.
-
- Device Drivers ---> Virtio drivers ---> <*> Platform bus driver for memory mapped virtio devices
- Device Drivers ---> [*] Block devices ---> <*> Virtio block driver
- File systems ---> <*> The Extended 4 (ext4) filesystem
-
- If some of these configurations are missing, enable them, save the kernel
- configuration, then rebuild the kernel image using the instructions
- provided in the section "Obtaining a Linux kernel".
-
-3. Change the Kernel command line to include `root=/dev/vda2`. This can either
- be done in the EDK2 boot menu or in the platform file. Editing the platform
- file and rebuilding EDK2 will make the change persist. To do this:
-
- 1. In EDK2, edit the following file:
-
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc
-
- 2. Add `root=/dev/vda2` to:
-
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"<Other default options>"
-
- 3. Remove the entry:
-
- gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|""
-
- 4. Rebuild EDK2 (see "Obtaining UEFI" section above).
-
-4. The file-system image file should be provided to the model environment by
- passing it the correct command line option. In the FVPs the following
- option should be provided in addition to the ones described in the
- "Running the software on FVP" section below.
-
- NOTE: A symbolic link to this file cannot be used with the FVP; the path
- to the real file must be provided.
-
- On the Base FVPs:
-
- -C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
-
- On the Foundation FVP:
-
- --block-device="<path-to>/<file-system-image>"
-
-5. Ensure that the FVP doesn't output any error messages. If the following
- error message is displayed:
-
- ERROR: BlockDevice: Failed to open "<path-to>/<file-system-image>"!
-
- then make sure the path to the file-system image in the model parameter is
- correct and that read permission is correctly set on the file-system image
- file.
-
-#### Prepare RAM-disk
-
-To prepare a RAM-disk root file-system, do the following:
-
-1. Download the file-system image:
-
- wget http://releases.linaro.org/15.03/members/arm/openembedded/aarch64/linaro-image-lamp-genericarmv8-20150323-747.rootfs.tar.gz
-
-2. Modify the Linaro image:
-
- # Prepare for use as RAM-disk. Normally use MMC, NFS or VirtioBlock.
- # Be careful, otherwise you could damage your host file-system.
- mkdir tmp; cd tmp
- sudo sh -c "zcat ../linaro-image-lamp-genericarmv8-20150323-747.rootfs.tar.gz | cpio -id"
- sudo ln -s sbin/init .
- sudo sh -c "echo 'devtmpfs /dev devtmpfs mode=0755,nosuid 0 0' >> etc/fstab"
- sudo sh -c "find . | cpio --quiet -H newc -o | gzip -3 -n > ../filesystem.cpio.gz"
- cd ..
-
-3. Copy the resultant `filesystem.cpio.gz` to the directory where the FVP is
- launched from. Alternatively a symbolic link may be used.
-
-
-7. Running the software on FVP
+8. Running the software on FVP
-------------------------------
This version of the ARM Trusted Firmware has been tested on the following ARM
@@ -871,29 +755,33 @@
The following `Foundation_Platform` parameters should be used to boot Linux with
4 CPUs using the ARM Trusted Firmware.
-NOTE: Using the `--block-device` parameter is not necessary if a Linux RAM-disk
-file-system is used (see the "Obtaining a File-system" section above).
+ <path-to>/Foundation_Platform \
+ --cores=4 \
+ --secure-memory \
+ --visualization \
+ --gicv3 \
+ --data="<path-to>/<bl1-binary>"@0x0 \
+ --data="<path-to>/<FIP-binary>"@0x08000000 \
+ --data="<path-to>/<fdt>"@0x83000000 \
+ --data="<path-to>/<kernel-binary>"@0x80080000 \
+ --block-device="<path-to>/<file-system-image>"
-NOTE: The `--data="<path to FIP binary>"@0x8000000` parameter is used to load a
-Firmware Image Package at the start of NOR FLASH0 (see the "Building the
-Trusted Firmware" section above).
+1. The `--data="<path-to-some-binary>"@0x...` parameters are used to load
+ binaries into memory.
- <path-to>/Foundation_Platform \
- --cores=4 \
- --secure-memory \
- --visualization \
- --gicv3 \
- --data="<path-to>/<bl1-binary>"@0x0 \
- --data="<path-to>/<FIP-binary>"@0x8000000 \
- --block-device="<path-to>/<file-system-image>"
+ * BL1 is loaded at the start of the Trusted ROM.
+ * The Firmware Image Package is loaded at the start of NOR FLASH0.
+ * The Linux kernel image and device tree are loaded in DRAM.
+
+2. The `--block-device` parameter is used to specify the path to the file
+ system image provided to Linux via VirtioBlock. Note that it must point to
+ the real file and that a symbolic link to this file cannot be used with the
+ FVP.
The default use-case for the Foundation FVP is to enable the GICv3 device in
the model but use the GICv2 FDT, in order for Linux to drive the GIC in GICv2
emulation mode.
-The memory mapped addresses `0x0` and `0x8000000` correspond to the start of
-trusted ROM and NOR FLASH0 respectively.
-
### Notes regarding Base FVP configuration options
Please refer to these notes in the subsequent "Running on the Base FVP"
@@ -907,9 +795,17 @@
still work (and run much faster) without this option but this will hide any
cache maintenance defects in the software.
+3. The `-C bp.virtioblockdevice.image_path` parameter is used to specify the
+ path to the file system image provided to Linux via VirtioBlock. Note that
+ it must point to the real file and that a symbolic link to this file cannot
+ be used with the FVP. Ensure that the FVP doesn't output any error messages.
+ If the following error message is displayed:
+
-3. Using the `-C bp.virtioblockdevice.image_path` parameter is not necessary
- if a Linux RAM-disk file-system is used (see the "Obtaining a root
- file-system" section above).
+ ERROR: BlockDevice: Failed to open "<path-to>/<file-system-image>"!
+
+ then make sure the path to the file-system image in the model parameter is
+ correct and that read permission is correctly set on the file-system image
+ file.
4. Setting the `-C bp.secure_memory` parameter to `1` is only supported on
Base FVP versions 5.4 and newer. Setting this parameter to `0` is also
@@ -917,30 +813,33 @@
instructs the FVP to provide some helpful information if a secure memory
violation occurs.
+5. The `--data="<path-to-some-binary>"@<base-address-of-binary>` parameter is
+ used to load images into Base FVP memory. The base addresses used should
+ match the image base addresses used while linking the images. This parameter
+ is used to load the Linux kernel image and device tree into DRAM.
+
-5. This and the following notes only apply when the firmware is built with
+6. This and the following notes only apply when the firmware is built with
the `RESET_TO_BL31` option.
The `--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`
- parameter is used to load bootloader images into Base FVP memory (see the
- "Building the Trusted Firmware" section above). The base addresses used
- should match the image base addresses in `platform_def.h` used while linking
- the images. The BL3-2 image is only needed if BL3-1 has been built to expect
- a Secure-EL1 Payload.
+ parameter is needed to load the individual bootloader images in memory.
+ BL32 image is only needed if BL31 has been built to expect a Secure-EL1
+ Payload.
-6. The `-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>` parameter, where
+7. The `-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>` parameter, where
X and Y are the cluster and CPU numbers respectively, is used to set the
reset vector for each core.
-7. Changing the default value of `FVP_SHARED_DATA_LOCATION` will also require
+8. Changing the default value of `FVP_SHARED_DATA_LOCATION` will also require
changing the value of
`--data="<path-to><bl31-binary>"@<base-address-of-bl31>` and
`-C cluster<X>.cpu<X>.RVBAR=@<base-address-of-bl31>`, to the new value of
- `BL31_BASE` in `platform_def.h`.
+ `BL31_BASE`.
-8. Changing the default value of `FVP_TSP_RAM_LOCATION` will also require
+9. Changing the default value of `FVP_TSP_RAM_LOCATION` will also require
changing the value of
`--data="<path-to><bl32-binary>"@<base-address-of-bl32>` to the new value of
- `BL32_BASE` in `platform_def.h`.
+ `BL32_BASE`.
### Running on the AEMv8 Base FVP with reset to BL1 entrypoint
@@ -951,15 +850,17 @@
The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux
with 8 CPUs using the ARM Trusted Firmware.
- <path-to>/FVP_Base_AEMv8A-AEMv8A \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cluster0.NUM_CORES=4 \
- -C cluster1.NUM_CORES=4 \
- -C cache_state_modelled=1 \
- -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
- -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ <path-to>/FVP_Base_AEMv8A-AEMv8A \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cluster0.NUM_CORES=4 \
+ -C cluster1.NUM_CORES=4 \
+ -C cache_state_modelled=1 \
+ -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
+ -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
@@ -970,13 +871,15 @@
The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to
boot Linux with 8 CPUs using the ARM Trusted Firmware.
- <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
- -C pctl.startup=0.0.0.0 \
- -C bp.secure_memory=1 \
- -C bp.tzc_400.diagnostics=1 \
- -C cache_state_modelled=1 \
- -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
- -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
+ -C pctl.startup=0.0.0.0 \
+ -C bp.secure_memory=1 \
+ -C bp.tzc_400.diagnostics=1 \
+ -C cache_state_modelled=1 \
+ -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
+ -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the AEMv8 Base FVP with reset to BL3-1 entrypoint
@@ -1005,6 +908,8 @@
--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Running on the Cortex-A57-A53 Base FVP with reset to BL3-1 entrypoint
@@ -1031,6 +936,8 @@
--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
+ --data cluster0.cpu0="<path-to>/<fdt>"@0x83000000 \
+ --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>"
### Configuring the GICv2 memory map
@@ -1115,48 +1022,38 @@
detect the legacy VE memory map while configuring the GIC.
-8. Running the software on Juno
+9. Running the software on Juno
--------------------------------
-### Preparing Trusted Firmware images
+This version of the ARM Trusted Firmware has been tested on Juno r0 and Juno r1.
To execute the versions of software components on Juno referred to in this
-document, the latest [Juno Board Recovery Image] must be installed. If you
+document, the latest Juno board recovery image must be installed. If you
have an earlier version installed or are unsure which version is installed,
follow the recovery image update instructions in the [Juno Software Guide]
-on the [ARM Connected Community] website.
+on the [ARM Connected Community] website. The latest Juno board recovery image
+can be obtained from [Linaro releases], see section 2.7 "Using prebuilt
+binaries".
-Note that you must use the board recovery image provided in the Juno R1 Initial
-Alpha release, even for Juno R0. This is because the Trusted Firmware now
-supports the new [SCPI v1.0 final protocol][Juno SCP Protocols v1.0]
-exclusively, which is not compatible with the SCP firmware provided in the
-latest Juno R0 release. Although the Juno R1 Initial Alpha release is generally
-not recommended for use with Juno R0 boards, it is suitable for Trusted Firmware
-development.
+### Preparing Trusted Firmware images
-The Juno platform requires a BL0 and a BL3-0 image to boot up. The BL0 image
+The Juno platform requires a BL0 and a BL30 image to boot up. The BL0 image
contains the ROM firmware that runs on the SCP (System Control Processor),
-whereas the BL3-0 image contains the SCP Runtime firmware. Both images are
-embedded within the [Juno Board Recovery Image] but they can also be downloaded
-directly: [Juno SCP ROM Firmware] and [Juno SCP Runtime Firmware].
-
-Rebuild the Trusted Firmware specifying the BL3-0 image. Refer to the section
-"Building the Trusted Firmware". Alternatively, the FIP image can be updated
-manually with the BL3-0 image:
+whereas the BL30 image contains the SCP Runtime firmware. Both images are
+embedded within the Juno board recovery image, these are the files `bl0.bin`
+and `bl30.bin`.
- fip_create --dump --bl30 <path-to>/<bl30-binary> <path-to>/<FIP-binary>
+The BL30 file must be part of the FIP image. Therefore, its path must be
+supplied using the `BL30` variable on the command line when building the
+FIP. Please refer to the section "Building the Trusted Firmware".
-### Obtaining the Flattened Device Tree
-
-Juno's device tree blob is built along with the kernel. It is located in:
-
- <path-to-linux>/arch/arm64/boot/dts/arm/juno.dtb
+After building Trusted Firmware, the files `bl1.bin` and `fip.bin` need copying
+to the `SOFTWARE/` directory as explained in the [Juno Software Guide].
### Other Juno software information
Please refer to the [Juno Software Guide] to:
-* Deploy a root filesystem
* Install and run the Juno binaries on the board
* Obtain any other Juno software information
@@ -1166,17 +1063,11 @@
_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._
-[Firmware Design]: ./firmware-design.md
-
+[Firmware Design]: firmware-design.md
+[Linaro releases]: http://releases.linaro.org/15.06/members/arm/platforms
[ARM FVP website]: http://www.arm.com/fvp
[ARM Connected Community]: http://community.arm.com
[Juno Software Guide]: http://community.arm.com/docs/DOC-8396
-[Juno Board Recovery Image]: http://community.arm.com/servlet/JiveServlet/download/10177-1-18236/board_recovery_image_0.11.3.zip
-[Juno SCP ROM Firmware]: http://community.arm.com/servlet/JiveServlet/download/10177-1-18187/bl0.bin.zip
-[Juno SCP Runtime Firmware]: http://community.arm.com/servlet/JiveServlet/download/10177-1-18193/bl30.bin.zip
-[Juno SCP Protocols v1.0]: http://community.arm.com/servlet/JiveServlet/download/8401-40-18262/DUI0922A_scp_message_interface.pdf
-[Linaro Toolchain]: http://releases.linaro.org/14.07/components/toolchain/binaries/
-[EDK2]: http://github.com/tianocore/edk2
[DS-5]: http://www.arm.com/products/tools/software-tools/ds-5/index.php
[mbedTLS Repository]: https://github.com/ARMmbed/mbedtls.git
[Trusted Board Boot]: trusted-board-boot.md
diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c
index 44916d4..2e773a9 100644
--- a/drivers/arm/cci/cci.c
+++ b/drivers/arm/cci/cci.c
@@ -33,8 +33,9 @@
#include <cci.h>
#include <debug.h>
#include <mmio.h>
+#include <stdint.h>
-static unsigned long g_cci_base;
+static uintptr_t g_cci_base;
static unsigned int g_max_master_id;
static const int *g_cci_slave_if_map;
@@ -74,7 +75,7 @@
}
#endif /* DEBUG */
-void cci_init(unsigned long cci_base,
+void cci_init(uintptr_t cci_base,
const int *map,
unsigned int num_cci_masters)
{
diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c
index f832af8..242e1fa 100644
--- a/drivers/arm/cci400/cci400.c
+++ b/drivers/arm/cci400/cci400.c
@@ -33,14 +33,15 @@
#include <cci400.h>
#include <debug.h>
#include <mmio.h>
+#include <stdint.h>
#define MAX_CLUSTERS 2
-static unsigned long cci_base_addr;
+static uintptr_t cci_base_addr;
static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS];
-void cci_init(unsigned long cci_base,
+void cci_init(uintptr_t cci_base,
int slave_iface3_cluster_ix,
int slave_iface4_cluster_ix)
{
diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c
index 5217471..90fc8b5 100644
--- a/drivers/arm/gic/arm_gic.c
+++ b/drivers/arm/gic/arm_gic.c
@@ -47,9 +47,9 @@
(GIC_HIGHEST_NS_PRIORITY << 16) | \
(GIC_HIGHEST_NS_PRIORITY << 24))
-static unsigned int g_gicc_base;
-static unsigned int g_gicd_base;
-static unsigned long g_gicr_base;
+static uintptr_t g_gicc_base;
+static uintptr_t g_gicd_base;
+static uintptr_t g_gicr_base;
static const unsigned int *g_irq_sec_ptr;
static unsigned int g_num_irqs;
@@ -323,12 +323,11 @@
/*******************************************************************************
* Initialize the ARM GIC driver with the provided platform inputs
******************************************************************************/
-void arm_gic_init(unsigned int gicc_base,
- unsigned int gicd_base,
- unsigned long gicr_base,
- const unsigned int *irq_sec_ptr,
- unsigned int num_irqs
- )
+void arm_gic_init(uintptr_t gicc_base,
+ uintptr_t gicd_base,
+ uintptr_t gicr_base,
+ const unsigned int *irq_sec_ptr,
+ unsigned int num_irqs)
{
unsigned int val;
diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c
index 41603a9..dc5dc08 100644
--- a/drivers/arm/gic/gic_v2.c
+++ b/drivers/arm/gic/gic_v2.c
@@ -38,73 +38,73 @@
* GIC Distributor interface accessors for reading entire registers
******************************************************************************/
-unsigned int gicd_read_igroupr(unsigned int base, unsigned int id)
+unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
{
unsigned n = id >> IGROUPR_SHIFT;
return mmio_read_32(base + GICD_IGROUPR + (n << 2));
}
-unsigned int gicd_read_isenabler(unsigned int base, unsigned int id)
+unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
{
unsigned n = id >> ISENABLER_SHIFT;
return mmio_read_32(base + GICD_ISENABLER + (n << 2));
}
-unsigned int gicd_read_icenabler(unsigned int base, unsigned int id)
+unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
{
unsigned n = id >> ICENABLER_SHIFT;
return mmio_read_32(base + GICD_ICENABLER + (n << 2));
}
-unsigned int gicd_read_ispendr(unsigned int base, unsigned int id)
+unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
{
unsigned n = id >> ISPENDR_SHIFT;
return mmio_read_32(base + GICD_ISPENDR + (n << 2));
}
-unsigned int gicd_read_icpendr(unsigned int base, unsigned int id)
+unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
{
unsigned n = id >> ICPENDR_SHIFT;
return mmio_read_32(base + GICD_ICPENDR + (n << 2));
}
-unsigned int gicd_read_isactiver(unsigned int base, unsigned int id)
+unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
{
unsigned n = id >> ISACTIVER_SHIFT;
return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
}
-unsigned int gicd_read_icactiver(unsigned int base, unsigned int id)
+unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
{
unsigned n = id >> ICACTIVER_SHIFT;
return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
}
-unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id)
+unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
{
unsigned n = id >> IPRIORITYR_SHIFT;
return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
}
-unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id)
+unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id)
{
unsigned n = id >> ITARGETSR_SHIFT;
return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
}
-unsigned int gicd_read_icfgr(unsigned int base, unsigned int id)
+unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
{
unsigned n = id >> ICFGR_SHIFT;
return mmio_read_32(base + GICD_ICFGR + (n << 2));
}
-unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id)
+unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id)
{
unsigned n = id >> CPENDSGIR_SHIFT;
return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
}
-unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id)
+unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id)
{
unsigned n = id >> SPENDSGIR_SHIFT;
return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
@@ -114,73 +114,73 @@
* GIC Distributor interface accessors for writing entire registers
******************************************************************************/
-void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> IGROUPR_SHIFT;
mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
}
-void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ISENABLER_SHIFT;
mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
}
-void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICENABLER_SHIFT;
mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
}
-void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ISPENDR_SHIFT;
mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
}
-void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICPENDR_SHIFT;
mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
}
-void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ISACTIVER_SHIFT;
mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
}
-void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICACTIVER_SHIFT;
mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
}
-void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> IPRIORITYR_SHIFT;
mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
}
-void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ITARGETSR_SHIFT;
mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
}
-void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> ICFGR_SHIFT;
mmio_write_32(base + GICD_ICFGR + (n << 2), val);
}
-void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> CPENDSGIR_SHIFT;
mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
}
-void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val)
+void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val)
{
unsigned n = id >> SPENDSGIR_SHIFT;
mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
@@ -189,7 +189,7 @@
/*******************************************************************************
* GIC Distributor interface accessors for individual interrupt manipulation
******************************************************************************/
-unsigned int gicd_get_igroupr(unsigned int base, unsigned int id)
+unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
unsigned int reg_val = gicd_read_igroupr(base, id);
@@ -197,7 +197,7 @@
return (reg_val >> bit_num) & 0x1;
}
-void gicd_set_igroupr(unsigned int base, unsigned int id)
+void gicd_set_igroupr(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
unsigned int reg_val = gicd_read_igroupr(base, id);
@@ -205,7 +205,7 @@
gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
}
-void gicd_clr_igroupr(unsigned int base, unsigned int id)
+void gicd_clr_igroupr(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
unsigned int reg_val = gicd_read_igroupr(base, id);
@@ -213,42 +213,42 @@
gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
}
-void gicd_set_isenabler(unsigned int base, unsigned int id)
+void gicd_set_isenabler(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
gicd_write_isenabler(base, id, (1 << bit_num));
}
-void gicd_set_icenabler(unsigned int base, unsigned int id)
+void gicd_set_icenabler(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
gicd_write_icenabler(base, id, (1 << bit_num));
}
-void gicd_set_ispendr(unsigned int base, unsigned int id)
+void gicd_set_ispendr(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
gicd_write_ispendr(base, id, (1 << bit_num));
}
-void gicd_set_icpendr(unsigned int base, unsigned int id)
+void gicd_set_icpendr(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
gicd_write_icpendr(base, id, (1 << bit_num));
}
-void gicd_set_isactiver(unsigned int base, unsigned int id)
+void gicd_set_isactiver(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
gicd_write_isactiver(base, id, (1 << bit_num));
}
-void gicd_set_icactiver(unsigned int base, unsigned int id)
+void gicd_set_icactiver(uintptr_t base, unsigned int id)
{
unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
@@ -259,7 +259,7 @@
* Make sure that the interrupt's group is set before expecting
* this function to do its job correctly.
*/
-void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri)
+void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
{
unsigned int reg = base + GICD_IPRIORITYR + (id & ~3);
unsigned int shift = (id & 3) << 3;
@@ -283,7 +283,7 @@
mmio_write_32(reg, reg_val);
}
-void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int target)
+void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target)
{
unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1);
unsigned int reg_val = gicd_read_itargetsr(base, id);
diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S
index 4ed0ceb..ea41e5d 100644
--- a/drivers/arm/pl011/pl011_console.S
+++ b/drivers/arm/pl011/pl011_console.S
@@ -44,7 +44,7 @@
/* -----------------------------------------------
- * int console_core_init(unsigned long base_addr,
+ * int console_core_init(uintptr_t base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. This
@@ -90,7 +90,7 @@
endfunc console_core_init
/* --------------------------------------------------------
- * int console_core_putc(int c, unsigned long base_addr)
+ * int console_core_putc(int c, uintptr_t base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
@@ -123,7 +123,7 @@
endfunc console_core_putc
/* ---------------------------------------------
- * int console_core_getc(unsigned long base_addr)
+ * int console_core_getc(uintptr_t base_addr)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 on error.
diff --git a/drivers/arm/tzc400/tzc400.c b/drivers/arm/tzc400/tzc400.c
index cb89fda..4b72a2b 100644
--- a/drivers/arm/tzc400/tzc400.c
+++ b/drivers/arm/tzc400/tzc400.c
@@ -41,7 +41,7 @@
* Address width : Values between 32 to 64
*/
typedef struct tzc_instance {
- uint64_t base;
+ uintptr_t base;
uint8_t addr_width;
uint8_t num_filters;
uint8_t num_regions;
@@ -50,27 +50,27 @@
tzc_instance_t tzc;
-static inline uint32_t tzc_read_build_config(uint64_t base)
+static inline uint32_t tzc_read_build_config(uintptr_t base)
{
return mmio_read_32(base + BUILD_CONFIG_OFF);
}
-static inline uint32_t tzc_read_gate_keeper(uint64_t base)
+static inline uint32_t tzc_read_gate_keeper(uintptr_t base)
{
return mmio_read_32(base + GATE_KEEPER_OFF);
}
-static inline void tzc_write_gate_keeper(uint64_t base, uint32_t val)
+static inline void tzc_write_gate_keeper(uintptr_t base, uint32_t val)
{
mmio_write_32(base + GATE_KEEPER_OFF, val);
}
-static inline void tzc_write_action(uint64_t base, tzc_action_t action)
+static inline void tzc_write_action(uintptr_t base, tzc_action_t action)
{
mmio_write_32(base + ACTION_OFF, action);
}
-static inline void tzc_write_region_base_low(uint64_t base,
+static inline void tzc_write_region_base_low(uintptr_t base,
uint32_t region,
uint32_t val)
{
@@ -78,7 +78,7 @@
REGION_NUM_OFF(region), val);
}
-static inline void tzc_write_region_base_high(uint64_t base,
+static inline void tzc_write_region_base_high(uintptr_t base,
uint32_t region,
uint32_t val)
{
@@ -86,7 +86,7 @@
REGION_NUM_OFF(region), val);
}
-static inline void tzc_write_region_top_low(uint64_t base,
+static inline void tzc_write_region_top_low(uintptr_t base,
uint32_t region,
uint32_t val)
{
@@ -94,7 +94,7 @@
REGION_NUM_OFF(region), val);
}
-static inline void tzc_write_region_top_high(uint64_t base,
+static inline void tzc_write_region_top_high(uintptr_t base,
uint32_t region,
uint32_t val)
{
@@ -102,7 +102,7 @@
REGION_NUM_OFF(region), val);
}
-static inline void tzc_write_region_attributes(uint64_t base,
+static inline void tzc_write_region_attributes(uintptr_t base,
uint32_t region,
uint32_t val)
{
@@ -110,7 +110,7 @@
REGION_NUM_OFF(region), val);
}
-static inline void tzc_write_region_id_access(uint64_t base,
+static inline void tzc_write_region_id_access(uintptr_t base,
uint32_t region,
uint32_t val)
{
@@ -118,7 +118,7 @@
REGION_NUM_OFF(region), val);
}
-static uint32_t tzc_read_component_id(uint64_t base)
+static uint32_t tzc_read_component_id(uintptr_t base)
{
uint32_t id;
@@ -130,7 +130,7 @@
return id;
}
-static uint32_t tzc_get_gate_keeper(uint64_t base, uint8_t filter)
+static uint32_t tzc_get_gate_keeper(uintptr_t base, uint8_t filter)
{
uint32_t tmp;
@@ -141,7 +141,7 @@
}
/* This function is not MP safe. */
-static void tzc_set_gate_keeper(uint64_t base, uint8_t filter, uint32_t val)
+static void tzc_set_gate_keeper(uintptr_t base, uint8_t filter, uint32_t val)
{
uint32_t tmp;
@@ -164,7 +164,7 @@
}
-void tzc_init(uint64_t base)
+void tzc_init(uintptr_t base)
{
uint32_t tzc_id, tzc_build;
diff --git a/drivers/console/console.S b/drivers/console/console.S
index 85c8f65..d966f0d 100644
--- a/drivers/console/console.S
+++ b/drivers/console/console.S
@@ -44,7 +44,7 @@
console_base: .quad 0x0
/* -----------------------------------------------
- * int console_init(unsigned long base_addr,
+ * int console_init(uintptr_t base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. It saves
diff --git a/drivers/console/skeleton_console.S b/drivers/console/skeleton_console.S
index af78376..083d3c7 100644
--- a/drivers/console/skeleton_console.S
+++ b/drivers/console/skeleton_console.S
@@ -40,7 +40,7 @@
.globl console_core_getc
/* -----------------------------------------------
- * int console_core_init(unsigned long base_addr,
+ * int console_core_init(uintptr_t base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. This
@@ -68,7 +68,7 @@
endfunc console_core_init
/* --------------------------------------------------------
- * int console_core_putc(int c, unsigned long base_addr)
+ * int console_core_putc(int c, uintptr_t base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
@@ -88,7 +88,7 @@
endfunc console_core_putc
/* ---------------------------------------------
- * int console_core_getc(unsigned long base_addr)
+ * int console_core_getc(uintptr_t base_addr)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 on error.
diff --git a/drivers/io/io_semihosting.c b/drivers/io/io_semihosting.c
index 3c92c6d..8e62be1 100644
--- a/drivers/io/io_semihosting.c
+++ b/drivers/io/io_semihosting.c
@@ -183,7 +183,6 @@
static int sh_file_write(io_entity_t *entity, const uintptr_t buffer,
size_t length, size_t *length_written)
{
- int result = IO_FAIL;
long sh_result = -1;
long file_handle;
size_t bytes = length;
@@ -196,13 +195,9 @@
sh_result = semihosting_file_write(file_handle, &bytes, buffer);
- if (sh_result >= 0) {
- *length_written = sh_result;
- result = IO_SUCCESS;
- } else
- result = IO_FAIL;
+ *length_written = length - bytes;
- return result;
+ return (sh_result == 0) ? IO_SUCCESS : IO_FAIL;
}
diff --git a/include/drivers/arm/arm_gic.h b/include/drivers/arm/arm_gic.h
index 9ab1a95..5752d8f 100644
--- a/include/drivers/arm/arm_gic.h
+++ b/include/drivers/arm/arm_gic.h
@@ -36,11 +36,11 @@
/*******************************************************************************
* Function declarations
******************************************************************************/
-void arm_gic_init(unsigned int gicc_base,
- unsigned int gicd_base,
- unsigned long gicr_base,
- const unsigned int *irq_sec_ptr,
- unsigned int num_irqs);
+void arm_gic_init(uintptr_t gicc_base,
+ uintptr_t gicd_base,
+ uintptr_t gicr_base,
+ const unsigned int *irq_sec_ptr,
+ unsigned int num_irqs);
void arm_gic_setup(void);
void arm_gic_cpuif_deactivate(void);
void arm_gic_cpuif_setup(void);
diff --git a/include/drivers/arm/cci.h b/include/drivers/arm/cci.h
index 2401e85..1145f91 100644
--- a/include/drivers/arm/cci.h
+++ b/include/drivers/arm/cci.h
@@ -146,7 +146,7 @@
* SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists
* for that interface.
*/
-void cci_init(unsigned long cci_base,
+void cci_init(uintptr_t cci_base,
const int *map,
unsigned int num_cci_masters);
diff --git a/include/drivers/arm/cci400.h b/include/drivers/arm/cci400.h
index 7756bdf..620221a 100644
--- a/include/drivers/arm/cci400.h
+++ b/include/drivers/arm/cci400.h
@@ -68,6 +68,8 @@
#ifndef __ASSEMBLY__
+#include <stdint.h>
+
/* Function declarations */
/*
@@ -79,7 +81,7 @@
* affinity instance of the mpidr representing the cluster. A negative cluster
* index indicates that no cluster is present on that slave interface.
*/
-void cci_init(unsigned long cci_base,
+void cci_init(uintptr_t cci_base,
int slave_iface3_cluster_ix,
int slave_iface4_cluster_ix);
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
index 54276b8..ce9311e 100644
--- a/include/drivers/arm/gic_v2.h
+++ b/include/drivers/arm/gic_v2.h
@@ -145,64 +145,64 @@
#ifndef __ASSEMBLY__
#include <mmio.h>
-
+#include <stdint.h>
/*******************************************************************************
* GIC Distributor function prototypes
******************************************************************************/
-unsigned int gicd_read_igroupr(unsigned int, unsigned int);
-unsigned int gicd_read_isenabler(unsigned int, unsigned int);
-unsigned int gicd_read_icenabler(unsigned int, unsigned int);
-unsigned int gicd_read_ispendr(unsigned int, unsigned int);
-unsigned int gicd_read_icpendr(unsigned int, unsigned int);
-unsigned int gicd_read_isactiver(unsigned int, unsigned int);
-unsigned int gicd_read_icactiver(unsigned int, unsigned int);
-unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
-unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
-unsigned int gicd_read_icfgr(unsigned int, unsigned int);
-unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
-unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
-void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
-void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
-void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
-void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
-void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
-void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
-void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
-void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
-void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
-void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
-void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
-void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
-unsigned int gicd_get_igroupr(unsigned int, unsigned int);
-void gicd_set_igroupr(unsigned int, unsigned int);
-void gicd_clr_igroupr(unsigned int, unsigned int);
-void gicd_set_isenabler(unsigned int, unsigned int);
-void gicd_set_icenabler(unsigned int, unsigned int);
-void gicd_set_ispendr(unsigned int, unsigned int);
-void gicd_set_icpendr(unsigned int, unsigned int);
-void gicd_set_isactiver(unsigned int, unsigned int);
-void gicd_set_icactiver(unsigned int, unsigned int);
-void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
-void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
+unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
+unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
+unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
+unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
+unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
+unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
+unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
+unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
+unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
+unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
+unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
+unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
+void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
+void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
+void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
+void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
+void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
+void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
+void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
+void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
+void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
+void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
+void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
+void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
+unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
+void gicd_set_igroupr(uintptr_t, unsigned int);
+void gicd_clr_igroupr(uintptr_t, unsigned int);
+void gicd_set_isenabler(uintptr_t, unsigned int);
+void gicd_set_icenabler(uintptr_t, unsigned int);
+void gicd_set_ispendr(uintptr_t, unsigned int);
+void gicd_set_icpendr(uintptr_t, unsigned int);
+void gicd_set_isactiver(uintptr_t, unsigned int);
+void gicd_set_icactiver(uintptr_t, unsigned int);
+void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
+void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
/*******************************************************************************
* GIC Distributor interface accessors for reading entire registers
******************************************************************************/
-static inline unsigned int gicd_read_ctlr(unsigned int base)
+static inline unsigned int gicd_read_ctlr(uintptr_t base)
{
return mmio_read_32(base + GICD_CTLR);
}
-static inline unsigned int gicd_read_typer(unsigned int base)
+static inline unsigned int gicd_read_typer(uintptr_t base)
{
return mmio_read_32(base + GICD_TYPER);
}
-static inline unsigned int gicd_read_sgir(unsigned int base)
+static inline unsigned int gicd_read_sgir(uintptr_t base)
{
return mmio_read_32(base + GICD_SGIR);
}
@@ -212,12 +212,12 @@
* GIC Distributor interface accessors for writing entire registers
******************************************************************************/
-static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
+static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICD_CTLR, val);
}
-static inline void gicd_write_sgir(unsigned int base, unsigned int val)
+static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICD_SGIR, val);
}
@@ -227,47 +227,47 @@
* GIC CPU interface accessors for reading entire registers
******************************************************************************/
-static inline unsigned int gicc_read_ctlr(unsigned int base)
+static inline unsigned int gicc_read_ctlr(uintptr_t base)
{
return mmio_read_32(base + GICC_CTLR);
}
-static inline unsigned int gicc_read_pmr(unsigned int base)
+static inline unsigned int gicc_read_pmr(uintptr_t base)
{
return mmio_read_32(base + GICC_PMR);
}
-static inline unsigned int gicc_read_BPR(unsigned int base)
+static inline unsigned int gicc_read_BPR(uintptr_t base)
{
return mmio_read_32(base + GICC_BPR);
}
-static inline unsigned int gicc_read_IAR(unsigned int base)
+static inline unsigned int gicc_read_IAR(uintptr_t base)
{
return mmio_read_32(base + GICC_IAR);
}
-static inline unsigned int gicc_read_EOIR(unsigned int base)
+static inline unsigned int gicc_read_EOIR(uintptr_t base)
{
return mmio_read_32(base + GICC_EOIR);
}
-static inline unsigned int gicc_read_hppir(unsigned int base)
+static inline unsigned int gicc_read_hppir(uintptr_t base)
{
return mmio_read_32(base + GICC_HPPIR);
}
-static inline unsigned int gicc_read_ahppir(unsigned int base)
+static inline unsigned int gicc_read_ahppir(uintptr_t base)
{
return mmio_read_32(base + GICC_AHPPIR);
}
-static inline unsigned int gicc_read_dir(unsigned int base)
+static inline unsigned int gicc_read_dir(uintptr_t base)
{
return mmio_read_32(base + GICC_DIR);
}
-static inline unsigned int gicc_read_iidr(unsigned int base)
+static inline unsigned int gicc_read_iidr(uintptr_t base)
{
return mmio_read_32(base + GICC_IIDR);
}
@@ -277,38 +277,38 @@
* GIC CPU interface accessors for writing entire registers
******************************************************************************/
-static inline void gicc_write_ctlr(unsigned int base, unsigned int val)
+static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_CTLR, val);
}
-static inline void gicc_write_pmr(unsigned int base, unsigned int val)
+static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_PMR, val);
}
-static inline void gicc_write_BPR(unsigned int base, unsigned int val)
+static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_BPR, val);
}
-static inline void gicc_write_IAR(unsigned int base, unsigned int val)
+static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_IAR, val);
}
-static inline void gicc_write_EOIR(unsigned int base, unsigned int val)
+static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_EOIR, val);
}
-static inline void gicc_write_hppir(unsigned int base, unsigned int val)
+static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_HPPIR, val);
}
-static inline void gicc_write_dir(unsigned int base, unsigned int val)
+static inline void gicc_write_dir(uintptr_t base, unsigned int val)
{
mmio_write_32(base + GICC_DIR, val);
}
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 7b951d2..a5312c4 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -189,7 +189,7 @@
} tzc_region_attributes_t;
-void tzc_init(uint64_t base);
+void tzc_init(uintptr_t base);
void tzc_configure_region0(tzc_region_attributes_t sec_attr,
uint32_t ns_device_access);
void tzc_configure_region(uint32_t filters,
diff --git a/include/drivers/console.h b/include/drivers/console.h
index f144ab9..d374157 100644
--- a/include/drivers/console.h
+++ b/include/drivers/console.h
@@ -31,7 +31,9 @@
#ifndef __CONSOLE_H__
#define __CONSOLE_H__
-int console_init(unsigned long base_addr,
+#include <stdint.h>
+
+int console_init(uintptr_t base_addr,
unsigned int uart_clk, unsigned int baud_rate);
int console_putc(int c);
int console_getc(void);
diff --git a/include/plat/arm/common/arm_config.h b/include/plat/arm/common/arm_config.h
index 21f394c..48fb33b 100644
--- a/include/plat/arm/common/arm_config.h
+++ b/include/plat/arm/common/arm_config.h
@@ -30,6 +30,7 @@
#ifndef __ARM_CONFIG_H__
#define __ARM_CONFIG_H__
+#include <stdint.h>
enum arm_config_flags {
/* Whether Base memory map is in use */
@@ -41,10 +42,10 @@
};
typedef struct arm_config {
- unsigned int gicd_base;
- unsigned int gicc_base;
- unsigned int gich_base;
- unsigned int gicv_base;
+ uintptr_t gicd_base;
+ uintptr_t gicc_base;
+ uintptr_t gich_base;
+ uintptr_t gicv_base;
unsigned int max_aff0;
unsigned int max_aff1;
unsigned long flags;
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c
index 849ec12..b4f53d2 100644
--- a/lib/semihosting/semihosting.c
+++ b/lib/semihosting/semihosting.c
@@ -125,6 +125,7 @@
const uintptr_t buffer)
{
smh_file_read_write_block_t write_block;
+ long result = -EINVAL;
if ((length == NULL) || (buffer == (uintptr_t)NULL))
return -EINVAL;
@@ -133,10 +134,12 @@
write_block.buffer = (uintptr_t)buffer; /* cast away const */
write_block.length = *length;
- *length = semihosting_call(SEMIHOSTING_SYS_WRITE,
+ result = semihosting_call(SEMIHOSTING_SYS_WRITE,
(void *) &write_block);
- return *length;
+ *length = result;
+
+ return (result == 0) ? 0 : -EINVAL;
}
long semihosting_file_close(long file_handle)