Merge pull request #337 from vwadekar/tegra-misc-fixes-v3
Tegra misc fixes v3
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 264749b..2979b32 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -57,6 +57,7 @@
*/
.macro cpu_init_common
+#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
/* -------------------------------------------------------
* Enable L2 and CPU ECTLR RW access from non-secure world
* -------------------------------------------------------
@@ -65,6 +66,7 @@
msr actlr_el3, x0
msr actlr_el2, x0
isb
+#endif
/* --------------------------------
* Enable the cycle count register
diff --git a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
index a36cf2d..b473dd6 100644
--- a/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
+++ b/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c
@@ -31,6 +31,7 @@
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
+#include <delay_timer.h>
#include <mmio.h>
#include <pmc.h>
#include <cortex_a53.h>
@@ -230,10 +231,7 @@
; /* wait till value reaches EVP_BPMP_RESET_VECTOR */
/* Wait for 2us before de-asserting the reset signal. */
- val = mmio_read_32(TEGRA_TMRUS_BASE);
- val += 2;
- while (val > mmio_read_32(TEGRA_TMRUS_BASE))
- ; /* wait for 2us */
+ udelay(2);
/* De-assert BPMP reset */
mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST);
diff --git a/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/plat/nvidia/tegra/common/drivers/pmc/pmc.c
index 5796ac7..d48b575 100644
--- a/plat/nvidia/tegra/common/drivers/pmc/pmc.c
+++ b/plat/nvidia/tegra/common/drivers/pmc/pmc.c
@@ -52,6 +52,13 @@
uint32_t val;
/*
+ * Check if CPU is already power ungated
+ */
+ val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
+ if (val & (1 << pmc_cpu_powergate_id[cpu]))
+ return;
+
+ /*
* The PMC deasserts the START bit when it starts the power
* ungate process. Loop till no power toggle is in progress.
*/
@@ -98,6 +105,11 @@
{
uint32_t val;
+ /* lock PMC_SECURE_SCRATCH22 */
+ val = tegra_pmc_read_32(PMC_SECURE_DISABLE2);
+ val |= PMC_SECURE_DISABLE2_WRITE22_ON;
+ tegra_pmc_write_32(PMC_SECURE_DISABLE2, val);
+
/* lock PMC_SECURE_SCRATCH34/35 */
val = tegra_pmc_read_32(PMC_SECURE_DISABLE3);
val |= (PMC_SECURE_DISABLE3_WRITE34_ON |
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index dea8457..ce7f317 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -162,6 +162,11 @@
uint32_t tmp_reg;
/*
+ * Initialize delay timer
+ */
+ tegra_delay_timer_init();
+
+ /*
* Setup secondary CPU POR infrastructure.
*/
plat_secondary_setup();
@@ -196,13 +201,9 @@
unsigned long total_size = TZDRAM_END - BL31_RO_BASE;
unsigned long ro_start = bl31_base_pa;
unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE;
- unsigned long coh_start = 0;
- unsigned long coh_size = 0;
const mmap_region_t *plat_mmio_map = NULL;
-
#if USE_COHERENT_MEM
- coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
- coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
+ unsigned long coh_start, coh_size;
#endif
/* add memory regions */
@@ -212,7 +213,11 @@
mmap_add_region(ro_start, ro_start,
ro_size,
MT_MEMORY | MT_RO | MT_SECURE);
+
#if USE_COHERENT_MEM
+ coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE);
+ coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE;
+
mmap_add_region(coh_start, coh_start,
coh_size,
MT_DEVICE | MT_RW | MT_SECURE);
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 73e1281..b88742a 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -34,6 +34,8 @@
ASM_ASSERTION := 1
$(eval $(call add_define,ASM_ASSERTION))
+USE_COHERENT_MEM := 0
+
PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \
-Iplat/nvidia/tegra/include \
-Iplat/nvidia/tegra/include/${TARGET_SOC}
@@ -46,6 +48,7 @@
BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/console/console.S \
+ drivers/delay_timer/delay_timer.c \
drivers/ti/uart/16550_console.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
@@ -55,6 +58,7 @@
${COMMON_DIR}/drivers/pmc/pmc.c \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
${COMMON_DIR}/tegra_bl31_setup.c \
+ ${COMMON_DIR}/tegra_delay_timer.c \
${COMMON_DIR}/tegra_gic.c \
${COMMON_DIR}/tegra_pm.c \
${COMMON_DIR}/tegra_sip_calls.c \
diff --git a/plat/nvidia/tegra/common/tegra_delay_timer.c b/plat/nvidia/tegra/common/tegra_delay_timer.c
new file mode 100644
index 0000000..e1f6ede
--- /dev/null
+++ b/plat/nvidia/tegra/common/tegra_delay_timer.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <delay_timer.h>
+#include <mmio.h>
+#include <tegra_def.h>
+
+static uint32_t tegra_timerus_get_value(void)
+{
+ return mmio_read_32(TEGRA_TMRUS_BASE);
+}
+
+static const timer_ops_t tegra_timer_ops = {
+ .get_timer_value = tegra_timerus_get_value,
+ .clk_mult = 1,
+ .clk_div = 1,
+};
+
+/*
+ * Initialise the on-chip free rolling us counter as the delay
+ * timer.
+ */
+void tegra_delay_timer_init(void)
+{
+ timer_init(&tegra_timer_ops);
+}
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index fa29fbb..d0cde2a 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -74,4 +74,7 @@
plat_params_from_bl2_t *bl31_get_plat_params(void);
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
+/* Declarations for tegra_delay_timer.c */
+void tegra_delay_timer_init(void);
+
#endif /* __TEGRA_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index f594d20..010899a 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -40,6 +40,13 @@
#include <tegra_def.h>
#include <tegra_private.h>
+/*
+ * Register used to clear CPU reset signals. Each CPU has two reset
+ * signals: CPU reset (3:0) and Core reset (19:16).
+ */
+#define CPU_CMPLX_RESET_CLR 0x454
+#define CPU_CORE_RESET_MASK 0x10001
+
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
@@ -116,6 +123,10 @@
int tegra_prepare_cpu_on(unsigned long mpidr)
{
int cpu = mpidr & MPIDR_CPU_MASK;
+ uint32_t mask = CPU_CORE_RESET_MASK << cpu;
+
+ /* Deassert CPU reset signals */
+ mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
/* Turn on CPU using flow controller or PMC */
if (cpu_powergate_mask[cpu] == 0) {
diff --git a/plat/nvidia/tegra/soc/t210/plat_secondary.c b/plat/nvidia/tegra/soc/t210/plat_secondary.c
index fb3cf71..b07f446 100644
--- a/plat/nvidia/tegra/soc/t210/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t210/plat_secondary.c
@@ -60,4 +60,5 @@
/* configure PMC */
tegra_pmc_cpu_setup(reset_addr);
+ tegra_pmc_lock_cpu_vectors();
}
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index 41651d3..003b489 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -28,19 +28,22 @@
# POSSIBILITY OF SUCH DAMAGE.
#
-TEGRA_BOOT_UART_BASE := 0x70006000
+TEGRA_BOOT_UART_BASE := 0x70006000
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
-TZDRAM_BASE := 0xFDC00000
+TZDRAM_BASE := 0xFDC00000
$(eval $(call add_define,TZDRAM_BASE))
ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
-PLATFORM_CLUSTER_COUNT := 2
+ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
+$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
+
+PLATFORM_CLUSTER_COUNT := 2
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
-PLATFORM_MAX_CPUS_PER_CLUSTER := 4
+PLATFORM_MAX_CPUS_PER_CLUSTER := 4
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
BL31_SOURCES += ${SOC_DIR}/plat_psci_handlers.c \
@@ -49,3 +52,4 @@
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_826319 := 1
+