Tegra186: fix programming sequence for SC7/SC8 entry
This patch fixes the programming sequence for 'System Suspend' and
'Quasi power down' state entry. The device needs to update the
required power state before querying the MCE firmware to see the
entry to that power state is allowed.
Original change by Allen Yu <alleny@nvidia.com>
Change-Id: I65e03754322188af913fabf41f29d1c3595afd85
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 536ecbf..8911e8f 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -150,14 +150,6 @@
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
- /* loop until SC7 is allowed */
- do {
- val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED,
- TEGRA_ARI_CORE_C7,
- MCE_CORE_SLEEP_TIME_INFINITE,
- 0);
- } while (val == 0);
-
/* save SE registers */
se_regs[0] = mmio_read_32(TEGRA_SE0_BASE +
SE_MUTEX_WATCHDOG_NS_LIMIT);
@@ -184,6 +176,14 @@
(void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC7);
+ /* Loop until system suspend is allowed */
+ do {
+ val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED,
+ TEGRA_ARI_CORE_C7,
+ MCE_CORE_SLEEP_TIME_INFINITE,
+ 0);
+ } while (val == 0);
+
/* Instruct the MCE to enter system suspend state */
(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
@@ -314,6 +314,13 @@
} else if (tegra186_system_powerdn_state == TEGRA_ARI_SYSTEM_SC8) {
+ /* Prepare for quasi power down */
+ write_ctx_reg(gp_regs, CTX_GPREG_X4, 1);
+ write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
+ write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
+ (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
+ TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC8);
+
/* loop until other CPUs power down */
do {
val = mce_command_handler(MCE_CMD_IS_SC7_ALLOWED,
@@ -322,13 +329,6 @@
0);
} while (val == 0);
- /* Prepare for quasi power down */
- write_ctx_reg(gp_regs, CTX_GPREG_X4, 1);
- write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
- write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
- (void)mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO,
- TEGRA_ARI_CLUSTER_CC7, 0, TEGRA_ARI_SYSTEM_SC8);
-
/* Enter quasi power down state */
(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);