Merge pull request #1584 from danielboulby-arm/db/Switches
Ensure the flow through switch statements is clear
diff --git a/.gitignore b/.gitignore
index 78da669..b4359c1 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,7 +11,6 @@
# Ignore build products from tools
tools/**/*.o
-tools/fip_create/
tools/fiptool/fiptool
tools/fiptool/fiptool.exe
tools/cert_create/src/*.o
diff --git a/Makefile b/Makefile
index 9dc8a42..23a1b0a 100644
--- a/Makefile
+++ b/Makefile
@@ -7,8 +7,8 @@
#
# Trusted Firmware Version
#
-VERSION_MAJOR := 1
-VERSION_MINOR := 5
+VERSION_MAJOR := 2
+VERSION_MINOR := 0
# Default goal is build all images
.DEFAULT_GOAL := all
@@ -327,19 +327,6 @@
include make_helpers/armv7-a-cpus.mk
endif
-# Platform compatibility is not supported in AArch32
-ifneq (${ARCH},aarch32)
-# If the platform has not defined ENABLE_PLAT_COMPAT, then enable it by default
-ifndef ENABLE_PLAT_COMPAT
-ENABLE_PLAT_COMPAT := 1
-endif
-
-# Include the platform compatibility helpers for PSCI
-ifneq (${ENABLE_PLAT_COMPAT}, 0)
-include plat/compat/plat_compat.mk
-endif
-endif
-
# Include the CPU specific operations makefile, which provides default
# values for all CPU errata workarounds and CPU specific optimisations.
# This can be overridden by the platform.
@@ -403,13 +390,6 @@
endif
endif
-# For AArch32, LOAD_IMAGE_V2 must be enabled.
-ifeq (${ARCH},aarch32)
- ifeq (${LOAD_IMAGE_V2}, 0)
- $(error "For AArch32, LOAD_IMAGE_V2 must be enabled.")
- endif
-endif
-
# When building for systems with hardware-assisted coherency, there's no need to
# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
ifeq ($(HW_ASSISTED_COHERENCY)-$(USE_COHERENT_MEM),1-1)
@@ -451,14 +431,11 @@
endif
endif
-# DYN_DISABLE_AUTH can be set only when TRUSTED_BOARD_BOOT=1 and LOAD_IMAGE_V2=1
+# DYN_DISABLE_AUTH can be set only when TRUSTED_BOARD_BOOT=1
ifeq ($(DYN_DISABLE_AUTH), 1)
ifeq (${TRUSTED_BOARD_BOOT}, 0)
$(error "TRUSTED_BOARD_BOOT must be enabled for DYN_DISABLE_AUTH to be set.")
endif
- ifeq (${LOAD_IMAGE_V2}, 0)
- $(error "DYN_DISABLE_AUTH is only supported for LOAD_IMAGE_V2.")
- endif
endif
################################################################################
@@ -586,7 +563,6 @@
$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
$(eval $(call assert_boolean,ENABLE_BACKTRACE))
$(eval $(call assert_boolean,ENABLE_MPAM_FOR_LOWER_ELS))
-$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
$(eval $(call assert_boolean,ENABLE_PMF))
$(eval $(call assert_boolean,ENABLE_PSCI_STAT))
$(eval $(call assert_boolean,ENABLE_RUNTIME_INSTRUMENTATION))
@@ -599,7 +575,6 @@
$(eval $(call assert_boolean,GICV2_G0_FOR_EL3))
$(eval $(call assert_boolean,HANDLE_EA_EL3_FIRST))
$(eval $(call assert_boolean,HW_ASSISTED_COHERENCY))
-$(eval $(call assert_boolean,LOAD_IMAGE_V2))
$(eval $(call assert_boolean,MULTI_CONSOLE_API))
$(eval $(call assert_boolean,NS_TIMER_SWITCH))
$(eval $(call assert_boolean,PL011_GENERIC_UART))
@@ -630,7 +605,6 @@
$(eval $(call add_define,ARM_ARCH_MAJOR))
$(eval $(call add_define,ARM_ARCH_MINOR))
-$(eval $(call add_define,ARM_GIC_ARCH))
$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
$(eval $(call add_define,CTX_INCLUDE_FPREGS))
@@ -639,7 +613,6 @@
$(eval $(call add_define,ENABLE_ASSERTIONS))
$(eval $(call add_define,ENABLE_BACKTRACE))
$(eval $(call add_define,ENABLE_MPAM_FOR_LOWER_ELS))
-$(eval $(call add_define,ENABLE_PLAT_COMPAT))
$(eval $(call add_define,ENABLE_PMF))
$(eval $(call add_define,ENABLE_PSCI_STAT))
$(eval $(call add_define,ENABLE_RUNTIME_INSTRUMENTATION))
@@ -651,7 +624,6 @@
$(eval $(call add_define,GICV2_G0_FOR_EL3))
$(eval $(call add_define,HANDLE_EA_EL3_FIRST))
$(eval $(call add_define,HW_ASSISTED_COHERENCY))
-$(eval $(call add_define,LOAD_IMAGE_V2))
$(eval $(call add_define,LOG_LEVEL))
$(eval $(call add_define,MULTI_CONSOLE_API))
$(eval $(call add_define,NS_TIMER_SWITCH))
diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c
index 28b9eb9..0fbdf51 100644
--- a/bl1/bl1_fwu.c
+++ b/bl1/bl1_fwu.c
@@ -289,26 +289,11 @@
return -ENOMEM;
}
-#if LOAD_IMAGE_V2
/* Check that the image size to load is within limit */
if (image_size > image_desc->image_info.image_max_size) {
WARN("BL1-FWU: Image size out of bounds\n");
return -ENOMEM;
}
-#else
- /*
- * Check the image will fit into the free trusted RAM after BL1
- * load.
- */
- const meminfo_t *mem_layout = bl1_plat_sec_mem_layout();
- if (!is_mem_free(mem_layout->free_base, mem_layout->free_size,
- image_desc->image_info.image_base,
- image_size)) {
- WARN("BL1-FWU: Copy not allowed due to insufficient"
- " resources.\n");
- return -ENOMEM;
- }
-#endif
/* Save the given image size. */
image_desc->image_info.image_size = image_size;
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 047cd6f..ca43695 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -37,7 +37,6 @@
assert(bl1_mem_layout != NULL);
assert(bl2_mem_layout != NULL);
-#if LOAD_IMAGE_V2
/*
* Remove BL1 RW data from the scope of memory visible to BL2.
* This is assuming BL1 RW data is at the top of bl1_mem_layout.
@@ -45,43 +44,11 @@
assert(BL1_RW_BASE > bl1_mem_layout->total_base);
bl2_mem_layout->total_base = bl1_mem_layout->total_base;
bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
-#else
- /* Check that BL1's memory is lying outside of the free memory */
- assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
- (BL1_RAM_BASE >= bl1_mem_layout->free_base +
- bl1_mem_layout->free_size));
-
- /* Remove BL1 RW data from the scope of memory visible to BL2 */
- *bl2_mem_layout = *bl1_mem_layout;
- reserve_mem(&bl2_mem_layout->total_base,
- &bl2_mem_layout->total_size,
- BL1_RAM_BASE,
- BL1_RAM_LIMIT - BL1_RAM_BASE);
-#endif /* LOAD_IMAGE_V2 */
flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
}
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Compatibility default implementation for deprecated API. This has a weak
- * definition. Platform specific code can override it if it wishes to.
- ******************************************************************************/
-#pragma weak bl1_init_bl2_mem_layout
-
/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout,
- struct meminfo *bl2_mem_layout)
-{
- bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout);
-}
-#endif
-
-/*******************************************************************************
* Function to perform late architectural and platform specific initialization.
* It also queries the platform to load and run next BL image. Only called
* by the primary cpu after a cold boot.
@@ -183,27 +150,7 @@
plat_error_handler(err);
}
-#if LOAD_IMAGE_V2
err = load_auth_image(BL2_IMAGE_ID, image_info);
-#else
- entry_point_info_t *ep_info;
- meminfo_t *bl1_tzram_layout;
-
- /* Get the entry point info */
- ep_info = &image_desc->ep_info;
-
- /* Find out how much free trusted ram remains after BL1 load */
- bl1_tzram_layout = bl1_plat_sec_mem_layout();
-
- /* Load the BL2 image */
- err = load_auth_image(bl1_tzram_layout,
- BL2_IMAGE_ID,
- image_info->image_base,
- image_info,
- ep_info);
-
-#endif /* LOAD_IMAGE_V2 */
-
if (err) {
ERROR("Failed to load BL2 firmware.\n");
plat_error_handler(err);
diff --git a/bl1/tbbr/tbbr_img_desc.c b/bl1/tbbr/tbbr_img_desc.c
index 44f58d3..2581d90 100644
--- a/bl1/tbbr/tbbr_img_desc.c
+++ b/bl1/tbbr/tbbr_img_desc.c
@@ -15,9 +15,7 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_1, image_info_t, 0),
.image_info.image_base = BL2_BASE,
-#if LOAD_IMAGE_V2
.image_info.image_max_size = BL2_LIMIT - BL2_BASE,
-#endif
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_1, entry_point_info_t, SECURE),
},
@@ -35,9 +33,7 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_1, image_info_t, 0),
.image_info.image_base = SCP_BL2U_BASE,
-#if LOAD_IMAGE_V2
.image_info.image_max_size = SCP_BL2U_LIMIT - SCP_BL2U_BASE,
-#endif
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_1, entry_point_info_t, SECURE),
},
@@ -48,9 +44,7 @@
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_1, image_info_t, 0),
.image_info.image_base = BL2U_BASE,
-#if LOAD_IMAGE_V2
.image_info.image_max_size = BL2U_LIMIT - BL2U_BASE,
-#endif
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),
.ep_info.pc = BL2U_BASE,
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index af30a81..f905bc2 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -14,11 +14,7 @@
BL2_SOURCES += common/aarch64/early_exceptions.S
endif
-ifeq (${LOAD_IMAGE_V2},1)
BL2_SOURCES += bl2/bl2_image_load_v2.c
-else
-BL2_SOURCES += bl2/bl2_image_load.c
-endif
ifeq (${BL2_AT_EL3},0)
BL2_SOURCES += bl2/${ARCH}/bl2_entrypoint.S
diff --git a/bl2/bl2_image_load.c b/bl2/bl2_image_load.c
deleted file mode 100644
index d22e9ce..0000000
--- a/bl2/bl2_image_load.c
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <assert.h>
-#include <auth_mod.h>
-#include <bl_common.h>
-#include <debug.h>
-#include <errno.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <stdint.h>
-
-/*
- * Check for platforms that use obsolete image terminology
- */
-#ifdef BL30_BASE
-# error "BL30_BASE platform define no longer used - please use SCP_BL2_BASE"
-#endif
-
-/*******************************************************************************
- * Load the SCP_BL2 image if there's one.
- * If a platform does not want to attempt to load SCP_BL2 image it must leave
- * SCP_BL2_BASE undefined.
- * Return 0 on success or if there's no SCP_BL2 image to load, a negative error
- * code otherwise.
- ******************************************************************************/
-static int load_scp_bl2(void)
-{
- int e = 0;
-#ifdef SCP_BL2_BASE
- meminfo_t scp_bl2_mem_info;
- image_info_t scp_bl2_image_info;
-
- /*
- * It is up to the platform to specify where SCP_BL2 should be loaded if
- * it exists. It could create space in the secure sram or point to a
- * completely different memory.
- *
- * The entry point information is not relevant in this case as the AP
- * won't execute the SCP_BL2 image.
- */
- INFO("BL2: Loading SCP_BL2\n");
- bl2_plat_get_scp_bl2_meminfo(&scp_bl2_mem_info);
- scp_bl2_image_info.h.version = VERSION_1;
- e = load_auth_image(&scp_bl2_mem_info,
- SCP_BL2_IMAGE_ID,
- SCP_BL2_BASE,
- &scp_bl2_image_info,
- NULL);
-
- if (e == 0) {
- /* The subsequent handling of SCP_BL2 is platform specific */
- e = bl2_plat_handle_scp_bl2(&scp_bl2_image_info);
- if (e) {
- ERROR("Failure in platform-specific handling of SCP_BL2 image.\n");
- }
- }
-#endif /* SCP_BL2_BASE */
-
- return e;
-}
-
-#ifndef EL3_PAYLOAD_BASE
-/*******************************************************************************
- * Load the BL31 image.
- * The bl2_to_bl31_params and bl31_ep_info params will be updated with the
- * relevant BL31 information.
- * Return 0 on success, a negative error code otherwise.
- ******************************************************************************/
-static int load_bl31(bl31_params_t *bl2_to_bl31_params,
- entry_point_info_t *bl31_ep_info)
-{
- meminfo_t *bl2_tzram_layout;
- int e;
-
- INFO("BL2: Loading BL31\n");
- assert(bl2_to_bl31_params != NULL);
- assert(bl31_ep_info != NULL);
-
- /* Find out how much free trusted ram remains after BL2 load */
- bl2_tzram_layout = bl2_plat_sec_mem_layout();
-
- /* Set the X0 parameter to BL31 */
- bl31_ep_info->args.arg0 = (unsigned long)bl2_to_bl31_params;
-
- /* Load the BL31 image */
- e = load_auth_image(bl2_tzram_layout,
- BL31_IMAGE_ID,
- BL31_BASE,
- bl2_to_bl31_params->bl31_image_info,
- bl31_ep_info);
-
- if (e == 0) {
- bl2_plat_set_bl31_ep_info(bl2_to_bl31_params->bl31_image_info,
- bl31_ep_info);
- }
-
- return e;
-}
-
-/*******************************************************************************
- * Load the BL32 image if there's one.
- * The bl2_to_bl31_params param will be updated with the relevant BL32
- * information.
- * If a platform does not want to attempt to load BL32 image it must leave
- * BL32_BASE undefined.
- * Return 0 on success or if there's no BL32 image to load, a negative error
- * code otherwise.
- ******************************************************************************/
-static int load_bl32(bl31_params_t *bl2_to_bl31_params)
-{
- int e = 0;
-#ifdef BL32_BASE
- meminfo_t bl32_mem_info;
-
- INFO("BL2: Loading BL32\n");
- assert(bl2_to_bl31_params != NULL);
-
- /*
- * It is up to the platform to specify where BL32 should be loaded if
- * it exists. It could create space in the secure sram or point to a
- * completely different memory.
- */
- bl2_plat_get_bl32_meminfo(&bl32_mem_info);
- e = load_auth_image(&bl32_mem_info,
- BL32_IMAGE_ID,
- BL32_BASE,
- bl2_to_bl31_params->bl32_image_info,
- bl2_to_bl31_params->bl32_ep_info);
-
- if (e == 0) {
- bl2_plat_set_bl32_ep_info(
- bl2_to_bl31_params->bl32_image_info,
- bl2_to_bl31_params->bl32_ep_info);
- }
-#endif /* BL32_BASE */
-
- return e;
-}
-
-#ifndef PRELOADED_BL33_BASE
-/*******************************************************************************
- * Load the BL33 image.
- * The bl2_to_bl31_params param will be updated with the relevant BL33
- * information.
- * Return 0 on success, a negative error code otherwise.
- ******************************************************************************/
-static int load_bl33(bl31_params_t *bl2_to_bl31_params)
-{
- meminfo_t bl33_mem_info;
- int e;
-
- INFO("BL2: Loading BL33\n");
- assert(bl2_to_bl31_params != NULL);
-
- bl2_plat_get_bl33_meminfo(&bl33_mem_info);
-
- /* Load the BL33 image in non-secure memory provided by the platform */
- e = load_auth_image(&bl33_mem_info,
- BL33_IMAGE_ID,
- plat_get_ns_image_entrypoint(),
- bl2_to_bl31_params->bl33_image_info,
- bl2_to_bl31_params->bl33_ep_info);
-
- if (e == 0) {
- bl2_plat_set_bl33_ep_info(bl2_to_bl31_params->bl33_image_info,
- bl2_to_bl31_params->bl33_ep_info);
- }
-
- return e;
-}
-#endif /* PRELOADED_BL33_BASE */
-
-#endif /* EL3_PAYLOAD_BASE */
-
-/*******************************************************************************
- * This function loads SCP_BL2/BL3x images and returns the ep_info for
- * the next executable image.
- ******************************************************************************/
-struct entry_point_info *bl2_load_images(void)
-{
- bl31_params_t *bl2_to_bl31_params;
- entry_point_info_t *bl31_ep_info;
- int e;
-
- e = load_scp_bl2();
- if (e) {
- ERROR("Failed to load SCP_BL2 (%i)\n", e);
- plat_error_handler(e);
- }
-
- /* Perform platform setup in BL2 after loading SCP_BL2 */
- bl2_platform_setup();
-
- /*
- * Get a pointer to the memory the platform has set aside to pass
- * information to BL31.
- */
- bl2_to_bl31_params = bl2_plat_get_bl31_params();
- bl31_ep_info = bl2_plat_get_bl31_ep_info();
-
-#ifdef EL3_PAYLOAD_BASE
- /*
- * In the case of an EL3 payload, we don't need to load any further
- * images. Just update the BL31 entrypoint info structure to make BL1
- * jump to the EL3 payload.
- * The pointer to the memory the platform has set aside to pass
- * information to BL31 in the normal boot flow is reused here, even
- * though only a fraction of the information contained in the
- * bl31_params_t structure makes sense in the context of EL3 payloads.
- * This will be refined in the future.
- */
- INFO("BL2: Populating the entrypoint info for the EL3 payload\n");
- bl31_ep_info->pc = EL3_PAYLOAD_BASE;
- bl31_ep_info->args.arg0 = (unsigned long) bl2_to_bl31_params;
- bl2_plat_set_bl31_ep_info(NULL, bl31_ep_info);
-#else
- e = load_bl31(bl2_to_bl31_params, bl31_ep_info);
- if (e) {
- ERROR("Failed to load BL31 (%i)\n", e);
- plat_error_handler(e);
- }
-
- e = load_bl32(bl2_to_bl31_params);
- if (e) {
- if (e == -EAUTH) {
- ERROR("Failed to authenticate BL32\n");
- plat_error_handler(e);
- } else {
- WARN("Failed to load BL32 (%i)\n", e);
- }
- }
-
-#ifdef PRELOADED_BL33_BASE
- /*
- * In this case, don't load the BL33 image as it's already loaded in
- * memory. Update BL33 entrypoint information.
- */
- INFO("BL2: Populating the entrypoint info for the preloaded BL33\n");
- bl2_to_bl31_params->bl33_ep_info->pc = PRELOADED_BL33_BASE;
- bl2_plat_set_bl33_ep_info(NULL, bl2_to_bl31_params->bl33_ep_info);
-#else
- e = load_bl33(bl2_to_bl31_params);
- if (e) {
- ERROR("Failed to load BL33 (%i)\n", e);
- plat_error_handler(e);
- }
-#endif /* PRELOADED_BL33_BASE */
-
-#endif /* EL3_PAYLOAD_BASE */
-
- /* Flush the params to be passed to memory */
- bl2_plat_flush_bl31_params();
-
- return bl31_ep_info;
-}
diff --git a/bl31/bl31_context_mgmt.c b/bl31/bl31_context_mgmt.c
index 7d2c893..f868372 100644
--- a/bl31/bl31_context_mgmt.c
+++ b/bl31/bl31_context_mgmt.c
@@ -61,70 +61,3 @@
set_cpu_data_by_index(cpu_idx, cpu_context[security_state], context);
}
-
-#if !ERROR_DEPRECATED
-/*
- * These context management helpers are deprecated but are maintained for use
- * by SPDs which have not migrated to the new API. If ERROR_DEPRECATED
- * is enabled, these are excluded from the build so as to force users to
- * migrate to the new API.
- */
-
-/*******************************************************************************
- * This function returns a pointer to the most recent 'cpu_context' structure
- * for the CPU identified by MPIDR that was set as the context for the specified
- * security state. NULL is returned if no such structure has been specified.
- ******************************************************************************/
-void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state)
-{
- assert(sec_state_is_valid(security_state));
-
- /*
- * Suppress deprecated declaration warning in compatibility function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- return cm_get_context_by_index(platform_get_core_pos(mpidr), security_state);
-#pragma GCC diagnostic pop
-}
-
-/*******************************************************************************
- * This function sets the pointer to the current 'cpu_context' structure for the
- * specified security state for the CPU identified by MPIDR
- ******************************************************************************/
-void cm_set_context_by_mpidr(uint64_t mpidr, void *context, uint32_t security_state)
-{
- assert(sec_state_is_valid(security_state));
-
- /*
- * Suppress deprecated declaration warning in compatibility function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- cm_set_context_by_index(platform_get_core_pos(mpidr),
- context, security_state);
-#pragma GCC diagnostic pop
-}
-
-/*******************************************************************************
- * The following function provides a compatibility function for SPDs using the
- * existing cm library routines. This function is expected to be invoked for
- * initializing the cpu_context for the CPU specified by MPIDR for first use.
- ******************************************************************************/
-void cm_init_context(uint64_t mpidr, const entry_point_info_t *ep)
-{
- if ((mpidr & MPIDR_AFFINITY_MASK) ==
- (read_mpidr_el1() & MPIDR_AFFINITY_MASK))
- cm_init_my_context(ep);
- else {
- /*
- * Suppress deprecated declaration warning in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- cm_init_context_by_index(platform_get_core_pos(mpidr), ep);
-#pragma GCC diagnostic pop
- }
-}
-#endif /* ERROR_DEPRECATED */
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 5479a49..4b7f63c 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -108,10 +108,8 @@
int32_t rc = (*bl32_init)();
- if (rc != 0) {
- WARN("BL31: BL32 initialization failed (rc = %d)\n",
- rc);
- }
+ if (rc == 0)
+ WARN("BL31: BL32 initialization failed\n");
}
/*
* We are ready to enter the next EL. Prepare entry into the image
diff --git a/common/bl_common.c b/common/bl_common.c
index af51c07..60baa5b 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -23,8 +23,7 @@
/******************************************************************************
* API to dynamically disable authentication. Only meant for development
- * systems. This is only invoked if DYN_DISABLE_AUTH is defined. This
- * capability is restricted to LOAD_IMAGE_V2.
+ * systems. This is only invoked if DYN_DISABLE_AUTH is defined.
*****************************************************************************/
void dyn_disable_auth(void)
{
@@ -101,88 +100,6 @@
return (addr >= free_base) && (requested_end <= free_end);
}
-#if !LOAD_IMAGE_V2
-/******************************************************************************
- * Inside a given memory region, determine whether a sub-region of memory is
- * closer from the top or the bottom of the encompassing region. Return the
- * size of the smallest chunk of free memory surrounding the sub-region in
- * 'small_chunk_size'.
- *****************************************************************************/
-static unsigned int choose_mem_pos(uintptr_t mem_start, uintptr_t mem_end,
- uintptr_t submem_start, uintptr_t submem_end,
- size_t *small_chunk_size)
-{
- size_t top_chunk_size, bottom_chunk_size;
-
- assert(mem_start <= submem_start);
- assert(submem_start <= submem_end);
- assert(submem_end <= mem_end);
- assert(small_chunk_size != NULL);
-
- top_chunk_size = mem_end - submem_end;
- bottom_chunk_size = submem_start - mem_start;
-
- if (top_chunk_size < bottom_chunk_size) {
- *small_chunk_size = top_chunk_size;
- return TOP;
- } else {
- *small_chunk_size = bottom_chunk_size;
- return BOTTOM;
- }
-}
-
-/******************************************************************************
- * Reserve the memory region delimited by 'addr' and 'size'. The extents of free
- * memory are passed in 'free_base' and 'free_size' and they will be updated to
- * reflect the memory usage.
- * The caller must ensure the memory to reserve is free and that the addresses
- * and sizes passed in arguments are sane.
- *****************************************************************************/
-void reserve_mem(uintptr_t *free_base, size_t *free_size,
- uintptr_t addr, size_t size)
-{
- size_t discard_size;
- size_t reserved_size;
- unsigned int pos;
-
- assert(free_base != NULL);
- assert(free_size != NULL);
- assert(is_mem_free(*free_base, *free_size, addr, size));
-
- if (size == 0) {
- WARN("Nothing to allocate, requested size is zero\n");
- return;
- }
-
- pos = choose_mem_pos(*free_base, *free_base + (*free_size - 1),
- addr, addr + (size - 1),
- &discard_size);
-
- reserved_size = size + discard_size;
- *free_size -= reserved_size;
-
- if (pos == BOTTOM)
- *free_base = addr + size;
-
- VERBOSE("Reserved 0x%zx bytes (discarded 0x%zx bytes %s)\n",
- reserved_size, discard_size,
- pos == TOP ? "above" : "below");
-}
-
-static void dump_load_info(uintptr_t image_load_addr,
- size_t image_size,
- const meminfo_t *mem_layout)
-{
- INFO("Trying to load image at address %p, size = 0x%zx\n",
- (void *)image_load_addr, image_size);
- INFO("Current memory layout:\n");
- INFO(" total region = [base = %p, size = 0x%zx]\n",
- (void *) mem_layout->total_base, mem_layout->total_size);
- INFO(" free region = [base = %p, size = 0x%zx]\n",
- (void *) mem_layout->free_base, mem_layout->free_size);
-}
-#endif /* LOAD_IMAGE_V2 */
-
/* Generic function to return the size of an image */
size_t get_image_size(unsigned int image_id)
{
@@ -226,8 +143,6 @@
return image_size;
}
-#if LOAD_IMAGE_V2
-
/*******************************************************************************
* Internal function to load an image at a specific address given
* an image ID and extents of free memory.
@@ -386,214 +301,6 @@
return err;
}
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * Generic function to load an image at a specific address given an image ID and
- * extents of free memory.
- *
- * If the load is successful then the image information is updated.
- *
- * If the entry_point_info argument is not NULL then this function also updates:
- * - the memory layout to mark the memory as reserved;
- * - the entry point information.
- *
- * The caller might pass a NULL pointer for the entry point if they are not
- * interested in this information. This is typically the case for non-executable
- * images (e.g. certificates) and executable images that won't ever be executed
- * on the application processor (e.g. additional microcontroller firmware).
- *
- * Returns 0 on success, a negative error code otherwise.
- ******************************************************************************/
-int load_image(meminfo_t *mem_layout,
- unsigned int image_id,
- uintptr_t image_base,
- image_info_t *image_data,
- entry_point_info_t *entry_point_info)
-{
- uintptr_t dev_handle;
- uintptr_t image_handle;
- uintptr_t image_spec;
- size_t image_size;
- size_t bytes_read;
- int io_result;
-
- assert(mem_layout != NULL);
- assert(image_data != NULL);
- assert(image_data->h.version == VERSION_1);
-
- /* Obtain a reference to the image by querying the platform layer */
- io_result = plat_get_image_source(image_id, &dev_handle, &image_spec);
- if (io_result != 0) {
- WARN("Failed to obtain reference to image id=%u (%i)\n",
- image_id, io_result);
- return io_result;
- }
-
- /* Attempt to access the image */
- io_result = io_open(dev_handle, image_spec, &image_handle);
- if (io_result != 0) {
- WARN("Failed to access image id=%u (%i)\n",
- image_id, io_result);
- return io_result;
- }
-
- INFO("Loading image id=%u at address %p\n", image_id,
- (void *) image_base);
-
- /* Find the size of the image */
- io_result = io_size(image_handle, &image_size);
- if ((io_result != 0) || (image_size == 0)) {
- WARN("Failed to determine the size of the image id=%u (%i)\n",
- image_id, io_result);
- goto exit;
- }
-
- /* Check that the memory where the image will be loaded is free */
- if (!is_mem_free(mem_layout->free_base, mem_layout->free_size,
- image_base, image_size)) {
- WARN("Failed to reserve region [base = %p, size = 0x%zx]\n",
- (void *) image_base, image_size);
- dump_load_info(image_base, image_size, mem_layout);
- io_result = -ENOMEM;
- goto exit;
- }
-
- /* We have enough space so load the image now */
- /* TODO: Consider whether to try to recover/retry a partially successful read */
- io_result = io_read(image_handle, image_base, image_size, &bytes_read);
- if ((io_result != 0) || (bytes_read < image_size)) {
- WARN("Failed to load image id=%u (%i)\n", image_id, io_result);
- goto exit;
- }
-
- image_data->image_base = image_base;
- image_data->image_size = image_size;
-
- /*
- * Update the memory usage info.
- * This is done after the actual loading so that it is not updated when
- * the load is unsuccessful.
- * If the caller does not provide an entry point, bypass the memory
- * reservation.
- */
- if (entry_point_info != NULL) {
- reserve_mem(&mem_layout->free_base, &mem_layout->free_size,
- image_base, image_size);
- entry_point_info->pc = image_base;
- } else {
- INFO("Skip reserving region [base = %p, size = 0x%zx]\n",
- (void *) image_base, image_size);
- }
-
-#if !TRUSTED_BOARD_BOOT
- /*
- * File has been successfully loaded.
- * Flush the image to main memory so that it can be executed later by
- * any CPU, regardless of cache and MMU state.
- * When TBB is enabled the image is flushed later, after image
- * authentication.
- */
- flush_dcache_range(image_base, image_size);
-#endif /* TRUSTED_BOARD_BOOT */
-
- INFO("Image id=%u loaded at address %p, size = 0x%zx\n", image_id,
- (void *) image_base, image_size);
-
-exit:
- io_close(image_handle);
- /* Ignore improbable/unrecoverable error in 'close' */
-
- /* TODO: Consider maintaining open device connection from this bootloader stage */
- io_dev_close(dev_handle);
- /* Ignore improbable/unrecoverable error in 'dev_close' */
-
- return io_result;
-}
-
-static int load_auth_image_internal(meminfo_t *mem_layout,
- unsigned int image_id,
- uintptr_t image_base,
- image_info_t *image_data,
- entry_point_info_t *entry_point_info,
- int is_parent_image)
-{
- int rc;
-
-#if TRUSTED_BOARD_BOOT
- unsigned int parent_id;
-
- /* Use recursion to authenticate parent images */
- rc = auth_mod_get_parent_id(image_id, &parent_id);
- if (rc == 0) {
- rc = load_auth_image_internal(mem_layout, parent_id, image_base,
- image_data, NULL, 1);
- if (rc != 0) {
- return rc;
- }
- }
-#endif /* TRUSTED_BOARD_BOOT */
-
- /* Load the image */
- rc = load_image(mem_layout, image_id, image_base, image_data,
- entry_point_info);
- if (rc != 0) {
- return rc;
- }
-
-#if TRUSTED_BOARD_BOOT
- /* Authenticate it */
- rc = auth_mod_verify_img(image_id,
- (void *)image_data->image_base,
- image_data->image_size);
- if (rc != 0) {
- /* Authentication error, zero memory and flush it right away. */
- zero_normalmem((void *)image_data->image_base,
- image_data->image_size);
- flush_dcache_range(image_data->image_base,
- image_data->image_size);
- return -EAUTH;
- }
- /*
- * File has been successfully loaded and authenticated.
- * Flush the image to main memory so that it can be executed later by
- * any CPU, regardless of cache and MMU state.
- * Do it only for child images, not for the parents (certificates).
- */
- if (!is_parent_image) {
- flush_dcache_range(image_data->image_base,
- image_data->image_size);
- }
-#endif /* TRUSTED_BOARD_BOOT */
-
- return 0;
-}
-
-/*******************************************************************************
- * Generic function to load and authenticate an image. The image is actually
- * loaded by calling the 'load_image()' function. Therefore, it returns the
- * same error codes if the loading operation failed, or -EAUTH if the
- * authentication failed. In addition, this function uses recursion to
- * authenticate the parent images up to the root of trust.
- ******************************************************************************/
-int load_auth_image(meminfo_t *mem_layout,
- unsigned int image_id,
- uintptr_t image_base,
- image_info_t *image_data,
- entry_point_info_t *entry_point_info)
-{
- int err;
-
- do {
- err = load_auth_image_internal(mem_layout, image_id, image_base,
- image_data, entry_point_info, 0);
- } while (err != 0 && plat_try_next_boot_source());
-
- return err;
-}
-
-#endif /* LOAD_IMAGE_V2 */
-
/*******************************************************************************
* Print the content of an entry_point_info_t structure.
******************************************************************************/
diff --git a/contributing.rst b/contributing.rst
index c3eadbb..5ab7f09 100644
--- a/contributing.rst
+++ b/contributing.rst
@@ -116,7 +116,7 @@
.. _Fork: https://help.github.com/articles/fork-a-repo
.. _arm-trusted-firmware: https://github.com/ARM-software/arm-trusted-firmware
.. _Git guidelines: http://git-scm.com/book/ch5-2.html
-.. _Linux coding style: https://www.kernel.org/doc/Documentation/CodingStyle
+.. _Linux coding style: https://github.com/torvalds/linux/blob/master/Documentation/process/coding-style.rst
.. _User Guide: ./docs/user-guide.rst
.. _automatically closed: https://help.github.com/articles/closing-issues-via-commit-messages
.. _Porting Guide: ./docs/porting-guide.rst
diff --git a/docs/change-log.rst b/docs/change-log.rst
index 41e53a5..95361e9 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,327 @@
.. contents::
+Trusted Firmware-A - version 2.0
+================================
+
+New Features
+------------
+
+- Removal of a number of deprecated API's
+
+ - A new Platform Compatibility Policy document has been created which
+ references a wiki page that maintains a listing of deprecated
+ interfaces and the release after which they will be removed.
+
+ - All deprecated interfaces except the MULTI_CONSOLE_API have been removed
+ from the code base.
+
+ - Various Arm and partner platforms have been updated to remove the use of
+ removed API's in this release.
+
+ - This release is otherwise unchanged from 1.6 release
+
+Issues resolved since last release
+----------------------------------
+
+- No issues known at 1.6 release resolved in 2.0 release
+
+Known Issues
+------------
+
+- DTB creation not supported when building on a Windows host. This step in the
+ build process is skipped when running on a Windows host. Known issue from
+ 1.6 version.
+
+- As a result of removal of deprecated interfaces the Nvidia Tegra, Marvell
+ Armada 8K and MediaTek MT6795 platforms do not build in this release.
+ Also MediaTek MT8173, NXP QorIQ LS1043A, NXP i.MX8QX, NXP i.MX8QMa,
+ Rockchip RK3328, Rockchip RK3368 and Rockchip RK3399 platforms have not been
+ confirmed to be working after the removal of the deprecated interfaces
+ although they do build.
+
+Trusted Firmware-A - version 1.6
+================================
+
+New Features
+------------
+
+- Addressing Speculation Security Vulnerabilities
+
+ - Implement static workaround for CVE-2018-3639 for AArch32 and AArch64
+
+ - Add support for dynamic mitigation for CVE-2018-3639
+
+ - Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
+
+ - Ensure SDEI handler executes with CVE-2018-3639 mitigation enabled
+
+- Introduce RAS handling on AArch64
+
+ - Some RAS extensions are mandatory for ARMv8.2 CPUs, with others
+ mandatory for ARMv8.4 CPUs however, all extensions are also optional
+ extensions to the base ARMv8.0 architecture.
+
+ - The ARMv8 RAS Extensions introduced Standard Error Records which are a
+ set of standard registers to configure RAS node policy and allow RAS
+ Nodes to record and expose error information for error handling agents.
+
+ - Capabilities are provided to support RAS Node enumeration and iteration
+ along with individual interrupt registrations and fault injections
+ support.
+
+ - Introduce handlers for Uncontainable errors, Double Faults and EL3
+ External Aborts
+
+- Enable Memory Partitioning And Monitoring (MPAM) for lower EL's
+
+ - Memory Partitioning And Monitoring is an Armv8.4 feature that enables
+ various memory system components and resources to define partitions.
+ Software running at various ELs can then assign themselves to the
+ desired partition to control their performance aspects.
+
+ - When ENABLE_MPAM_FOR_LOWER_ELS is set to 1, EL3 allows
+ lower ELs to access their own MPAM registers without trapping to EL3.
+ This patch however, doesn't make use of partitioning in EL3; platform
+ initialisation code should configure and use partitions in EL3 if
+ required.
+
+- Introduce ROM Lib Feature
+
+ - Support combining several libraries into a self-called "romlib" image,
+ that may be shared across images to reduce memory footprint. The romlib
+ image is stored in ROM but is accessed through a jump-table that may be
+ stored in read-write memory, allowing for the library code to be patched.
+
+- Introduce Backtrace Feature
+
+ - This function displays the backtrace, the current EL and security state
+ to allow a post-processing tool to choose the right binary to interpret
+ the dump.
+
+ - Print backtrace in assert() and panic() to the console.
+
+- Code hygiene changes and alignment with MISRA C-2012 guideline with fixes
+ addressing issues complying to the following rules:
+
+ - MISRA rules 4.9, 5.1, 5.3, 5.7, 8.2-8.5, 8.8, 8.13, 9.3, 10.1,
+ 10.3-10.4, 10.8, 11.3, 11.6, 12.1, 14.4, 15.7, 16.1-16.7, 17.7-17.8,
+ 20.7, 20.10, 20.12, 21.1, 21.15, 22.7
+
+ - Clean up the usage of void pointers to access symbols
+
+ - Increase usage of static qualifier to locally used functions and data
+
+ - Migrated to use of u_register_t for register read/write to better
+ match AArch32 and AArch64 type sizes
+
+ - Use int-ll64 for both AArch32 and AArch64 to assist in consistent
+ format strings between architectures
+
+ - Clean up TF-A libc by removing non arm copyrighted implementations
+ and replacing them with modified FreeBSD and SCC implementations
+
+- Various changes to support Clang linker and assembler
+
+ - The clang assembler/preprocessor is used when Clang is selected however,
+ the clang linker is not used because it is unable to link TF-A objects
+ due to immaturity of clang linker functionality at this time.
+
+- Refactor support API's into Libraries
+
+ - Evolve libfdt, mbed TLS library and standard C library sources as
+ proper libraries that TF-A may be linked against.
+
+- CPU Enhancements
+
+ - Add CPU support for Cortex-Ares and Cortex-A76
+
+ - Add AMU support for Cortex-Ares
+
+ - Add initial CPU support for Cortex-Deimos
+
+ - Add initial CPU support for Cortex-Helios
+
+ - Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76
+
+ - Implement Cortex-Ares erratum 1043202 workaround
+
+ - Implement DSU erratum 936184 workaround
+
+ - Check presence of fix for errata 843419 in Cortex-A53
+
+ - Check presence of fix for errata 835769 in Cortex-A53
+
+- Translation Tables Enhancements
+
+ - The xlat v2 library has been refactored in order to be reused by
+ different TF components at different EL's including the addition of EL2.
+ Some refactoring to make the code more generic and less specific to TF,
+ in order to reuse the library outside of this project.
+
+- SPM Enhancements
+
+ - General cleanups and refactoring to pave the way to multiple partitions
+ support
+
+- SDEI Enhancements
+
+ - Allow platforms to define explicit events
+
+ - Determine client EL from NS context's SCR_EL3
+
+ - Make dispatches synchronous
+
+ - Introduce jump primitives for BL31
+
+ - Mask events after CPU wakeup in SDEI dispatcher to conform to the
+ specification
+
+- Misc TF-A Core Common Code Enhancements
+
+ - Add support for eXecute In Place (XIP) memory in BL2
+
+ - Add support for the SMC Calling Convention 2.0
+
+ - Introduce External Abort handling on AArch64
+ External Abort routed to EL3 was reported as an unhandled exception
+ and caused a panic. This change enables Arm Trusted Firmware-A to
+ handle External Aborts routed to EL3.
+
+ - Save value of ACTLR_EL1 implementation-defined register in the CPU
+ context structure rather than forcing it to 0.
+
+ - Introduce ARM_LINUX_KERNEL_AS_BL33 build option, which allows BL31 to
+ directly jump to a Linux kernel. This makes for a quicker and simpler
+ boot flow, which might be useful in some test environments.
+
+ - Add dynamic configurations for BL31, BL32 and BL33 enabling support for
+ Chain of Trust (COT).
+
+ - Make TF UUID RFC 4122 compliant
+
+- New Platform Support
+
+ - Arm SGI-575
+
+ - Arm SGM-775
+
+ - Allwinner sun50i_64
+
+ - Allwinner sun50i_h6
+
+ - NXP ls1043
+
+ - NXP i.MX8QX
+
+ - NXP i.MX8QM
+
+ - TI K3
+
+ - Socionext Synquacer SC2A11
+
+ - Marvell Armada 8K
+
+ - STMicroelectronics STM32MP1
+
+- Misc Generic Platform Common Code Enhancements
+
+ - Add MMC framework that supports both eMMC and SD card devices
+
+- Misc Arm Platform Common Code Enhancements
+
+ - Demonstrate PSCI MEM_PROTECT from el3_runtime
+
+ - Provide RAS support
+
+ - Migrate AArch64 port to the multi console driver. The old API is
+ deprecated and will eventually be removed.
+
+ - Move BL31 below BL2 to enable BL2 overlay resulting in changes in the
+ layout of BL images in memory to enable more efficient use of available
+ space.
+
+ - Add cpp build processing for dtb that allows processing device tree
+ with external includes.
+
+ - Extend FIP io driver to support multiple FIP devices
+
+ - Add support for SCMI AP core configuration protocol v1.0
+
+ - Use SCMI AP core protocol to set the warm boot entrypoint
+
+ - Add support to Mbed TLS drivers for shared heap among different
+ BL images to help optimise memory usage
+
+ - Enable non-secure access to UART1 through a build option to support
+ a serial debug port for debugger connection
+
+- Enhancements for Arm Juno Platform
+
+ - Add support for TrustZone Media Protection 1 (TZMP1)
+
+- Enhancements for Arm FVP Platform
+
+ - Dynamic_config: remove the FVP dtb files
+
+ - Set DYNAMIC_WORKAROUND_CVE_2018_3639=1 on FVP by default
+
+ - Set the ability to dynamically disable Trusted Boot Board
+ authentication to be off by default with DYN_DISABLE_AUTH
+
+ - Add librom enhancement support in FVP
+
+ - Support shared Mbed TLS heap between BL1 and BL2 that allow a
+ reduction in BL2 size for FVP
+
+- Enhancements for Arm SGI/SGM Platform
+
+ - Enable ARM_PLAT_MT flag for SGI-575
+
+ - Add dts files to enable support for dynamic config
+
+ - Add RAS support
+
+ - Support shared Mbed TLS heap for SGI and SGM between BL1 and BL2
+
+- Enhancements for Non Arm Platforms
+
+ - Raspberry Pi Platform
+
+ - Hikey Platforms
+
+ - Xilinx Platforms
+
+ - QEMU Platform
+
+ - Rockchip rk3399 Platform
+
+ - TI Platforms
+
+ - Socionext Platforms
+
+ - Allwinner Platforms
+
+ - NXP Platforms
+
+ - NVIDIA Tegra Platform
+
+ - Marvell Platforms
+
+ - STMicroelectronics STM32MP1 Platform
+
+Issues resolved since last release
+----------------------------------
+
+- No issues known at 1.5 release resolved in 1.6 release
+
+Known Issues
+------------
+
+- DTB creation not supported when building on a Windows host. This step in the
+ build process is skipped when running on a Windows host. Known issue from
+ 1.5 version.
+
Trusted Firmware-A - version 1.5
================================
@@ -287,8 +608,8 @@
Known Issues
------------
-- DTB creation not supported when building on a windows host. This step in the
- build process is skipped when running on a windows host.
+- DTB creation not supported when building on a Windows host. This step in the
+ build process is skipped when running on a Windows host.
Trusted Firmware-A - version 1.4
================================
diff --git a/docs/firmware-design.rst b/docs/firmware-design.rst
index 8aa7622..79bdec9 100644
--- a/docs/firmware-design.rst
+++ b/docs/firmware-design.rst
@@ -394,13 +394,9 @@
Image loading in BL2
^^^^^^^^^^^^^^^^^^^^
-Image loading scheme in BL2 depends on ``LOAD_IMAGE_V2`` build option. If the
-flag is disabled, the BLxx images are loaded, by calling the respective
-load\_blxx() function from BL2 generic code. If the flag is enabled, the BL2
-generic code loads the images based on the list of loadable images provided
-by the platform. BL2 passes the list of executable images provided by the
-platform to the next handover BL image. By default, this flag is disabled for
-AArch64 and the AArch32 build is supported only if this flag is enabled.
+BL2 generic code loads the images based on the list of loadable images
+provided by the platform. BL2 passes the list of executable images
+provided by the platform to the next handover BL image.
The list of loadable images provided by the platform may also contain
dynamic configuration files. The files are loaded and can be parsed as
@@ -425,10 +421,7 @@
BL2 loads the EL3 Runtime Software image from platform storage into a platform-
specific address in trusted SRAM. If there is not enough memory to load the
-image or image is missing it leads to an assertion failure. If ``LOAD_IMAGE_V2``
-is disabled and if image loads successfully, BL2 updates the amount of trusted
-SRAM used and available for use by EL3 Runtime Software. This information is
-populated at a platform-specific memory address.
+image or image is missing it leads to an assertion failure.
AArch64 BL32 (Secure-EL1 Payload) image load
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1281,47 +1274,22 @@
GIC driver (either GICv2 or GICv3, as selected by the platform) with the
interrupt configuration during the driver initialisation.
-There are two ways to specify secure interrupt configuration:
+Secure interrupt configuration are specified in an array of secure interrupt
+properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
+``interrupt_props`` member points to an array of interrupt properties. Each
+element of the array specifies the interrupt number and its configuration, viz.
+priority, group, configuration. Each element of the array shall be populated by
+the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
-#. Array of secure interrupt properties: In this scheme, in both GICv2 and GICv3
- driver data structures, the ``interrupt_props`` member points to an array of
- interrupt properties. Each element of the array specifies the interrupt
- number and its configuration, viz. priority, group, configuration. Each
- element of the array shall be populated by the macro ``INTR_PROP_DESC()``.
- The macro takes the following arguments:
+- 10-bit interrupt number,
- - 10-bit interrupt number,
+- 8-bit interrupt priority,
- - 8-bit interrupt priority,
+- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
+ ``INTR_TYPE_NS``),
- - Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
- ``INTR_TYPE_NS``),
-
- - Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
- ``GIC_INTR_CFG_EDGE``).
-
-#. Array of secure interrupts: In this scheme, the GIC driver is provided an
- array of secure interrupt numbers. The GIC driver, at the time of
- initialisation, iterates through the array and assigns each interrupt
- the appropriate group.
-
- - For the GICv2 driver, in ``gicv2_driver_data`` structure, the
- ``g0_interrupt_array`` member of the should point to the array of
- interrupts to be assigned to *Group 0*, and the ``g0_interrupt_num``
- member of the should be set to the number of interrupts in the array.
-
- - For the GICv3 driver, in ``gicv3_driver_data`` structure:
-
- - The ``g0_interrupt_array`` member of the should point to the array of
- interrupts to be assigned to *Group 0*, and the ``g0_interrupt_num``
- member of the should be set to the number of interrupts in the array.
-
- - The ``g1s_interrupt_array`` member of the should point to the array of
- interrupts to be assigned to *Group 1 Secure*, and the
- ``g1s_interrupt_num`` member of the should be set to the number of
- interrupts in the array.
-
- **Note that this scheme is deprecated.**
+- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
+ ``GIC_INTR_CFG_EDGE``).
CPU specific operations framework
---------------------------------
@@ -1650,83 +1618,13 @@
on FVP, BL31 and TSP need to know the limit address that their PROGBITS
sections must not overstep. The platform code must provide those.
-When LOAD\_IMAGE\_V2 is disabled, TF-A provides a mechanism to verify at boot
-time that the memory to load a new image is free to prevent overwriting a
-previously loaded image. For this mechanism to work, the platform must specify
-the memory available in the system as regions, where each region consists of
-base address, total size and the free area within it (as defined in the
-``meminfo_t`` structure). TF-A retrieves these memory regions by calling the
-corresponding platform API:
-
-- ``meminfo_t *bl1_plat_sec_mem_layout(void)``
-- ``meminfo_t *bl2_plat_sec_mem_layout(void)``
-- ``void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)``
-- ``void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)``
-- ``void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)``
+TF-A does not provide any mechanism to verify at boot time that the memory
+to load a new image is free to prevent overwriting a previously loaded image.
+The platform must specify the memory available in the system for all the
+relevant BL images to be loaded.
For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
return the region defined by the platform where BL1 intends to load BL2. The
-``load_image()`` function will check that the memory where BL2 will be loaded is
-within the specified region and marked as free.
-
-The actual number of regions and their base addresses and sizes is platform
-specific. The platform may return the same region or define a different one for
-each API. However, the overlap verification mechanism applies only to a single
-region. Hence, it is the platform responsibility to guarantee that different
-regions do not overlap, or that if they do, the overlapping images are not
-accessed at the same time. This could be used, for example, to load temporary
-images (e.g. certificates) or firmware images prior to being transfered to its
-corresponding processor (e.g. the SCP BL2 image).
-
-To reduce fragmentation and simplify the tracking of free memory, all the free
-memory within a region is always located in one single buffer defined by its
-base address and size. TF-A implements a top/bottom load approach:
-after a new image is loaded, it checks how much memory remains free above and
-below the image. The smallest area is marked as unavailable, while the larger
-area becomes the new free memory buffer. Platforms should take this behaviour
-into account when defining the base address for each of the images. For example,
-if an image is loaded near the middle of the region, small changes in image size
-could cause a flip between a top load and a bottom load, which may result in an
-unexpected memory layout.
-
-The following diagram is an example of an image loaded in the bottom part of
-the memory region. The region is initially free (nothing has been loaded yet):
-
-::
-
- Memory region
- +----------+
- | |
- | | <<<<<<<<<<<<< Free
- | |
- |----------| +------------+
- | image | <<<<<<<<<<<<< | image |
- |----------| +------------+
- | xxxxxxxx | <<<<<<<<<<<<< Marked as unavailable
- +----------+
-
-And the following diagram is an example of an image loaded in the top part:
-
-::
-
- Memory region
- +----------+
- | xxxxxxxx | <<<<<<<<<<<<< Marked as unavailable
- |----------| +------------+
- | image | <<<<<<<<<<<<< | image |
- |----------| +------------+
- | |
- | | <<<<<<<<<<<<< Free
- | |
- +----------+
-
-When LOAD\_IMAGE\_V2 is enabled, TF-A does not provide any mechanism to verify
-at boot time that the memory to load a new image is free to prevent overwriting
-a previously loaded image. The platform must specify the memory available in
-the system for all the relevant BL images to be loaded.
-
-For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
-return the region defined by the platform where BL1 intends to load BL2. The
``load_image()`` function performs bounds check for the image size based on the
base and maximum image size provided by the platforms. Platforms must take
this behaviour into account when defining the base/size for each of the images.
@@ -1774,43 +1672,6 @@
When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
BL31.
-When LOAD\_IMAGE\_V2 is disabled the memory regions for the overlap detection
-mechanism at boot time are defined as follows (shown per API):
-
-- ``meminfo_t *bl1_plat_sec_mem_layout(void)``
-
- This region corresponds to the whole Trusted SRAM except for the shared
- memory at the base. This region is initially free. At boot time, BL1 will
- mark the BL1(rw) section within this region as occupied. The BL1(rw) section
- is placed at the top of Trusted SRAM.
-
-- ``meminfo_t *bl2_plat_sec_mem_layout(void)``
-
- This region corresponds to the whole Trusted SRAM as defined by
- ``bl1_plat_sec_mem_layout()``, but with the BL1(rw) section marked as
- occupied. This memory region is used to check that BL2 and BL31 do not
- overlap with each other. BL2\_BASE and BL1\_RW\_BASE are carefully chosen so
- that the memory for BL31 is top loaded above BL2.
-
-- ``void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)``
-
- This region is an exact copy of the region defined by
- ``bl2_plat_sec_mem_layout()``. Being a disconnected copy means that all the
- changes made to this region by the TF-A will not be propagated. This
- approach is valid because the SCP BL2 image is loaded temporarily while it
- is being transferred to the SCP, so this memory is reused afterwards.
-
-- ``void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)``
-
- This region depends on the location of the BL32 image. Currently, Arm
- platforms support three different locations (detailed below): Trusted SRAM,
- Trusted DRAM and the TZC-Secured DRAM.
-
-- ``void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)``
-
- This region corresponds to the Non-Secure DDR-DRAM, excluding the
- TZC-Secured area.
-
The location of the BL32 image will result in different memory maps. This is
illustrated for both FVP and Juno in the following diagrams, using the TSP as
an example.
diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst
index 4280241..2b48ba9 100644
--- a/docs/plat/xilinx-zynqmp.rst
+++ b/docs/plat/xilinx-zynqmp.rst
@@ -14,13 +14,13 @@
.. code:: bash
- make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31
To build bl32 TSP you have to rebuild bl31 too:
.. code:: bash
- make ERROR_DEPRECATED=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
ZynqMP platform specific build options
======================================
diff --git a/docs/platform-compatibility-policy.rst b/docs/platform-compatibility-policy.rst
new file mode 100644
index 0000000..b33c4e7
--- /dev/null
+++ b/docs/platform-compatibility-policy.rst
@@ -0,0 +1,45 @@
+TF-A Platform Compatibility Policy
+======================================================
+
+
+.. section-numbering::
+ :suffix: .
+
+.. contents::
+
+--------------
+
+Introduction
+------------
+
+This document clarifies the project's policy around compatibility for upstream
+platforms.
+
+Platform compatibility policy
+-----------------------------
+
+Platform compatibility is mainly affected by changes to Platform APIs (as
+documented in the `Porting Guide`_), driver APIs (like the GICv3 drivers) or
+library interfaces (like xlat_table library). The project will try to maintain
+compatibility for upstream platforms. Due to evolving requirements and
+enhancements, there might be changes affecting platform compatibility which
+means the previous interface needs to be deprecated and a new interface
+introduced to replace it. In case the migration to the new interface is trivial,
+the contributor of the change is expected to make good effort to migrate the
+upstream platforms to the new interface.
+
+The `Release information`_ documents the deprecated interfaces and the intended
+release after which it will be removed. When an interface is deprecated, the
+page must be updated to indicate the release after which the interface will be
+removed. This must be at least 1 full release cycle in future. For non-trivial
+interface changes, a `tf-issue`_ should be posted to notify platforms that they
+should migrate away from the deprecated interfaces. Platforms are expected to
+migrate before the removal of the deprecated interface.
+
+--------------
+
+*Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.*
+
+.. _Porting Guide: ./porting-guide.rst
+.. _Release information: https://github.com/ARM-software/arm-trusted-firmware/wiki/TF-A-Release-information#2removal-of-deprecated-interfaces
+.. _tf-issue: https://github.com/ARM-software/tf-issues/issues
diff --git a/docs/platform-migration-guide.rst b/docs/platform-migration-guide.rst
deleted file mode 100644
index 87d35f4..0000000
--- a/docs/platform-migration-guide.rst
+++ /dev/null
@@ -1,608 +0,0 @@
-Guide to migrate to new Platform porting interface
-==================================================
-
-
-.. section-numbering::
- :suffix: .
-
-.. contents::
-
---------------
-
-Introduction
-------------
-
-The PSCI implementation in TF-A has undergone a redesign because of three
-requirements that the PSCI 1.0 specification introduced :
-
-- Removing the framework assumption about the structure of the MPIDR, and
- its relation to the power topology enables support for deeper and more
- complex hierarchies.
-
-- Reworking the power state coordination implementation in the framework
- to support the more detailed PSCI 1.0 requirements and reduce platform
- port complexity
-
-- Enable the use of the extended power\_state parameter and the larger StateID
- field
-
-The PSCI 1.0 implementation introduces new frameworks to fulfill the above
-requirements. These framework changes mean that the platform porting API must
-also be modified. This document is a guide to assist migration of the existing
-platform ports to the new platform API.
-
-This document describes the new platform API and compares it with the
-deprecated API. It also describes the compatibility layer that enables the
-existing platform ports to work with the PSCI 1.0 implementation. The
-deprecated platform API is documented for reference.
-
-Platform API modification due to PSCI framework changes
--------------------------------------------------------
-
-This section describes changes to the platform APIs.
-
-Power domain topology framework platform API modifications
-----------------------------------------------------------
-
-This removes the assumption in the PSCI implementation that MPIDR
-based affinity instances map directly to power domains. A power domain, as
-described in section 4.2 of `PSCI`_, could contain a core or a logical group
-of cores (a cluster) which share some state on which power management
-operations can be performed. The existing affinity instance based APIs
-``plat_get_aff_count()`` and ``plat_get_aff_state()`` are deprecated. The new
-platform interfaces that are introduced for this framework are:
-
-- ``plat_core_pos_by_mpidr()``
-- ``plat_my_core_pos()``
-- ``plat_get_power_domain_tree_desc()``
-
-``plat_my_core_pos()`` and ``plat_core_pos_by_mpidr()`` are mandatory
-and are meant to replace the existing ``platform_get_core_pos()`` API.
-The description of these APIs can be found in the `Porting Guide`_.
-These are used by the power domain topology framework such that:
-
-#. The generic PSCI code does not generate MPIDRs or use them to query the
- platform about the number of power domains at a particular power level. The
- ``plat_get_power_domain_tree_desc()`` provides a description of the power
- domain tree on the SoC through a pointer to the byte array containing the
- power domain topology tree description data structure.
-
-#. The linear indices returned by ``plat_core_pos_by_mpidr()`` and
- ``plat_my_core_pos()`` are used to retrieve core power domain nodes from
- the power domain tree. These core indices are unique for a core and it is a
- number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The platform can choose
- to implement a static mapping between ``MPIDR`` and core index or implement
- a dynamic mapping, choosing to skip the unavailable/unused cores to compact
- the core indices.
-
-In addition, the platforms must define the macros ``PLAT_NUM_PWR_DOMAINS`` and
-``PLAT_MAX_PWR_LVL`` which replace the macros ``PLAT_NUM_AFFS`` and
-``PLATFORM_MAX_AFFLVL`` respectively. On platforms where the affinity instances
-correspond to power domains, the values of new macros remain the same as the
-old ones.
-
-More details on the power domain topology description and its platform
-interface can be found in `psci pd tree`_.
-
-Composite power state framework platform API modifications
-----------------------------------------------------------
-
-The state-ID field in the power-state parameter of a CPU\_SUSPEND call can be
-used to describe the composite power states specific to a platform. The existing
-PSCI state coordination had the limitation that it operates on a run/off
-granularity of power states and it did not interpret the state-ID field. This
-was acceptable as the specification requirement in PSCI 0.2 and the framework's
-approach to coordination only required maintaining a reference
-count of the number of cores that have requested the cluster to remain powered.
-
-In the PSCI 1.0 specification, this approach is non optimal. If composite
-power states are used, the PSCI implementation cannot make global
-decisions about state coordination required because it does not understand the
-platform specific states.
-
-The PSCI 1.0 implementation now defines a generic representation of the
-power-state parameter :
-
-.. code:: c
-
- typedef struct psci_power_state {
- plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1];
- } psci_power_state_t;
-
-``pwr_domain_state`` is an array where each index corresponds to a power level.
-Each entry in the array contains the local power state the power domain at
-that power level could enter. The meaning of the local power state value is
-platform defined, and can vary between levels in a single platform. The PSCI
-implementation constraints the values only so that it can classify the state
-as RUN, RETENTION or OFF as required by the specification:
-
-#. Zero means RUN
-
-#. All OFF state values at all levels must be higher than all
- RETENTION state values at all levels
-
-The platform is required to define the macros ``PLAT_MAX_RET_STATE`` and
-``PLAT_MAX_OFF_STATE`` to the framework. The requirement for these macros can
-be found in the `Porting Guide <porting-guide.rst>`__.
-
-The PSCI 1.0 implementation adds support to involve the platform in state
-coordination. This enables the platform to decide the final target state.
-During a request to place a power domain in a low power state, the platform
-is passed an array of requested ``plat_local_state_t`` for that power domain by
-each core within it through the ``plat_get_target_pwr_state()`` API. This API
-coordinates amongst these requested states to determine a target
-``plat_local_state_t`` for that power domain. A default weak implementation of
-this API is provided in the platform layer which returns the minimum of the
-requested local states back to the PSCI state coordination. More details
-of ``plat_get_target_pwr_state()`` API can be found in the
-`Porting Guide <porting-guide.rst#user-content-function--plat_get_target_pwr_state-optional>`__.
-
-The PSCI Generic implementation expects platform ports to populate the handlers
-for the ``plat_psci_ops`` structure which is declared as :
-
-.. code:: c
-
- typedef struct plat_psci_ops {
- void (*cpu_standby)(plat_local_state_t cpu_state);
- int (*pwr_domain_on)(u_register_t mpidr);
- void (*pwr_domain_off)(const psci_power_state_t *target_state);
- void (*pwr_domain_suspend_early)(const psci_power_state_t *target_state);
- void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
- void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
- void (*pwr_domain_suspend_finish)(
- const psci_power_state_t *target_state);
- void (*system_off)(void) __dead2;
- void (*system_reset)(void) __dead2;
- int (*validate_power_state)(unsigned int power_state,
- psci_power_state_t *req_state);
- int (*validate_ns_entrypoint)(unsigned long ns_entrypoint);
- void (*get_sys_suspend_power_state)(
- psci_power_state_t *req_state);
- int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
- int pwrlvl);
- int (*translate_power_state_by_mpidr)(u_register_t mpidr,
- unsigned int power_state,
- psci_power_state_t *output_state);
- int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
- int (*mem_protect_chk)(uintptr_t base, u_register_t length);
- int (*read_mem_protect)(int *val);
- int (*write_mem_protect)(int val);
- int (*system_reset2)(int is_vendor,
- int reset_type, u_register_t cookie);
- } plat_psci_ops_t;
-
-The description of these handlers can be found in the `Porting Guide <porting-guide.rst#user-content-function--plat_setup_psci_ops-mandatory>`__.
-The previous ``plat_pm_ops`` structure is deprecated. Compared with the previous
-handlers, the major differences are:
-
-- Difference in parameters
-
-The PSCI 1.0 implementation depends on the ``validate_power_state`` handler to
-convert the power-state parameter (possibly encoding a composite power state)
-passed in a PSCI ``CPU_SUSPEND`` to the ``psci_power_state`` format. This handler
-is now mandatory for PSCI ``CPU_SUSPEND`` support.
-
-The ``plat_psci_ops`` handlers, ``pwr_domain_off``, ``pwr_domain_suspend_early``
-and ``pwr_domain_suspend``, are passed the target local state for each affected
-power domain. The platform must execute operations specific to these target
-states. Similarly, ``pwr_domain_on_finish`` and ``pwr_domain_suspend_finish``
-are passed the local states of the affected power domains before wakeup. The
-platform must execute actions to restore these power domains from these specific
-local states.
-
-- Difference in invocation
-
-Whereas the power management handlers in ``plat_pm_ops`` used to be invoked
-for each affinity level till the target affinity level, the new handlers
-are only invoked once. The ``target_state`` encodes the target low power
-state or the low power state woken up from for each affected power domain.
-
-- Difference in semantics
-
-Although the previous ``suspend`` handlers could be used for power down as well
-as retention at different affinity levels, the new handlers make this support
-explicit. The ``pwr_domain_suspend`` can be used to specify powerdown and
-retention at various power domain levels subject to the conditions mentioned
-in section 4.2.1 of `PSCI`_
-
-Unlike the previous ``standby`` handler, the ``cpu_standby()`` handler is only used
-as a fast path for placing a core power domain into a standby or retention
-state.
-
-The below diagram shows the sequence of a PSCI SUSPEND call and the interaction
-with the platform layer depicting the exchange of data between PSCI Generic
-layer and the platform layer.
-
-|Image 1|
-
-Refer `plat/arm/board/fvp/fvp\_pm.c`_ for the implementation details of
-these handlers for the FVP. The commit `38dce70f51fb83b27958ba3e2ad15f5635cb1061`_
-demonstrates the migration of Arm reference platforms to the new platform API.
-
-Miscellaneous modifications
----------------------------
-
-In addition to the framework changes, unification of warm reset entry points on
-wakeup from low power modes has led to a change in the platform API. In the
-earlier implementation, the warm reset entry used to be programmed into the
-mailboxes by the 'ON' and 'SUSPEND' power management hooks. In the PSCI 1.0
-implementation, this information is not required, because it can figure that
-out by querying affinity info state whether to execute the 'suspend\_finisher\`
-or 'on\_finisher'.
-
-As a result, the warm reset entry point must be programmed only once. The
-``plat_setup_psci_ops()`` API takes the secure entry point as an
-additional parameter to enable the platforms to configure their mailbox. The
-plat\_psci\_ops handlers ``pwr_domain_on`` and ``pwr_domain_suspend`` no longer take
-the warm reset entry point as a parameter.
-
-Also, some platform APIs which took ``MPIDR`` as an argument were only ever
-invoked to perform actions specific to the caller core which makes the argument
-redundant. Therefore the platform APIs ``plat_get_my_entrypoint()``,
-``plat_is_my_cpu_primary()``, ``plat_set_my_stack()`` and
-``plat_get_my_stack()`` are defined which are meant to be invoked only for
-operations on the current caller core instead of ``platform_get_entrypoint()``,
-``platform_is_primary_cpu()``, ``platform_set_stack()`` and ``platform_get_stack()``.
-
-Compatibility layer
--------------------
-
-To ease the migration of the platform ports to the new porting interface,
-a compatibility layer is introduced that essentially implements a glue layer
-between the old platform API and the new API. The build flag
-``ENABLE_PLAT_COMPAT`` (enabled by default), specifies whether to enable this
-layer or not. A platform port which has migrated to the new API can disable
-this flag within the platform specific makefile.
-
-The compatibility layer works on the assumption that the onus of
-state coordination, in case multiple low power states are supported,
-is with the platform. The generic PSCI implementation only takes into
-account whether the suspend request is power down or not. This corresponds
-with the behavior of the PSCI implementation before the introduction of
-new frameworks. Also, it assumes that the affinity levels of the platform
-correspond directly to the power domain levels.
-
-The compatibility layer dynamically constructs the new topology
-description array by querying the platform using ``plat_get_aff_count()``
-and ``plat_get_aff_state()`` APIs. The linear index returned by
-``platform_get_core_pos()`` is used as the core index for the cores. The
-higher level (non-core) power domain nodes must know the cores contained
-within its domain. It does so by storing the core index of first core
-within it and number of core indexes following it. This means that core
-indices returned by ``platform_get_core_pos()`` for cores within a particular
-power domain must be consecutive. We expect that this is the case for most
-platform ports including Arm reference platforms.
-
-The old PSCI helpers like ``psci_get_suspend_powerstate()``,
-``psci_get_suspend_stateid()``, ``psci_get_suspend_stateid_by_mpidr()``,
-``psci_get_max_phys_off_afflvl()`` and ``psci_get_suspend_afflvl()`` are also
-implemented for the compatibility layer. This allows the existing
-platform ports to work with the new PSCI frameworks without significant
-rework.
-
-Deprecated Platform API
------------------------
-
-This section documents the deprecated platform porting API.
-
-Common mandatory modifications
-------------------------------
-
-The mandatory macros to be defined by the platform port in ``platform_def.h``
-
-- **#define : PLATFORM\_NUM\_AFFS**
-
- Defines the total number of nodes in the affinity hierarchy at all affinity
- levels used by the platform.
-
-- **#define : PLATFORM\_MAX\_AFFLVL**
-
- Defines the maximum affinity level that the power management operations
- should apply to. Armv8-A has support for four affinity levels. It is likely
- that hardware will implement fewer affinity levels. This macro allows the
- PSCI implementation to consider only those affinity levels in the system
- that the platform implements. For example, the Base AEM FVP implements two
- clusters with a configurable number of cores. It reports the maximum
- affinity level as 1, resulting in PSCI power control up to the cluster
- level.
-
-The following functions must be implemented by the platform port to enable
-the reset vector code to perform the required tasks.
-
-Function : platform\_get\_entrypoint() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned long
- Return : unsigned long
-
-This function is called with the ``SCTLR.M`` and ``SCTLR.C`` bits disabled. The core
-is identified by its ``MPIDR``, which is passed as the argument. The function is
-responsible for distinguishing between a warm and cold reset using platform-
-specific means. If it is a warm reset, it returns the entrypoint into the
-BL31 image that the core must jump to. If it is a cold reset, this function
-must return zero.
-
-This function is also responsible for implementing a platform-specific mechanism
-to handle the condition where the core has been warm reset but there is no
-entrypoint to jump to.
-
-This function does not follow the Procedure Call Standard used by the
-Application Binary Interface for the Arm 64-bit architecture. The caller should
-not assume that callee saved registers are preserved across a call to this
-function.
-
-Function : platform\_is\_primary\_cpu() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned long
- Return : unsigned int
-
-This function identifies a core by its ``MPIDR``, which is passed as the argument,
-to determine whether this core is the primary core or a secondary core. A return
-value of zero indicates that the core is not the primary core, while a non-zero
-return value indicates that the core is the primary core.
-
-Common optional modifications
------------------------------
-
-Function : platform\_get\_core\_pos()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned long
- Return : int
-
-A platform may need to convert the ``MPIDR`` of a core to an absolute number, which
-can be used as a core-specific linear index into blocks of memory (for example
-while allocating per-core stacks). This routine contains a simple mechanism
-to perform this conversion, using the assumption that each cluster contains a
-maximum of four cores:
-
-::
-
- linear index = cpu_id + (cluster_id * 4)
-
- cpu_id = 8-bit value in MPIDR at affinity level 0
- cluster_id = 8-bit value in MPIDR at affinity level 1
-
-Function : platform\_set\_stack()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned long
- Return : void
-
-This function sets the current stack pointer to the normal memory stack that
-has been allocated for the core specified by MPIDR. For BL images that only
-require a stack for the primary core the parameter is ignored. The size of
-the stack allocated to each core is specified by the platform defined constant
-``PLATFORM_STACK_SIZE``.
-
-Common implementations of this function for the UP and MP BL images are
-provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
-`plat/common/aarch64/platform\_mp\_stack.S`_
-
-Function : platform\_get\_stack()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned long
- Return : unsigned long
-
-This function returns the base address of the normal memory stack that
-has been allocated for the core specificed by MPIDR. For BL images that only
-require a stack for the primary core the parameter is ignored. The size of
-the stack allocated to each core is specified by the platform defined constant
-``PLATFORM_STACK_SIZE``.
-
-Common implementations of this function for the UP and MP BL images are
-provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
-`plat/common/aarch64/platform\_mp\_stack.S`_
-
-Modifications for Power State Coordination Interface (in BL31)
---------------------------------------------------------------
-
-The following functions must be implemented to initialize PSCI functionality in
-TF-A.
-
-Function : plat\_get\_aff\_count() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned int, unsigned long
- Return : unsigned int
-
-This function may execute with the MMU and data caches enabled if the platform
-port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
-called by the primary core.
-
-This function is called by the PSCI initialization code to detect the system
-topology. Its purpose is to return the number of affinity instances implemented
-at a given ``affinity level`` (specified by the first argument) and a given
-``MPIDR`` (specified by the second argument). For example, on a dual-cluster
-system where first cluster implements two cores and the second cluster
-implements four cores, a call to this function with an ``MPIDR`` corresponding
-to the first cluster (``0x0``) and affinity level 0, would return 2. A call
-to this function with an ``MPIDR`` corresponding to the second cluster (``0x100``)
-and affinity level 0, would return 4.
-
-Function : plat\_get\_aff\_state() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : unsigned int, unsigned long
- Return : unsigned int
-
-This function may execute with the MMU and data caches enabled if the platform
-port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
-called by the primary core.
-
-This function is called by the PSCI initialization code. Its purpose is to
-return the state of an affinity instance. The affinity instance is determined by
-the affinity ID at a given ``affinity level`` (specified by the first argument)
-and an ``MPIDR`` (specified by the second argument). The state can be one of
-``PSCI_AFF_PRESENT`` or ``PSCI_AFF_ABSENT``. The latter state is used to cater for
-system topologies where certain affinity instances are unimplemented. For
-example, consider a platform that implements a single cluster with four cores and
-another core implemented directly on the interconnect with the cluster. The
-``MPIDR``\ s of the cluster would range from ``0x0-0x3``. The ``MPIDR`` of the single
-core is 0x100 to indicate that it does not belong to cluster 0. Cluster 1
-is missing but needs to be accounted for to reach this single core in the
-topology tree. Therefore it is marked as ``PSCI_AFF_ABSENT``.
-
-Function : platform\_setup\_pm() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : const plat_pm_ops **
- Return : int
-
-This function may execute with the MMU and data caches enabled if the platform
-port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
-called by the primary core.
-
-This function is called by PSCI initialization code. Its purpose is to export
-handler routines for platform-specific power management actions by populating
-the passed pointer with a pointer to the private ``plat_pm_ops`` structure of
-BL31.
-
-A description of each member of this structure is given below. A platform port
-is expected to implement these handlers if the corresponding PSCI operation
-is to be supported and these handlers are expected to succeed if the return
-type is ``void``.
-
-plat\_pm\_ops.affinst\_standby()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Perform the platform-specific setup to enter the standby state indicated by the
-passed argument. The generic code expects the handler to succeed.
-
-plat\_pm\_ops.affinst\_on()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Perform the platform specific setup to power on an affinity instance, specified
-by the ``MPIDR`` (first argument) and ``affinity level`` (third argument). The
-``state`` (fourth argument) contains the current state of that affinity instance
-(ON or OFF). This is useful to determine whether any action must be taken. For
-example, while powering on a core, the cluster that contains this core might
-already be in the ON state. The platform decides what actions must be taken to
-transition from the current state to the target state (indicated by the power
-management operation). The generic code expects the platform to return
-E\_SUCCESS on success or E\_INTERN\_FAIL for any failure.
-
-plat\_pm\_ops.affinst\_off()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Perform the platform specific setup to power off an affinity instance of the
-calling core. It is called by the PSCI ``CPU_OFF`` API implementation.
-
-The ``affinity level`` (first argument) and ``state`` (second argument) have
-a similar meaning as described in the ``affinst_on()`` operation. They
-identify the affinity instance on which the call is made and its
-current state. This gives the platform port an indication of the
-state transition it must make to perform the requested action. For example, if
-the calling core is the last powered on core in the cluster, after powering down
-affinity level 0 (the core), the platform port should power down affinity
-level 1 (the cluster) as well. The generic code expects the handler to succeed.
-
-plat\_pm\_ops.affinst\_suspend()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Perform the platform specific setup to power off an affinity instance of the
-calling core. It is called by the PSCI ``CPU_SUSPEND`` API and ``SYSTEM_SUSPEND``
-API implementation
-
-The ``affinity level`` (second argument) and ``state`` (third argument) have a
-similar meaning as described in the ``affinst_on()`` operation. They are used to
-identify the affinity instance on which the call is made and its current state.
-This gives the platform port an indication of the state transition it must
-make to perform the requested action. For example, if the calling core is the
-last powered on core in the cluster, after powering down affinity level 0
-(the core), the platform port should power down affinity level 1 (the cluster)
-as well.
-
-The difference between turning an affinity instance off and suspending it
-is that in the former case, the affinity instance is expected to re-initialize
-its state when it is next powered on (see ``affinst_on_finish()``). In the latter
-case, the affinity instance is expected to save enough state so that it can
-resume execution by restoring this state when it is powered on (see
-``affinst_suspend_finish()``).The generic code expects the handler to succeed.
-
-plat\_pm\_ops.affinst\_on\_finish()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This function is called by the PSCI implementation after the calling core is
-powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
-It performs the platform-specific setup required to initialize enough state for
-this core to enter the Normal world and also provide secure runtime firmware
-services.
-
-The ``affinity level`` (first argument) and ``state`` (second argument) have a
-similar meaning as described in the previous operations. The generic code
-expects the handler to succeed.
-
-plat\_pm\_ops.affinst\_suspend\_finish()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This function is called by the PSCI implementation after the calling core is
-powered on and released from reset in response to an asynchronous wakeup
-event, for example a timer interrupt that was programmed by the core during the
-``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
-setup required to restore the saved state for this core to resume execution
-in the Normal world and also provide secure runtime firmware services.
-
-The ``affinity level`` (first argument) and ``state`` (second argument) have a
-similar meaning as described in the previous operations. The generic code
-expects the platform to succeed.
-
-plat\_pm\_ops.validate\_power\_state()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This function is called by the PSCI implementation during the ``CPU_SUSPEND``
-call to validate the ``power_state`` parameter of the PSCI API. If the
-``power_state`` is known to be invalid, the platform must return
-PSCI\_E\_INVALID\_PARAMS as an error, which is propagated back to the Normal
-world PSCI client.
-
-plat\_pm\_ops.validate\_ns\_entrypoint()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
-``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the Non-secure ``entry_point``
-parameter passed by the Normal world. If the ``entry_point`` is known to be
-invalid, the platform must return PSCI\_E\_INVALID\_PARAMS as an error, which is
-propagated back to the Normal world PSCI client.
-
-plat\_pm\_ops.get\_sys\_suspend\_power\_state()
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
-call to return the ``power_state`` parameter. This allows the platform to encode
-the appropriate State-ID field within the ``power_state`` parameter which can be
-utilized in ``affinst_suspend()`` to suspend to system affinity level. The
-``power_state`` parameter should be in the same format as specified by the
-PSCI specification for the CPU\_SUSPEND API.
-
---------------
-
-*Copyright (c) 2015-2018, Arm Limited and Contributors. All rights reserved.*
-
-.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
-.. _Porting Guide: porting-guide.rst#user-content-function--plat_my_core_pos
-.. _psci pd tree: psci-pd-tree.rst
-.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
-.. _38dce70f51fb83b27958ba3e2ad15f5635cb1061: https://github.com/ARM-software/arm-trusted-firmware/commit/38dce70f51fb83b27958ba3e2ad15f5635cb1061
-.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S
-.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S
-
-.. |Image 1| image:: diagrams/psci-suspend-sequence.png?raw=true
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index 84f4c9d..1667cce 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -12,10 +12,6 @@
Introduction
------------
-Please note that this document has been updated for the new platform API
-as required by the PSCI v1.0 implementation. Please refer to the
-`Migration Guide`_ for the previous platform API.
-
Porting Trusted Firmware-A (TF-A) to a new platform involves making some
mandatory and optional modifications for both the cold and warm boot paths.
Modifications consist of:
@@ -45,6 +41,9 @@
This document should be read in conjunction with the TF-A `User Guide`_.
+Please refer to the `Platform compatibility policy`_ for the policy regarding
+compatibility and deprecation of these porting interfaces.
+
Common modifications
--------------------
@@ -481,13 +480,6 @@
enabled for a BL image, ``MAX_MMAP_REGIONS`` must be defined to accommodate
the dynamic regions as well.
-- **#define : ADDR\_SPACE\_SIZE**
-
- Defines the total size of the address space in bytes. For example, for a 32
- bit address space, this value should be ``(1ULL << 32)``. This definition is
- now deprecated, platforms should use ``PLAT_PHY_ADDR_SPACE_SIZE`` and
- ``PLAT_VIRT_ADDR_SPACE_SIZE`` instead.
-
- **#define : PLAT\_VIRT\_ADDR\_SPACE\_SIZE**
Defines the total size of the virtual address space in bytes. For example,
@@ -1008,8 +1000,8 @@
Return : bl_load_info_t *
This function returns pointer to the list of images that the platform has
-populated to load. This function is currently invoked in BL2 to load the
-BL3xx images, when LOAD\_IMAGE\_V2 is enabled.
+populated to load. This function is invoked in BL2 to load the
+BL3xx images.
Function : plat\_get\_next\_bl\_params()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1021,8 +1013,8 @@
This function returns a pointer to the shared memory that the platform has
kept aside to pass TF-A related information that next BL image needs. This
-function is currently invoked in BL2 to pass this information to the next BL
-image, when LOAD\_IMAGE\_V2 is enabled.
+function is invoked in BL2 to pass this information to the next BL
+image.
Function : plat\_get\_stack\_protector\_canary()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1051,8 +1043,8 @@
Return : void
This function flushes to main memory all the image params that are passed to
-next image. This function is currently invoked in BL2 to flush this information
-to the next BL image, when LOAD\_IMAGE\_V2 is enabled.
+next image. This function is invoked in BL2 to flush this information
+to the next BL image.
Function : plat\_log\_get\_prefix()
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1119,15 +1111,9 @@
meminfo.total_base = Base address of secure RAM visible to BL2
meminfo.total_size = Size of secure RAM visible to BL2
- meminfo.free_base = Base address of secure RAM available for
- allocation to BL2
- meminfo.free_size = Size of secure RAM available for allocation to BL2
- By default, BL1 places this ``meminfo`` structure at the beginning of the
- free memory available for its use. Since BL1 cannot allocate memory
- dynamically at the moment, its free memory will be available for BL2's use
- as-is. However, this means that BL2 must read the ``meminfo`` structure
- before it starts using its free memory (this is discussed in Section 3.2).
+ By default, BL1 places this ``meminfo`` structure at the end of secure
+ memory visible to BL2.
It is possible for the platform to decide where it wants to place the
``meminfo`` structure for BL2 or restrict the amount of memory visible to
@@ -1357,66 +1343,33 @@
The BL2 stage is executed only by the primary CPU, which is determined in BL1
using the ``platform_is_primary_cpu()`` function. BL1 passed control to BL2 at
-``BL2_BASE``. BL2 executes in Secure EL1 and is responsible for:
-
-#. (Optional) Loading the SCP\_BL2 binary image (if present) from platform
- provided non-volatile storage. To load the SCP\_BL2 image, BL2 makes use of
- the ``meminfo`` returned by the ``bl2_plat_get_scp_bl2_meminfo()`` function.
- The platform also defines the address in memory where SCP\_BL2 is loaded
- through the optional constant ``SCP_BL2_BASE``. BL2 uses this information
- to determine if there is enough memory to load the SCP\_BL2 image.
- Subsequent handling of the SCP\_BL2 image is platform-specific and is
- implemented in the ``bl2_plat_handle_scp_bl2()`` function.
- If ``SCP_BL2_BASE`` is not defined then this step is not performed.
-
-#. Loading the BL31 binary image into secure RAM from non-volatile storage. To
- load the BL31 image, BL2 makes use of the ``meminfo`` structure passed to it
- by BL1. This structure allows BL2 to calculate how much secure RAM is
- available for its use. The platform also defines the address in secure RAM
- where BL31 is loaded through the constant ``BL31_BASE``. BL2 uses this
- information to determine if there is enough memory to load the BL31 image.
-
-#. (Optional) Loading the BL32 binary image (if present) from platform
- provided non-volatile storage. To load the BL32 image, BL2 makes use of
- the ``meminfo`` returned by the ``bl2_plat_get_bl32_meminfo()`` function.
- The platform also defines the address in memory where BL32 is loaded
- through the optional constant ``BL32_BASE``. BL2 uses this information
- to determine if there is enough memory to load the BL32 image.
- If ``BL32_BASE`` is not defined then this and the next step is not performed.
-
-#. (Optional) Arranging to pass control to the BL32 image (if present) that
- has been pre-loaded at ``BL32_BASE``. BL2 populates an ``entry_point_info``
- structure in memory provided by the platform with information about how
- BL31 should pass control to the BL32 image.
-
-#. (Optional) Loading the normal world BL33 binary image (if not loaded by
- other means) into non-secure DRAM from platform storage and arranging for
- BL31 to pass control to this image. This address is determined using the
- ``plat_get_ns_image_entrypoint()`` function described below.
-
-#. BL2 populates an ``entry_point_info`` structure in memory provided by the
- platform with information about how BL31 should pass control to the
- other BL images.
+``BL2_BASE``. BL2 executes in Secure EL1 and and invokes
+``plat_get_bl_image_load_info()`` to retrieve the list of images to load from
+non-volatile storage to secure/non-secure RAM. After all the images are loaded
+then BL2 invokes ``plat_get_next_bl_params()`` to get the list of executable
+images to be passed to the next BL image.
The following functions must be implemented by the platform port to enable BL2
to perform the above tasks.
-Function : bl2\_early\_platform\_setup() [mandatory]
+Function : bl2\_early\_platform\_setup2() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
- Argument : meminfo *
+ Argument : u_register_t, u_register_t, u_register_t, u_register_t
Return : void
This function executes with the MMU and data caches disabled. It is only called
-by the primary CPU. The arguments to this function is the address of the
-``meminfo`` structure populated by BL1.
+by the primary CPU. The 4 arguments are passed by BL1 to BL2 and these arguments
+are platform specific.
-The platform may copy the contents of the ``meminfo`` structure into a private
-variable as the original memory may be subsequently overwritten by BL2. The
-copied structure is made available to all BL2 code through the
-``bl2_plat_sec_mem_layout()`` function.
+On Arm standard platforms, the arguments received are :
+
+ arg0 - Points to load address of HW_CONFIG if present
+
+ arg1 - ``meminfo`` structure populated by BL1. The platform copies
+ the contents of ``meminfo`` as it may be subsequently overwritten by BL2.
On Arm standard platforms, this function also:
@@ -1462,24 +1415,6 @@
configuration of the TrustZone controller to allow non-secure masters access
to most of DRAM. Part of DRAM is reserved for secure world use.
-Function : bl2\_plat\_sec\_mem\_layout() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : void
- Return : meminfo *
-
-This function should only be called on the cold boot path. It may execute with
-the MMU and data caches enabled if the platform port does the necessary
-initialization in ``bl2_plat_arch_setup()``. It is only called by the primary CPU.
-
-The purpose of this function is to return a pointer to a ``meminfo`` structure
-populated with the extents of secure RAM available for BL2 to use. See
-``bl2_early_platform_setup()`` above.
-
-Following functions are optionally used only when LOAD\_IMAGE\_V2 is enabled.
-
Function : bl2\_plat\_handle\_pre\_image\_load() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1490,7 +1425,7 @@
This function can be used by the platforms to update/use image information
for given ``image_id``. This function is currently invoked in BL2 before
-loading each image, when LOAD\_IMAGE\_V2 is enabled.
+loading each image.
Function : bl2\_plat\_handle\_post\_image\_load() [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1502,183 +1437,7 @@
This function can be used by the platforms to update/use image information
for given ``image_id``. This function is currently invoked in BL2 after
-loading each image, when LOAD\_IMAGE\_V2 is enabled.
-
-Following functions are required only when LOAD\_IMAGE\_V2 is disabled.
-
-Function : bl2\_plat\_get\_scp\_bl2\_meminfo() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : meminfo *
- Return : void
-
-This function is used to get the memory limits where BL2 can load the
-SCP\_BL2 image. The meminfo provided by this is used by load\_image() to
-validate whether the SCP\_BL2 image can be loaded within the given
-memory from the given base.
-
-Function : bl2\_plat\_handle\_scp\_bl2() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : image_info *
- Return : int
-
-This function is called after loading SCP\_BL2 image and it is used to perform
-any platform-specific actions required to handle the SCP firmware. Typically it
-transfers the image into SCP memory using a platform-specific protocol and waits
-until SCP executes it and signals to the Application Processor (AP) for BL2
-execution to continue.
-
-This function returns 0 on success, a negative error code otherwise.
-
-Function : bl2\_plat\_get\_bl31\_params() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : void
- Return : bl31_params *
-
-BL2 platform code needs to return a pointer to a ``bl31_params`` structure it
-will use for passing information to BL31. The ``bl31_params`` structure carries
-the following information.
-- Header describing the version information for interpreting the bl31\_param
-structure
-- Information about executing the BL33 image in the ``bl33_ep_info`` field
-- Information about executing the BL32 image in the ``bl32_ep_info`` field
-- Information about the type and extents of BL31 image in the
-``bl31_image_info`` field
-- Information about the type and extents of BL32 image in the
-``bl32_image_info`` field
-- Information about the type and extents of BL33 image in the
-``bl33_image_info`` field
-
-The memory pointed by this structure and its sub-structures should be
-accessible from BL31 initialisation code. BL31 might choose to copy the
-necessary content, or maintain the structures until BL33 is initialised.
-
-Funtion : bl2\_plat\_get\_bl31\_ep\_info() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : void
- Return : entry_point_info *
-
-BL2 platform code returns a pointer which is used to populate the entry point
-information for BL31 entry point. The location pointed by it should be
-accessible from BL1 while processing the synchronous exception to run to BL31.
-
-In Arm standard platforms this is allocated inside a bl2\_to\_bl31\_params\_mem
-structure in BL2 memory.
-
-Function : bl2\_plat\_set\_bl31\_ep\_info() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : image_info *, entry_point_info *
- Return : void
-
-In the normal boot flow, this function is called after loading BL31 image and
-it can be used to overwrite the entry point set by loader and also set the
-security state and SPSR which represents the entry point system state for BL31.
-
-When booting an EL3 payload instead, this function is called after populating
-its entry point address and can be used for the same purpose for the payload
-image. It receives a null pointer as its first argument in this case.
-
-Function : bl2\_plat\_set\_bl32\_ep\_info() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : image_info *, entry_point_info *
- Return : void
-
-This function is called after loading BL32 image and it can be used to
-overwrite the entry point set by loader and also set the security state
-and SPSR which represents the entry point system state for BL32.
-
-Function : bl2\_plat\_set\_bl33\_ep\_info() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : image_info *, entry_point_info *
- Return : void
-
-This function is called after loading BL33 image and it can be used to
-overwrite the entry point set by loader and also set the security state
-and SPSR which represents the entry point system state for BL33.
-
-In the preloaded BL33 alternative boot flow, this function is called after
-populating its entry point address. It is passed a null pointer as its first
-argument in this case.
-
-Function : bl2\_plat\_get\_bl32\_meminfo() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : meminfo *
- Return : void
-
-This function is used to get the memory limits where BL2 can load the
-BL32 image. The meminfo provided by this is used by load\_image() to
-validate whether the BL32 image can be loaded with in the given
-memory from the given base.
-
-Function : bl2\_plat\_get\_bl33\_meminfo() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : meminfo *
- Return : void
-
-This function is used to get the memory limits where BL2 can load the
-BL33 image. The meminfo provided by this is used by load\_image() to
-validate whether the BL33 image can be loaded with in the given
-memory from the given base.
-
-This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE``
-build options are used.
-
-Function : bl2\_plat\_flush\_bl31\_params() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : void
- Return : void
-
-Once BL2 has populated all the structures that needs to be read by BL1
-and BL31 including the bl31\_params structures and its sub-structures,
-the bl31\_ep\_info structure and any platform specific data. It flushes
-all these data to the main memory so that it is available when we jump to
-later Bootloader stages with MMU off
-
-Function : plat\_get\_ns\_image\_entrypoint() [mandatory]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : void
- Return : uintptr_t
-
-As previously described, BL2 is responsible for arranging for control to be
-passed to a normal world BL image through BL31. This function returns the
-entrypoint of that image, which BL31 uses to jump to it.
-
-BL2 is responsible for loading the normal world BL33 image (e.g. UEFI).
-
-This function isn't needed if either ``PRELOADED_BL33_BASE`` or ``EL3_PAYLOAD_BASE``
-build options are used.
+loading each image.
Function : bl2\_plat\_preload\_setup [optional]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1881,8 +1640,8 @@
should make no assumptions about the system state when it receives control.
#. Passing control to a normal world BL image, pre-loaded at a platform-
- specific address by BL2. BL31 uses the ``entry_point_info`` structure that BL2
- populated in memory to do this.
+ specific address by BL2. On ARM platforms, BL31 uses the ``bl_params`` list
+ populated by BL2 in memory to do this.
#. Providing runtime firmware services. Currently, BL31 only implements a
subset of the Power State Coordination Interface (PSCI) API as a runtime
@@ -1892,8 +1651,8 @@
#. Optionally passing control to the BL32 image, pre-loaded at a platform-
specific address by BL2. BL31 exports a set of apis that allow runtime
services to specify the security state in which the next image should be
- executed and run the corresponding image. BL31 uses the ``entry_point_info``
- structure populated by BL2 to do this.
+ executed and run the corresponding image. On ARM platforms, BL31 uses the
+ ``bl_params`` list populated by BL2 in memory to do this.
If BL31 is a reset vector, It also needs to handle the reset as specified in
section 2.2 before the tasks described above.
@@ -1901,28 +1660,32 @@
The following functions must be implemented by the platform port to enable BL31
to perform the above tasks.
-Function : bl31\_early\_platform\_setup() [mandatory]
+Function : bl31\_early\_platform\_setup2() [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
- Argument : bl31_params *, void *
+ Argument : u_register_t, u_register_t, u_register_t, u_register_t
Return : void
This function executes with the MMU and data caches disabled. It is only called
-by the primary CPU. The arguments to this function are:
+by the primary CPU. BL2 can pass 4 arguments to BL31 and these arguments are
+platform specific.
-- The address of the ``bl31_params`` structure populated by BL2.
-- An opaque pointer that the platform may use as needed.
+In Arm standard platforms, the arguments received are :
-The platform can copy the contents of the ``bl31_params`` structure and its
-sub-structures into private variables if the original memory may be
-subsequently overwritten by BL31 and similarly the ``void *`` pointing
-to the platform data also needs to be saved.
+ arg0 - The pointer to the head of `bl_params_t` list
+ which is list of executable images following BL31,
-In Arm standard platforms, BL2 passes a pointer to a ``bl31_params`` structure
-in BL2 memory. BL31 copies the information in this pointer to internal data
-structures. It also performs the following:
+ arg1 - Points to load address of SOC_FW_CONFIG if present
+
+ arg2 - Points to load address of HW_CONFIG if present
+
+ arg3 - A special value to verify platform parameters from BL2 to BL31. Not
+ used in release builds.
+
+The function runs through the `bl_param_t` list and extracts the entry point
+information for BL32 and BL33. It also performs the following:
- Initialize a UART (PL011 console), which enables access to the ``printf``
family of functions in BL31.
@@ -2976,12 +2739,6 @@
Build flags
-----------
-- **ENABLE\_PLAT\_COMPAT**
- All the platforms ports conforming to this API specification should define
- the build flag ``ENABLE_PLAT_COMPAT`` to 0 as the compatibility layer should
- be disabled. For more details on compatibility layer, refer
- `Migration Guide`_.
-
There are some build flags which can be defined by the platform to control
inclusion or exclusion of certain BL stages from the FIP image. These flags
need to be defined in the platform makefile which will get included by the
@@ -3067,7 +2824,6 @@
*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
-.. _Migration Guide: platform-migration-guide.rst
.. _include/plat/common/platform.h: ../include/plat/common/platform.h
.. _include/plat/arm/common/plat\_arm.h: ../include/plat/arm/common/plat_arm.h%5D
.. _User Guide: user-guide.rst
@@ -3082,6 +2838,7 @@
.. _Firmware Design: firmware-design.rst
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
+.. _Platform compatibility policy: ./platform-compatibility-policy.rst
.. _IMF Design Guide: interrupt-framework-design.rst
.. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
.. _3.0 (GICv3): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index 67fe578..2632329 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -234,11 +234,6 @@
compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
*Armv8 Architecture Extensions* in `Firmware Design`_.
-- ``ARM_GIC_ARCH``: Choice of Arm GIC architecture version used by the Arm
- Legacy GIC driver for implementing the platform GIC API. This API is used
- by the interrupt management framework. Default is 2 (that is, version 2.0).
- This build option is deprecated.
-
- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
is set, the functions which deal with MPIDR assume that the ``MT`` bit in
@@ -334,8 +329,8 @@
- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted
Board Boot authentication at runtime. This option is meant to be enabled only
- for development platforms. Both TRUSTED_BOARD_BOOT and LOAD_IMAGE_V2 flags
- must be set if this flag has to be enabled. 0 is the default.
+ for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this
+ flag has to be enabled. 0 is the default.
- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of
the normal boot flow. It must specify the entry point address of the EL3
@@ -396,6 +391,10 @@
The default is 1 but is automatically disabled when the target architecture
is AArch32.
+- ``ENABLE_SPM`` : Boolean option to enable the Secure Partition Manager (SPM).
+ Refer to the `Secure Partition Manager Design guide`_ for more details about
+ this feature. Default is 0.
+
- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
(SVE) for the Non-secure world only. SVE is an optional architectural feature
for AArch64. Note that when SVE is enabled for the Non-secure world, access
@@ -510,12 +509,6 @@
- ``LDFLAGS``: Extra user options appended to the linkers' command line in
addition to the one set by the build system.
-- ``LOAD_IMAGE_V2``: Boolean option to enable support for new version (v2) of
- image loading, which provides more flexibility and scalability around what
- images are loaded and executed during boot. Default is 0.
-
- Note: this flag must be enabled for AArch32 builds.
-
- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log
output compiled into the build. This should be one of the following:
@@ -714,14 +707,6 @@
sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
flag.
-- ``ARM_BOARD_OPTIMISE_MEM``: Boolean option to enable or disable optimisation
- of the memory reserved for each image. This affects the maximum size of each
- BL image as well as the number of allocated memory regions and translation
- tables. By default this flag is 0, which means it uses the default
- unoptimised values for these macros. Arm development platforms that wish to
- optimise memory usage need to set this flag to 1 and must override the
- related macros.
-
- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which should
@@ -840,9 +825,6 @@
- ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
- ``FVP_GICV2`` : The GICv2 only driver is selected
- ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
- - ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
- Note: If TF-A is compiled with this option on FVPs with GICv3 hardware,
- then it configures the hardware to run in GICv2 emulation mode
- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
for functions that wait for an arbitrary time length (udelay and mdelay).
@@ -1081,18 +1063,6 @@
More information about FIP can be found in the `Firmware Design`_ document.
-Migrating from fip\_create to fiptool
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The previous version of fiptool was called fip\_create. A compatibility script
-that emulates the basic functionality of the previous fip\_create is provided.
-However, users are strongly encouraged to migrate to fiptool.
-
-- To create a new FIP file, replace "fip\_create" with "fiptool create".
-- To update a FIP file, replace "fip\_create" with "fiptool update".
-- To dump the contents of a FIP file, replace "fip\_create --dump"
- with "fiptool info".
-
Building FIP images with support for Trusted Board Boot
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -1211,12 +1181,12 @@
make PLAT=<platform> [DEBUG=1] [V=1] certtool
-For platforms that do not require their own IDs in certificate files,
-the generic 'cert\_create' tool can be built with the following command:
+For platforms that require their own IDs in certificate files, the generic
+'cert\_create' tool can be built with the following command:
::
- make USE_TBBR_DEFS=1 [DEBUG=1] [V=1] certtool
+ make USE_TBBR_DEFS=0 [DEBUG=1] [V=1] certtool
``DEBUG=1`` builds the tool in debug mode. ``V=1`` makes the build process more
verbose. The following command should be used to obtain help about the tool:
@@ -1334,7 +1304,7 @@
::
- make ARCH=aarch64 PLAT=juno LOAD_IMAGE_V2=1 JUNO_AARCH32_EL3_RUNTIME=1 \
+ make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
BL33=<path-to-juno32-oe-uboot>/SOFTWARE/bl33-uboot.bin \
SCP_BL2=<path-to-juno32-oe-uboot>/SOFTWARE/scp_bl2.bin \
BL32=<path-to-bl32>/bl32.bin all fip
@@ -2076,7 +2046,7 @@
.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
-.. _Linux master tree: <https://github.com/torvalds/linux/tree/master/>
+.. _Linux master tree: https://github.com/torvalds/linux/tree/master/
.. _Dia: https://wiki.gnome.org/Apps/Dia/Download
.. _here: psci-lib-integration-guide.rst
.. _Trusted Board Boot: trusted-board-boot.rst
@@ -2090,3 +2060,4 @@
.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
+.. _Secure Partition Manager Design guide: secure-partition-manager-design.rst
diff --git a/drivers/arm/cci400/cci400.c b/drivers/arm/cci400/cci400.c
deleted file mode 100644
index 402e5e1..0000000
--- a/drivers/arm/cci400/cci400.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <assert.h>
-#include <cci400.h>
-#include <debug.h>
-#include <mmio.h>
-#include <stdint.h>
-
-#define MAX_CLUSTERS 2
-
-static uintptr_t cci_base_addr;
-static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS];
-
-
-void cci_init(uintptr_t cci_base,
- int slave_iface3_cluster_ix,
- int slave_iface4_cluster_ix)
-{
- /*
- * Check the passed arguments are valid. The cluster indices must be
- * less than MAX_CLUSTERS, not the same as each other and at least one
- * of them must refer to a valid cluster index.
- */
- assert(cci_base);
- assert(slave_iface3_cluster_ix < MAX_CLUSTERS);
- assert(slave_iface4_cluster_ix < MAX_CLUSTERS);
- assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix);
- assert((slave_iface3_cluster_ix >= 0) ||
- (slave_iface4_cluster_ix >= 0));
-
- WARN("Please migrate to common cci driver, This driver will be" \
- " deprecated in future\n");
-
- cci_base_addr = cci_base;
- if (slave_iface3_cluster_ix >= 0)
- cci_cluster_ix_to_iface[slave_iface3_cluster_ix] =
- SLAVE_IFACE3_OFFSET;
- if (slave_iface4_cluster_ix >= 0)
- cci_cluster_ix_to_iface[slave_iface4_cluster_ix] =
- SLAVE_IFACE4_OFFSET;
-}
-
-static inline unsigned long get_slave_iface_base(unsigned long mpidr)
-{
- /*
- * We assume the TF topology code allocates affinity instances
- * consecutively from zero.
- * It is a programming error if this is called without initializing
- * the slave interface to use for this cluster.
- */
- unsigned int cluster_id =
- (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
-
- assert(cluster_id < MAX_CLUSTERS);
- assert(cci_cluster_ix_to_iface[cluster_id] != 0);
-
- return cci_base_addr + cci_cluster_ix_to_iface[cluster_id];
-}
-
-void cci_enable_cluster_coherency(unsigned long mpidr)
-{
- assert(cci_base_addr);
- /* Enable Snoops and DVM messages */
- mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
- DVM_EN_BIT | SNOOP_EN_BIT);
-
- /* Wait for the dust to settle down */
- while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
- ;
-}
-
-void cci_disable_cluster_coherency(unsigned long mpidr)
-{
- assert(cci_base_addr);
- /* Disable Snoops and DVM messages */
- mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG,
- ~(DVM_EN_BIT | SNOOP_EN_BIT));
-
- /* Wait for the dust to settle down */
- while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT)
- ;
-}
-
diff --git a/drivers/arm/gic/arm_gic.c b/drivers/arm/gic/arm_gic.c
deleted file mode 100644
index e040e0a..0000000
--- a/drivers/arm/gic/arm_gic.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <arm_gic.h>
-#include <assert.h>
-#include <bl_common.h>
-#include <debug.h>
-#include <gic_v2.h>
-#include <gic_v3.h>
-#include <interrupt_mgmt.h>
-#include <platform.h>
-#include <stdint.h>
-
-/* Value used to initialize Non-Secure IRQ priorities four at a time */
-#define GICD_IPRIORITYR_DEF_VAL \
- (GIC_HIGHEST_NS_PRIORITY | \
- (GIC_HIGHEST_NS_PRIORITY << 8) | \
- (GIC_HIGHEST_NS_PRIORITY << 16) | \
- (GIC_HIGHEST_NS_PRIORITY << 24))
-
-static uintptr_t g_gicc_base;
-static uintptr_t g_gicd_base;
-static uintptr_t g_gicr_base;
-static const unsigned int *g_irq_sec_ptr;
-static unsigned int g_num_irqs;
-
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration. The Firmware itself does
- * not fully support GICv3 at this time and relies on GICv2 emulation as
- * provided by GICv3. This function allows software (like Linux) in later stages
- * to use full GICv3 features.
- ******************************************************************************/
-static void gicv3_cpuif_setup(void)
-{
- unsigned int val;
- uintptr_t base;
-
- /*
- * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
- * bit set. In order to allow interrupts to get routed to the CPU we
- * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
- * to clear (GICv3 Architecture specification 5.4.23).
- * GICR_WAKER is NOT banked per CPU, compute the correct base address
- * per CPU.
- */
- assert(g_gicr_base);
- base = gicv3_get_rdist(g_gicr_base, read_mpidr());
- if (base == (uintptr_t)NULL) {
- /* No re-distributor base address. This interface cannot be
- * configured.
- */
- panic();
- }
-
- val = gicr_read_waker(base);
-
- val &= ~WAKER_PS;
- gicr_write_waker(base, val);
- dsb();
-
- /* We need to wait for ChildrenAsleep to clear. */
- val = gicr_read_waker(base);
- while (val & WAKER_CA)
- val = gicr_read_waker(base);
-
- val = read_icc_sre_el3();
- write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
- isb();
-}
-
-/*******************************************************************************
- * This function does some minimal GICv3 configuration when cores go
- * down.
- ******************************************************************************/
-static void gicv3_cpuif_deactivate(void)
-{
- unsigned int val;
- uintptr_t base;
-
- /*
- * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
- * wait for GICR_WAKER.ChildrenAsleep to get set.
- * (GICv3 Architecture specification 5.4.23).
- * GICR_WAKER is NOT banked per CPU, compute the correct base address
- * per CPU.
- */
- assert(g_gicr_base);
- base = gicv3_get_rdist(g_gicr_base, read_mpidr());
- if (base == (uintptr_t)NULL) {
- /* No re-distributor base address. This interface cannot be
- * configured.
- */
- panic();
- }
-
- val = gicr_read_waker(base);
- val |= WAKER_PS;
- gicr_write_waker(base, val);
- dsb();
-
- /* We need to wait for ChildrenAsleep to set. */
- val = gicr_read_waker(base);
- while ((val & WAKER_CA) == 0)
- val = gicr_read_waker(base);
-}
-
-
-/*******************************************************************************
- * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
- * and set the priority mask register to allow all interrupts to trickle in.
- ******************************************************************************/
-void arm_gic_cpuif_setup(void)
-{
- unsigned int val;
-
- assert(g_gicc_base);
- val = gicc_read_iidr(g_gicc_base);
-
- /*
- * If GICv3 we need to do a bit of additional setup. We want to
- * allow default GICv2 behaviour but allow the next stage to
- * enable full gicv3 features.
- */
- if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
- gicv3_cpuif_setup();
-
- val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
- val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
-
- gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
- gicc_write_ctlr(g_gicc_base, val);
-}
-
-/*******************************************************************************
- * Place the cpu interface in a state where it can never make a cpu exit wfi as
- * as result of an asserted interrupt. This is critical for powering down a cpu
- ******************************************************************************/
-void arm_gic_cpuif_deactivate(void)
-{
- unsigned int val;
-
- /* Disable secure, non-secure interrupts and disable their bypass */
- assert(g_gicc_base);
- val = gicc_read_ctlr(g_gicc_base);
- val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
- val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
- val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
- gicc_write_ctlr(g_gicc_base, val);
-
- val = gicc_read_iidr(g_gicc_base);
-
- /*
- * If GICv3 we need to do a bit of additional setup. Make sure the
- * RDIST is put to sleep.
- */
- if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
- gicv3_cpuif_deactivate();
-}
-
-/*******************************************************************************
- * Per cpu gic distributor setup which will be done by all cpus after a cold
- * boot/hotplug. This marks out the secure interrupts & enables them.
- ******************************************************************************/
-void arm_gic_pcpu_distif_setup(void)
-{
- unsigned int index, irq_num, sec_ppi_sgi_mask;
-
- assert(g_gicd_base);
-
- /* Setup PPI priorities doing four at a time */
- for (index = 0; index < 32; index += 4) {
- gicd_write_ipriorityr(g_gicd_base, index,
- GICD_IPRIORITYR_DEF_VAL);
- }
-
- assert(g_irq_sec_ptr);
- sec_ppi_sgi_mask = 0;
-
- /* Ensure all SGIs and PPIs are Group0 to begin with */
- gicd_write_igroupr(g_gicd_base, 0, 0);
-
- for (index = 0; index < g_num_irqs; index++) {
- irq_num = g_irq_sec_ptr[index];
- if (irq_num < MIN_SPI_ID) {
- /* We have an SGI or a PPI */
- sec_ppi_sgi_mask |= 1U << irq_num;
- gicd_set_ipriorityr(g_gicd_base, irq_num,
- GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_isenabler(g_gicd_base, irq_num);
- }
- }
-
- /*
- * Invert the bitmask to create a mask for non-secure PPIs and
- * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
- * update the GICR_IGROUPR0 as well in case we are running on a GICv3
- * system. This is critical if GICD_CTLR.ARE_NS=1.
- */
- gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
-}
-
-/*******************************************************************************
- * Get the current CPU bit mask from GICD_ITARGETSR0
- ******************************************************************************/
-static unsigned int arm_gic_get_cpuif_id(void)
-{
- unsigned int val;
-
- val = gicd_read_itargetsr(g_gicd_base, 0);
- return val & GIC_TARGET_CPU_MASK;
-}
-
-/*******************************************************************************
- * Global gic distributor setup which will be done by the primary cpu after a
- * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
- * then enables the secure GIC distributor interface.
- ******************************************************************************/
-static void arm_gic_distif_setup(void)
-{
- unsigned int num_ints, ctlr, index, irq_num;
- uint8_t target_cpu;
-
- /* Disable the distributor before going further */
- assert(g_gicd_base);
- ctlr = gicd_read_ctlr(g_gicd_base);
- ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
- gicd_write_ctlr(g_gicd_base, ctlr);
-
- /*
- * Mark out non-secure SPI interrupts. The number of interrupts is
- * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
- */
- num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
- num_ints = (num_ints + 1) << 5;
- for (index = MIN_SPI_ID; index < num_ints; index += 32)
- gicd_write_igroupr(g_gicd_base, index, ~0);
-
- /* Setup SPI priorities doing four at a time */
- for (index = MIN_SPI_ID; index < num_ints; index += 4) {
- gicd_write_ipriorityr(g_gicd_base, index,
- GICD_IPRIORITYR_DEF_VAL);
- }
-
- /* Read the target CPU mask */
- target_cpu = arm_gic_get_cpuif_id();
-
- /* Configure SPI secure interrupts now */
- assert(g_irq_sec_ptr);
- for (index = 0; index < g_num_irqs; index++) {
- irq_num = g_irq_sec_ptr[index];
- if (irq_num >= MIN_SPI_ID) {
- /* We have an SPI */
- gicd_clr_igroupr(g_gicd_base, irq_num);
- gicd_set_ipriorityr(g_gicd_base, irq_num,
- GIC_HIGHEST_SEC_PRIORITY);
- gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
- gicd_set_isenabler(g_gicd_base, irq_num);
- }
- }
-
- /*
- * Configure the SGI and PPI. This is done in a separated function
- * because each CPU is responsible for initializing its own private
- * interrupts.
- */
- arm_gic_pcpu_distif_setup();
-
- gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
-}
-
-/*******************************************************************************
- * Initialize the ARM GIC driver with the provided platform inputs
-******************************************************************************/
-void arm_gic_init(uintptr_t gicc_base,
- uintptr_t gicd_base,
- uintptr_t gicr_base,
- const unsigned int *irq_sec_ptr,
- unsigned int num_irqs)
-{
- unsigned int val;
-
- assert(gicc_base);
- assert(gicd_base);
- assert(irq_sec_ptr);
-
- g_gicc_base = gicc_base;
- g_gicd_base = gicd_base;
-
- val = gicc_read_iidr(g_gicc_base);
-
- if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
- assert(gicr_base);
- g_gicr_base = gicr_base;
- }
-
- g_irq_sec_ptr = irq_sec_ptr;
- g_num_irqs = num_irqs;
-}
-
-/*******************************************************************************
- * Setup the ARM GIC CPU and distributor interfaces.
-******************************************************************************/
-void arm_gic_setup(void)
-{
- arm_gic_cpuif_setup();
- arm_gic_distif_setup();
-}
-
-/*******************************************************************************
- * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
- * The interrupt controller knows which pin/line it uses to signal a type of
- * interrupt. This function provides a common implementation of
- * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
- * across platforms. It lets the interrupt management framework determine
- * for a type of interrupt and security state, which line should be used in the
- * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
- * the bit position of the IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
- uint32_t security_state)
-{
- assert(type == INTR_TYPE_S_EL1 ||
- type == INTR_TYPE_EL3 ||
- type == INTR_TYPE_NS);
-
- assert(sec_state_is_valid(security_state));
-
- /*
- * We ignore the security state parameter under the assumption that
- * both normal and secure worlds are using ARM GICv2. This parameter
- * will be used when the secure world starts using GICv3.
- */
-#if ARM_GIC_ARCH == 2
- return gicv2_interrupt_type_to_line(g_gicc_base, type);
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
-}
-
-#if ARM_GIC_ARCH == 2
-/*******************************************************************************
- * This function returns the type of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t arm_gic_get_pending_interrupt_type(void)
-{
- uint32_t id;
-
- assert(g_gicc_base);
- id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
-
- /* Assume that all secure interrupts are S-EL1 interrupts */
- if (id < 1022)
- return INTR_TYPE_S_EL1;
-
- if (id == GIC_SPURIOUS_INTERRUPT)
- return INTR_TYPE_INVAL;
-
- return INTR_TYPE_NS;
-}
-
-/*******************************************************************************
- * This function returns the id of the highest priority pending interrupt at
- * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
- * interrupt pending.
- ******************************************************************************/
-uint32_t arm_gic_get_pending_interrupt_id(void)
-{
- uint32_t id;
-
- assert(g_gicc_base);
- id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
-
- if (id < 1022)
- return id;
-
- if (id == 1023)
- return INTR_ID_UNAVAILABLE;
-
- /*
- * Find out which non-secure interrupt it is under the assumption that
- * the GICC_CTLR.AckCtl bit is 0.
- */
- return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK;
-}
-
-/*******************************************************************************
- * This functions reads the GIC cpu interface Interrupt Acknowledge register
- * to start handling the pending interrupt. It returns the contents of the IAR.
- ******************************************************************************/
-uint32_t arm_gic_acknowledge_interrupt(void)
-{
- assert(g_gicc_base);
- return gicc_read_IAR(g_gicc_base);
-}
-
-/*******************************************************************************
- * This functions writes the GIC cpu interface End Of Interrupt register with
- * the passed value to finish handling the active interrupt
- ******************************************************************************/
-void arm_gic_end_of_interrupt(uint32_t id)
-{
- assert(g_gicc_base);
- gicc_write_EOIR(g_gicc_base, id);
-}
-
-/*******************************************************************************
- * This function returns the type of the interrupt id depending upon the group
- * this interrupt has been configured under by the interrupt controller i.e.
- * group0 or group1.
- ******************************************************************************/
-uint32_t arm_gic_get_interrupt_type(uint32_t id)
-{
- uint32_t group;
-
- assert(g_gicd_base);
- group = gicd_get_igroupr(g_gicd_base, id);
-
- /* Assume that all secure interrupts are S-EL1 interrupts */
- if (group == GRP0)
- return INTR_TYPE_S_EL1;
- else
- return INTR_TYPE_NS;
-}
-
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
diff --git a/drivers/arm/gic/gic_v2.c b/drivers/arm/gic/gic_v2.c
deleted file mode 100644
index 29c79e0..0000000
--- a/drivers/arm/gic/gic_v2.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <assert.h>
-#include <gic_v2.h>
-#include <interrupt_mgmt.h>
-#include <mmio.h>
-
-/*******************************************************************************
- * GIC Distributor interface accessors for reading entire registers
- ******************************************************************************/
-
-unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> IGROUPR_SHIFT;
- return mmio_read_32(base + GICD_IGROUPR + (n << 2));
-}
-
-unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ISENABLER_SHIFT;
- return mmio_read_32(base + GICD_ISENABLER + (n << 2));
-}
-
-unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ICENABLER_SHIFT;
- return mmio_read_32(base + GICD_ICENABLER + (n << 2));
-}
-
-unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ISPENDR_SHIFT;
- return mmio_read_32(base + GICD_ISPENDR + (n << 2));
-}
-
-unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ICPENDR_SHIFT;
- return mmio_read_32(base + GICD_ICPENDR + (n << 2));
-}
-
-unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ISACTIVER_SHIFT;
- return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
-}
-
-unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ICACTIVER_SHIFT;
- return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
-}
-
-unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> IPRIORITYR_SHIFT;
- return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
-}
-
-unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ITARGETSR_SHIFT;
- return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
-}
-
-unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> ICFGR_SHIFT;
- return mmio_read_32(base + GICD_ICFGR + (n << 2));
-}
-
-unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> CPENDSGIR_SHIFT;
- return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
-}
-
-unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id)
-{
- unsigned n = id >> SPENDSGIR_SHIFT;
- return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
-}
-
-/*******************************************************************************
- * GIC Distributor interface accessors for writing entire registers
- ******************************************************************************/
-
-void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> IGROUPR_SHIFT;
- mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
-}
-
-void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ISENABLER_SHIFT;
- mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
-}
-
-void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ICENABLER_SHIFT;
- mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
-}
-
-void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ISPENDR_SHIFT;
- mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
-}
-
-void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ICPENDR_SHIFT;
- mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
-}
-
-void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ISACTIVER_SHIFT;
- mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
-}
-
-void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ICACTIVER_SHIFT;
- mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
-}
-
-void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> IPRIORITYR_SHIFT;
- mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
-}
-
-void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ITARGETSR_SHIFT;
- mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
-}
-
-void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> ICFGR_SHIFT;
- mmio_write_32(base + GICD_ICFGR + (n << 2), val);
-}
-
-void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> CPENDSGIR_SHIFT;
- mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
-}
-
-void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val)
-{
- unsigned n = id >> SPENDSGIR_SHIFT;
- mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
-}
-
-/*******************************************************************************
- * GIC Distributor interface accessors for individual interrupt manipulation
- ******************************************************************************/
-unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
- unsigned int reg_val = gicd_read_igroupr(base, id);
-
- return (reg_val >> bit_num) & 0x1;
-}
-
-void gicd_set_igroupr(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
- unsigned int reg_val = gicd_read_igroupr(base, id);
-
- gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
-}
-
-void gicd_clr_igroupr(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
- unsigned int reg_val = gicd_read_igroupr(base, id);
-
- gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
-}
-
-void gicd_set_isenabler(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
-
- gicd_write_isenabler(base, id, (1 << bit_num));
-}
-
-void gicd_set_icenabler(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
-
- gicd_write_icenabler(base, id, (1 << bit_num));
-}
-
-void gicd_set_ispendr(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
-
- gicd_write_ispendr(base, id, (1 << bit_num));
-}
-
-void gicd_set_icpendr(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
-
- gicd_write_icpendr(base, id, (1 << bit_num));
-}
-
-void gicd_set_isactiver(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
-
- gicd_write_isactiver(base, id, (1 << bit_num));
-}
-
-void gicd_set_icactiver(uintptr_t base, unsigned int id)
-{
- unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
-
- gicd_write_icactiver(base, id, (1 << bit_num));
-}
-
-/*
- * Make sure that the interrupt's group is set before expecting
- * this function to do its job correctly.
- */
-void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
-{
- /*
- * Enforce ARM recommendation to manage priority values such
- * that group1 interrupts always have a lower priority than
- * group0 interrupts.
- * Note, lower numerical values are higher priorities so the comparison
- * checks below are reversed from what might be expected.
- */
- assert(gicd_get_igroupr(base, id) == GRP1 ?
- pri >= GIC_HIGHEST_NS_PRIORITY &&
- pri <= GIC_LOWEST_NS_PRIORITY :
- pri >= GIC_HIGHEST_SEC_PRIORITY &&
- pri <= GIC_LOWEST_SEC_PRIORITY);
-
- mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK);
-}
-
-void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target)
-{
- mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
-}
-
-/*******************************************************************************
- * This function allows the interrupt management framework to determine (through
- * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to
- * route it to EL3. The interrupt line is represented as the bit position of the
- * IRQ or FIQ bit in the SCR_EL3.
- ******************************************************************************/
-uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type)
-{
- uint32_t gicc_ctlr;
-
- /* Non-secure interrupts are signalled on the IRQ line always */
- if (type == INTR_TYPE_NS)
- return __builtin_ctz(SCR_IRQ_BIT);
-
- /*
- * Secure interrupts are signalled using the IRQ line if the FIQ_EN
- * bit is not set else they are signalled using the FIQ line.
- */
- gicc_ctlr = gicc_read_ctlr(cpuif_base);
- if (gicc_ctlr & FIQ_EN)
- return __builtin_ctz(SCR_FIQ_BIT);
- else
- return __builtin_ctz(SCR_IRQ_BIT);
-}
diff --git a/drivers/arm/gic/gic_v3.c b/drivers/arm/gic/gic_v3.c
deleted file mode 100644
index 5486817..0000000
--- a/drivers/arm/gic/gic_v3.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <debug.h>
-#include <gic_v3.h>
-
-uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr)
-{
- uint32_t cpu_aff, gicr_aff;
- uint64_t gicr_typer;
- uintptr_t addr;
-
- /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
- * mask is the same.
- */
- cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
- GICV3_AFF0_SHIFT;
- cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
- GICV3_AFF1_SHIFT;
- cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
- GICV3_AFF2_SHIFT;
- cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
- GICV3_AFF3_SHIFT;
-
- addr = gicr_base;
- do {
- gicr_typer = gicr_read_typer(addr);
-
- gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
- GICR_TYPER_AFF_MASK;
- if (cpu_aff == gicr_aff) {
- /* Disable this print for now as it appears every time
- * when using PSCI CPU_SUSPEND.
- * TODO: Print this only the first time for each CPU.
- * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n",
- * mpidr, (void *) addr);
- */
- return addr;
- }
-
- /* TODO:
- * For GICv4 we need to adjust the Base address based on
- * GICR_TYPER.VLPIS
- */
- addr += (1 << GICR_PCPUBASE_SHIFT);
-
- } while (!(gicr_typer & GICR_TYPER_LAST));
-
- /* If we get here we did not find a match. */
- ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
- return (uintptr_t)NULL;
-}
diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c
index 221f1b5..bc4c1d1 100644
--- a/drivers/arm/gic/v2/gicv2_helpers.c
+++ b/drivers/arm/gic/v2/gicv2_helpers.c
@@ -114,43 +114,6 @@
gicd_write_icfgr(gicd_base, index, 0U);
}
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 SPIs.
- ******************************************************************************/
-void gicv2_secure_spis_configure(uintptr_t gicd_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list)
-{
- unsigned int index, irq_num;
-
- /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- if (num_ints != 0U)
- assert(sec_intr_list != NULL);
-
- for (index = 0; index < num_ints; index++) {
- irq_num = sec_intr_list[index];
- if (irq_num >= MIN_SPI_ID) {
- /* Configure this interrupt as a secure interrupt */
- gicd_clr_igroupr(gicd_base, irq_num);
-
- /* Set the priority of this interrupt */
- gicd_set_ipriorityr(gicd_base,
- irq_num,
- GIC_HIGHEST_SEC_PRIORITY);
-
- /* Target the secure interrupts to primary CPU */
- gicd_set_itargetsr(gicd_base, irq_num,
- gicv2_get_cpuif_id(gicd_base));
-
- /* Enable this interrupt */
- gicd_set_isenabler(gicd_base, irq_num);
- }
- }
-
-}
-#endif
-
/*******************************************************************************
* Helper function to configure properties of secure G0 SPIs.
******************************************************************************/
@@ -191,56 +154,6 @@
gicd_set_isenabler(gicd_base, prop_desc->intr_num);
}
}
-
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 SGIs and PPIs.
- ******************************************************************************/
-void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list)
-{
- unsigned int index, irq_num, sec_ppi_sgi_mask = 0;
-
- /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- assert(num_ints ? (uintptr_t)sec_intr_list : 1);
-
- /*
- * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
- * more scalable approach as it avoids clearing the enable bits in the
- * GICD_CTLR.
- */
- gicd_write_icenabler(gicd_base, 0, ~0);
-
- /* Setup the default PPI/SGI priorities doing four at a time */
- for (index = 0; index < MIN_SPI_ID; index += 4)
- gicd_write_ipriorityr(gicd_base,
- index,
- GICD_IPRIORITYR_DEF_VAL);
-
- for (index = 0; index < num_ints; index++) {
- irq_num = sec_intr_list[index];
- if (irq_num < MIN_SPI_ID) {
- /* We have an SGI or a PPI. They are Group0 at reset */
- sec_ppi_sgi_mask |= 1U << irq_num;
-
- /* Set the priority of this interrupt */
- gicd_set_ipriorityr(gicd_base,
- irq_num,
- GIC_HIGHEST_SEC_PRIORITY);
- }
- }
-
- /*
- * Invert the bitmask to create a mask for non-secure PPIs and
- * SGIs. Program the GICD_IGROUPR0 with this bit mask.
- */
- gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
-
- /* Enable the Group 0 SGIs and PPIs */
- gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask);
-}
-#endif
/*******************************************************************************
* Helper function to configure properties of secure G0 SGIs and PPIs.
diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c
index 55897bf..b872905 100644
--- a/drivers/arm/gic/v2/gicv2_main.c
+++ b/drivers/arm/gic/v2/gicv2_main.c
@@ -79,27 +79,9 @@
assert(driver_data != NULL);
assert(driver_data->gicd_base != 0U);
-#if !ERROR_DEPRECATED
- if (driver_data->interrupt_props != NULL) {
-#endif
- gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
- driver_data->interrupt_props,
- driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
- } else {
- /*
- * Suppress deprecated declaration warnings in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- assert(driver_data->g0_interrupt_array);
- gicv2_secure_ppi_sgi_setup(driver_data->gicd_base,
- driver_data->g0_interrupt_num,
- driver_data->g0_interrupt_array);
-#pragma GCC diagnostic pop
- }
-#endif
+ gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
+ driver_data->interrupt_props,
+ driver_data->interrupt_props_num);
/* Enable G0 interrupts if not already */
ctlr = gicd_read_ctlr(driver_data->gicd_base);
@@ -129,30 +111,10 @@
/* Set the default attribute of all SPIs */
gicv2_spis_configure_defaults(driver_data->gicd_base);
-#if !ERROR_DEPRECATED
- if (driver_data->interrupt_props != NULL) {
-#endif
- gicv2_secure_spis_configure_props(driver_data->gicd_base,
- driver_data->interrupt_props,
- driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
- } else {
- /*
- * Suppress deprecated declaration warnings in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
- assert(driver_data->g0_interrupt_array);
+ gicv2_secure_spis_configure_props(driver_data->gicd_base,
+ driver_data->interrupt_props,
+ driver_data->interrupt_props_num);
- /* Configure the G0 SPIs */
- gicv2_secure_spis_configure(driver_data->gicd_base,
- driver_data->g0_interrupt_num,
- driver_data->g0_interrupt_array);
-#pragma GCC diagnostic pop
- }
-#endif
/* Re-enable the secure SPIs now that they have been configured */
gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT);
@@ -169,35 +131,8 @@
assert(plat_driver_data->gicd_base != 0U);
assert(plat_driver_data->gicc_base != 0U);
-#if !ERROR_DEPRECATED
- if (plat_driver_data->interrupt_props == NULL) {
- /* Interrupt properties array size must be 0 */
- assert(plat_driver_data->interrupt_props_num == 0);
-
- /*
- * Suppress deprecated declaration warnings in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
- /*
- * If there are no interrupts of a particular type, then the
- * number of interrupts of that type should be 0 and vice-versa.
- */
- assert(plat_driver_data->g0_interrupt_array ?
- plat_driver_data->g0_interrupt_num :
- plat_driver_data->g0_interrupt_num == 0);
-#pragma GCC diagnostic pop
-
- WARN("Using deprecated integer interrupt array in "
- "gicv2_driver_data_t\n");
- WARN("Please migrate to using an interrupt_prop_t array\n");
- }
-#else
assert(plat_driver_data->interrupt_props_num > 0 ?
plat_driver_data->interrupt_props != NULL : 1);
-#endif
/* Ensure that this is a GICv2 system */
gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
diff --git a/drivers/arm/gic/v2/gicv2_private.h b/drivers/arm/gic/v2/gicv2_private.h
index fadc960..1eb6d9d 100644
--- a/drivers/arm/gic/v2/gicv2_private.h
+++ b/drivers/arm/gic/v2/gicv2_private.h
@@ -15,14 +15,6 @@
* Private function prototypes
******************************************************************************/
void gicv2_spis_configure_defaults(uintptr_t gicd_base);
-#if !ERROR_DEPRECATED
-void gicv2_secure_spis_configure(uintptr_t gicd_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list);
-void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list);
-#endif
void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num);
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index 1953a37..c12a4b6 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -377,56 +377,6 @@
gicd_write_icfgr(gicd_base, index, 0U);
}
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 and G1S SPIs.
- ******************************************************************************/
-void gicv3_secure_spis_config(uintptr_t gicd_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list,
- unsigned int int_grp)
-{
- unsigned int index, irq_num;
- unsigned long long gic_affinity_val;
-
- assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
- /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- if (num_ints != 0U)
- assert(sec_intr_list != NULL);
-
- for (index = 0U; index < num_ints; index++) {
- irq_num = sec_intr_list[index];
- if (irq_num >= MIN_SPI_ID) {
-
- /* Configure this interrupt as a secure interrupt */
- gicd_clr_igroupr(gicd_base, irq_num);
-
- /* Configure this interrupt as G0 or a G1S interrupt */
- if (int_grp == INTR_GROUP1S)
- gicd_set_igrpmodr(gicd_base, irq_num);
- else
- gicd_clr_igrpmodr(gicd_base, irq_num);
-
- /* Set the priority of this interrupt */
- gicd_set_ipriorityr(gicd_base,
- irq_num,
- GIC_HIGHEST_SEC_PRIORITY);
-
- /* Target SPIs to the primary CPU */
- gic_affinity_val =
- gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
- gicd_write_irouter(gicd_base,
- irq_num,
- gic_affinity_val);
-
- /* Enable this interrupt */
- gicd_set_isenabler(gicd_base, irq_num);
- }
- }
-
-}
-#endif
-
/*******************************************************************************
* Helper function to configure properties of secure SPIs
******************************************************************************/
@@ -511,47 +461,6 @@
/* Configure all PPIs as level triggered by default */
gicr_write_icfgr1(gicr_base, 0U);
}
-
-#if !ERROR_DEPRECATED
-/*******************************************************************************
- * Helper function to configure secure G0 and G1S SPIs.
- ******************************************************************************/
-void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list,
- unsigned int int_grp)
-{
- unsigned int index, irq_num;
-
- assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
- /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
- if (num_ints != 0U)
- assert(sec_intr_list != NULL);
-
- for (index = 0; index < num_ints; index++) {
- irq_num = sec_intr_list[index];
- if (irq_num < MIN_SPI_ID) {
-
- /* Configure this interrupt as a secure interrupt */
- gicr_clr_igroupr0(gicr_base, irq_num);
-
- /* Configure this interrupt as G0 or a G1S interrupt */
- if (int_grp == INTR_GROUP1S)
- gicr_set_igrpmodr0(gicr_base, irq_num);
- else
- gicr_clr_igrpmodr0(gicr_base, irq_num);
-
- /* Set the priority of this interrupt */
- gicr_set_ipriorityr(gicr_base,
- irq_num,
- GIC_HIGHEST_SEC_PRIORITY);
-
- /* Enable this interrupt */
- gicr_set_isenabler0(gicr_base, irq_num);
- }
- }
-}
-#endif
/*******************************************************************************
* Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 8da4512..5af7e40 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -67,45 +67,8 @@
assert(IS_IN_EL3());
-#if !ERROR_DEPRECATED
- if (plat_driver_data->interrupt_props == NULL) {
- /* Interrupt properties array size must be 0 */
- assert(plat_driver_data->interrupt_props_num == 0);
-
- /*
- * Suppress deprecated declaration warnings in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
- /*
- * The platform should provide a list of at least one type of
- * interrupt.
- */
- assert(plat_driver_data->g0_interrupt_array ||
- plat_driver_data->g1s_interrupt_array);
-
- /*
- * If there are no interrupts of a particular type, then the
- * number of interrupts of that type should be 0 and vice-versa.
- */
- assert(plat_driver_data->g0_interrupt_array ?
- plat_driver_data->g0_interrupt_num :
- plat_driver_data->g0_interrupt_num == 0);
- assert(plat_driver_data->g1s_interrupt_array ?
- plat_driver_data->g1s_interrupt_num :
- plat_driver_data->g1s_interrupt_num == 0);
-#pragma GCC diagnostic pop
-
- WARN("Using deprecated integer interrupt arrays in "
- "gicv3_driver_data_t\n");
- WARN("Please migrate to using interrupt_prop_t arrays\n");
- }
-#else
assert(plat_driver_data->interrupt_props_num > 0 ?
plat_driver_data->interrupt_props != NULL : 1);
-#endif
/* Check for system register support */
#ifdef AARCH32
@@ -193,45 +156,10 @@
/* Set the default attribute of all SPIs */
gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
-#if !ERROR_DEPRECATED
- if (gicv3_driver_data->interrupt_props != NULL) {
-#endif
- bitmap = gicv3_secure_spis_config_props(
- gicv3_driver_data->gicd_base,
- gicv3_driver_data->interrupt_props,
- gicv3_driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
- } else {
- /*
- * Suppress deprecated declaration warnings in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
- assert(gicv3_driver_data->g1s_interrupt_array ||
- gicv3_driver_data->g0_interrupt_array);
-
- /* Configure the G1S SPIs */
- if (gicv3_driver_data->g1s_interrupt_array) {
- gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
- gicv3_driver_data->g1s_interrupt_num,
- gicv3_driver_data->g1s_interrupt_array,
- INTR_GROUP1S);
- bitmap |= CTLR_ENABLE_G1S_BIT;
- }
-
- /* Configure the G0 SPIs */
- if (gicv3_driver_data->g0_interrupt_array) {
- gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
- gicv3_driver_data->g0_interrupt_num,
- gicv3_driver_data->g0_interrupt_array,
- INTR_GROUP0);
- bitmap |= CTLR_ENABLE_G0_BIT;
- }
-#pragma GCC diagnostic pop
- }
-#endif
+ bitmap = gicv3_secure_spis_config_props(
+ gicv3_driver_data->gicd_base,
+ gicv3_driver_data->interrupt_props,
+ gicv3_driver_data->interrupt_props_num);
/* Enable the secure SPIs now that they have been configured */
gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
@@ -266,44 +194,9 @@
/* Set the default attribute of all SGIs and PPIs */
gicv3_ppi_sgi_config_defaults(gicr_base);
-#if !ERROR_DEPRECATED
- if (gicv3_driver_data->interrupt_props != NULL) {
-#endif
- bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
- gicv3_driver_data->interrupt_props,
- gicv3_driver_data->interrupt_props_num);
-#if !ERROR_DEPRECATED
- } else {
- /*
- * Suppress deprecated declaration warnings in compatibility
- * function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
-
- assert(gicv3_driver_data->g1s_interrupt_array ||
- gicv3_driver_data->g0_interrupt_array);
-
- /* Configure the G1S SGIs/PPIs */
- if (gicv3_driver_data->g1s_interrupt_array) {
- gicv3_secure_ppi_sgi_config(gicr_base,
- gicv3_driver_data->g1s_interrupt_num,
- gicv3_driver_data->g1s_interrupt_array,
- INTR_GROUP1S);
- bitmap |= CTLR_ENABLE_G1S_BIT;
- }
-
- /* Configure the G0 SGIs/PPIs */
- if (gicv3_driver_data->g0_interrupt_array) {
- gicv3_secure_ppi_sgi_config(gicr_base,
- gicv3_driver_data->g0_interrupt_num,
- gicv3_driver_data->g0_interrupt_array,
- INTR_GROUP0);
- bitmap |= CTLR_ENABLE_G0_BIT;
- }
-#pragma GCC diagnostic pop
- }
-#endif
+ bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
+ gicv3_driver_data->interrupt_props,
+ gicv3_driver_data->interrupt_props_num);
/* Enable interrupt groups as required, if not already */
if ((ctlr & bitmap) != bitmap)
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index 36d4b3e..85231ad 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -95,16 +95,6 @@
******************************************************************************/
void gicv3_spis_config_defaults(uintptr_t gicd_base);
void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
-#if !ERROR_DEPRECATED
-void gicv3_secure_spis_config(uintptr_t gicd_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list,
- unsigned int int_grp);
-void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
- unsigned int num_ints,
- const unsigned int *sec_intr_list,
- unsigned int int_grp);
-#endif
unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num);
diff --git a/drivers/arm/pl011/pl011_console.S b/drivers/arm/pl011/pl011_console.S
deleted file mode 100644
index 1789f15..0000000
--- a/drivers/arm/pl011/pl011_console.S
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/pl011_console.S"
-#endif
diff --git a/drivers/arm/tzc400/tzc400.c b/drivers/arm/tzc400/tzc400.c
deleted file mode 100644
index ff2ebc7..0000000
--- a/drivers/arm/tzc400/tzc400.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if ERROR_DEPRECATED
-#error "Using deprecated TZC-400 source file"
-#else
-#include "../tzc/tzc400.c"
-#endif /* ERROR_DEPRECATED */
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 71c496e..cfbd86a 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -60,16 +60,6 @@
endif
endif
-# If MBEDTLS_KEY_ALG build flag is defined use it to set TF_MBEDTLS_KEY_ALG for
-# backward compatibility
-ifdef MBEDTLS_KEY_ALG
- ifeq (${ERROR_DEPRECATED},1)
- $(error "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
- endif
- $(warning "MBEDTLS_KEY_ALG is deprecated. Please use the new build flag TF_MBEDTLS_KEY_ALG")
- TF_MBEDTLS_KEY_ALG := ${MBEDTLS_KEY_ALG}
-endif
-
ifeq (${HASH_ALG}, sha384)
TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384
else ifeq (${HASH_ALG}, sha512)
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index fc357f8..6732631 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -15,9 +15,11 @@
.globl console_cdns_core_init
.globl console_cdns_core_putc
.globl console_cdns_core_getc
+ .globl console_cdns_core_flush
.globl console_cdns_putc
.globl console_cdns_getc
+ .globl console_cdns_flush
/* -----------------------------------------------
* int console_cdns_core_init(uintptr_t base_addr)
@@ -87,6 +89,7 @@
.equ console_core_init,console_cdns_core_init
.equ console_core_putc,console_cdns_core_putc
.equ console_core_getc,console_cdns_core_getc
+ .equ console_core_flush,console_cdns_core_flush
#endif
/* --------------------------------------------------------
@@ -188,8 +191,7 @@
endfunc console_cdns_getc
/* ---------------------------------------------
- * int console_core_flush(uintptr_t base_addr)
- * DEPRECATED: Not used with MULTI_CONSOLE_API!
+ * int console_cdns_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
@@ -197,8 +199,30 @@
* Clobber list : x0, x1
* ---------------------------------------------
*/
-func console_core_flush
+func console_cdns_core_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
/* Placeholder */
mov w0, #0
ret
-endfunc console_core_flush
+endfunc console_cdns_core_flush
+
+ /* ---------------------------------------------
+ * int console_cdns_flush(console_pl011_t *console)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - pointer to console_t structure
+ * Out : return -1 on error else return 0.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_cdns_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x0, [x0, #CONSOLE_T_CDNS_BASE]
+ b console_cdns_core_flush
+endfunc console_cdns_flush
diff --git a/drivers/cadence/uart/cdns_console.S b/drivers/cadence/uart/cdns_console.S
deleted file mode 100644
index 6da8f91..0000000
--- a/drivers/cadence/uart/cdns_console.S
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/cdns_console.S"
-#endif
diff --git a/drivers/console/console.S b/drivers/console/console.S
deleted file mode 100644
index c48530c..0000000
--- a/drivers/console/console.S
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/console.S"
-#endif
diff --git a/drivers/console/skeleton_console.S b/drivers/console/skeleton_console.S
deleted file mode 100644
index 905370d..0000000
--- a/drivers/console/skeleton_console.S
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/skeleton_console.S"
-#endif
diff --git a/drivers/delay_timer/delay_timer.c b/drivers/delay_timer/delay_timer.c
index 587724e..feac357 100644
--- a/drivers/delay_timer/delay_timer.c
+++ b/drivers/delay_timer/delay_timer.c
@@ -20,20 +20,21 @@
***********************************************************/
void udelay(uint32_t usec)
{
- assert(timer_ops != NULL &&
- (timer_ops->clk_mult != 0) &&
- (timer_ops->clk_div != 0) &&
+ assert((timer_ops != NULL) &&
+ (timer_ops->clk_mult != 0U) &&
+ (timer_ops->clk_div != 0U) &&
(timer_ops->get_timer_value != NULL));
uint32_t start, delta, total_delta;
- assert(usec < UINT32_MAX / timer_ops->clk_div);
+ assert(usec < (UINT32_MAX / timer_ops->clk_div));
start = timer_ops->get_timer_value();
/* Add an extra tick to avoid delaying less than requested. */
total_delta =
- div_round_up(usec * timer_ops->clk_div, timer_ops->clk_mult) + 1;
+ div_round_up(usec * timer_ops->clk_div,
+ timer_ops->clk_mult) + 1U;
do {
/*
@@ -51,7 +52,7 @@
***********************************************************/
void mdelay(uint32_t msec)
{
- udelay(msec*1000);
+ udelay(msec * 1000U);
}
/***********************************************************
@@ -60,9 +61,9 @@
***********************************************************/
void timer_init(const timer_ops_t *ops_ptr)
{
- assert(ops_ptr != NULL &&
- (ops_ptr->clk_mult != 0) &&
- (ops_ptr->clk_div != 0) &&
+ assert((ops_ptr != NULL) &&
+ (ops_ptr->clk_mult != 0U) &&
+ (ops_ptr->clk_div != 0U) &&
(ops_ptr->get_timer_value != NULL));
timer_ops = ops_ptr;
diff --git a/drivers/delay_timer/generic_delay_timer.c b/drivers/delay_timer/generic_delay_timer.c
index 8a36c8a..03ca532 100644
--- a/drivers/delay_timer/generic_delay_timer.c
+++ b/drivers/delay_timer/generic_delay_timer.c
@@ -49,9 +49,9 @@
unsigned int div = plat_get_syscnt_freq2();
/* Reduce multiplier and divider by dividing them repeatedly by 10 */
- while ((mult % 10 == 0) && (div % 10 == 0)) {
- mult /= 10;
- div /= 10;
+ while (((mult % 10U) == 0U) && ((div % 10U) == 0U)) {
+ mult /= 10U;
+ div /= 10U;
}
generic_delay_timer_init_args(mult, div);
diff --git a/drivers/mentor/i2c/mi2cv.c b/drivers/mentor/i2c/mi2cv.c
index 1b73e6f..8ebd966 100644
--- a/drivers/mentor/i2c/mi2cv.c
+++ b/drivers/mentor/i2c/mi2cv.c
@@ -15,6 +15,7 @@
#include <delay_timer.h>
#include <errno.h>
#include <mentor/mi2cv.h>
+#include <mentor_i2c_plat.h>
#include <mmio.h>
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 73287ae..418ab11 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -87,7 +87,7 @@
}
ret = mmc_send_cmd(MMC_CMD(13), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R(1), &resp_data[0]);
+ MMC_RESPONSE_R1, &resp_data[0]);
if (ret != 0) {
return ret;
}
@@ -138,14 +138,14 @@
/* CMD55: Application Specific Command */
ret = mmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R5, NULL);
if (ret != 0) {
return ret;
}
/* ACMD51: SEND_SCR */
do {
- ret = mmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(MMC_ACMD(51), 0, MMC_RESPONSE_R1, NULL);
if ((ret != 0) && (retries == 0)) {
ERROR("ACMD51 failed after %d retries (ret=%d)\n",
MMC_DEFAULT_MAX_RETRIES, ret);
@@ -167,13 +167,13 @@
/* CMD55: Application Specific Command */
ret = mmc_send_cmd(MMC_CMD(55), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R5, NULL);
if (ret != 0) {
return ret;
}
/* ACMD6: SET_BUS_WIDTH */
- ret = mmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(MMC_ACMD(6), bus_width_arg, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
@@ -235,7 +235,7 @@
}
/* MMC CMD8: SEND_EXT_CSD */
- ret = mmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(MMC_CMD(8), 0, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
@@ -327,7 +327,7 @@
int ret;
/* CMD55: Application Specific Command */
- ret = mmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(MMC_CMD(55), 0, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
@@ -416,7 +416,7 @@
} else {
/* CMD8: Send Interface Condition Command */
ret = mmc_send_cmd(MMC_CMD(8), VHS_2_7_3_6_V | CMD8_CHECK_PATTERN,
- MMC_RESPONSE_R(7), &resp_data[0]);
+ MMC_RESPONSE_R5, &resp_data[0]);
if ((ret == 0) && ((resp_data[0] & 0xffU) == CMD8_CHECK_PATTERN)) {
ret = sd_send_op_cond();
@@ -427,7 +427,7 @@
}
/* CMD2: Card Identification */
- ret = mmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R(2), NULL);
+ ret = mmc_send_cmd(MMC_CMD(2), 0, MMC_RESPONSE_R2, NULL);
if (ret != 0) {
return ret;
}
@@ -436,13 +436,13 @@
if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
rca = MMC_FIX_RCA;
ret = mmc_send_cmd(MMC_CMD(3), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
} else {
ret = mmc_send_cmd(MMC_CMD(3), 0,
- MMC_RESPONSE_R(6), &resp_data[0]);
+ MMC_RESPONSE_R6, &resp_data[0]);
if (ret != 0) {
return ret;
}
@@ -452,7 +452,7 @@
/* CMD9: CSD Register */
ret = mmc_send_cmd(MMC_CMD(9), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R(2), &resp_data[0]);
+ MMC_RESPONSE_R2, &resp_data[0]);
if (ret != 0) {
return ret;
}
@@ -461,7 +461,7 @@
/* CMD7: Select Card */
ret = mmc_send_cmd(MMC_CMD(7), rca << RCA_SHIFT_OFFSET,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return ret;
}
@@ -499,7 +499,7 @@
if (is_cmd23_enabled()) {
/* Set block count */
ret = mmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
@@ -520,7 +520,7 @@
cmd_arg = lba;
}
- ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
@@ -567,7 +567,7 @@
if (is_cmd23_enabled()) {
/* Set block count */
ret = mmc_send_cmd(MMC_CMD(23), size / MMC_BLOCK_SIZE,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
@@ -587,7 +587,7 @@
cmd_arg = lba;
}
- ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(cmd_idx, cmd_arg, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
@@ -622,18 +622,18 @@
assert(ops != NULL);
assert((size != 0U) && ((size & MMC_BLOCK_MASK) == 0U));
- ret = mmc_send_cmd(MMC_CMD(35), lba, MMC_RESPONSE_R(1), NULL);
+ ret = mmc_send_cmd(MMC_CMD(35), lba, MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
ret = mmc_send_cmd(MMC_CMD(36), lba + (size / MMC_BLOCK_SIZE) - 1U,
- MMC_RESPONSE_R(1), NULL);
+ MMC_RESPONSE_R1, NULL);
if (ret != 0) {
return 0;
}
- ret = mmc_send_cmd(MMC_CMD(38), lba, MMC_RESPONSE_R(0x1B), NULL);
+ ret = mmc_send_cmd(MMC_CMD(38), lba, MMC_RESPONSE_R1B, NULL);
if (ret != 0) {
return 0;
}
diff --git a/drivers/synopsys/emmc/dw_mmc.c b/drivers/synopsys/emmc/dw_mmc.c
index c544233..eb42819 100644
--- a/drivers/synopsys/emmc/dw_mmc.c
+++ b/drivers/synopsys/emmc/dw_mmc.c
@@ -263,10 +263,7 @@
op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
CMD_RESP_LEN;
break;
- case MMC_RESPONSE_R1:
- case MMC_RESPONSE_R1B:
case MMC_RESPONSE_R3:
- case MMC_RESPONSE_R5:
op |= CMD_RESP_EXPECT;
break;
default:
diff --git a/drivers/ti/uart/16550_console.S b/drivers/ti/uart/16550_console.S
deleted file mode 100644
index 03ca526..0000000
--- a/drivers/ti/uart/16550_console.S
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/16550_console.S"
-#endif
diff --git a/include/bl32/sp_min/platform_sp_min.h b/include/bl32/sp_min/platform_sp_min.h
index 8f6a82d..2d71a47 100644
--- a/include/bl32/sp_min/platform_sp_min.h
+++ b/include/bl32/sp_min/platform_sp_min.h
@@ -10,10 +10,6 @@
/*******************************************************************************
* Mandatory SP_MIN functions
******************************************************************************/
-#if !ERROR_DEPRECATED
-void sp_min_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2);
-#endif
void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3);
void sp_min_platform_setup(void);
diff --git a/include/common/aarch64/asm_macros.S b/include/common/aarch64/asm_macros.S
index 6e66ea9..9621a1c 100644
--- a/include/common/aarch64/asm_macros.S
+++ b/include/common/aarch64/asm_macros.S
@@ -98,36 +98,6 @@
.endm
/*
- * This macro verifies that the given vector doesn't exceed the
- * architectural limit of 32 instructions. This is meant to be placed
- * immediately after the last instruction in the vector. It takes the
- * vector entry as the parameter
- */
- .macro check_vector_size since
-#if ERROR_DEPRECATED
- .error "check_vector_size must not be used. Use end_vector_entry instead"
-#endif
- end_vector_entry \since
- .endm
-
-#if ENABLE_PLAT_COMPAT
- /*
- * This macro calculates the base address of an MP stack using the
- * platform_get_core_pos() index, the name of the stack storage and
- * the size of each stack
- * In: X0 = MPIDR of CPU whose stack is wanted
- * Out: X0 = physical address of stack base
- * Clobber: X30, X1, X2
- */
- .macro get_mp_stack _name, _size
- bl platform_get_core_pos
- ldr x2, =(\_name + \_size)
- mov x1, #\_size
- madd x0, x0, x1, x2
- .endm
-#endif
-
- /*
* This macro calculates the base address of the current CPU's MP stack
* using the plat_my_core_pos() index, the name of the stack storage
* and the size of each stack
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 6478f12..bfe1d8c 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -107,10 +107,6 @@
typedef struct meminfo {
uintptr_t total_base;
size_t total_size;
-#if !LOAD_IMAGE_V2
- uintptr_t free_base;
- size_t free_size;
-#endif
} meminfo_t;
/*****************************************************************************
@@ -124,9 +120,7 @@
param_header_t h;
uintptr_t image_base; /* physical address of base of image */
uint32_t image_size; /* bytes read from image file */
-#if LOAD_IMAGE_V2
uint32_t image_max_size;
-#endif
} image_info_t;
/*****************************************************************************
@@ -145,7 +139,6 @@
entry_point_info_t ep_info;
} image_desc_t;
-#if LOAD_IMAGE_V2
/* BL image node in the BL image loading sequence */
typedef struct bl_load_info_node {
unsigned int image_id;
@@ -176,33 +169,6 @@
bl_params_node_t *head;
} bl_params_t;
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * This structure represents the superset of information that can be passed to
- * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
- * populated only if BL2 detects its presence. A pointer to a structure of this
- * type should be passed in X0 to BL31's cold boot entrypoint.
- *
- * Use of this structure and the X0 parameter is not mandatory: the BL31
- * platform code can use other mechanisms to provide the necessary information
- * about BL32 and BL33 to the common and SPD code.
- *
- * BL31 image information is mandatory if this structure is used. If either of
- * the optional BL32 and BL33 image information is not provided, this is
- * indicated by the respective image_info pointers being zero.
- ******************************************************************************/
-typedef struct bl31_params {
- param_header_t h;
- image_info_t *bl31_image_info;
- entry_point_info_t *bl32_ep_info;
- image_info_t *bl32_image_info;
- entry_point_info_t *bl33_ep_info;
- image_info_t *bl33_image_info;
-} bl31_params_t;
-
-#endif /* LOAD_IMAGE_V2 */
-
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
@@ -211,27 +177,8 @@
int is_mem_free(uintptr_t free_base, size_t free_size,
uintptr_t addr, size_t size);
-#if LOAD_IMAGE_V2
-
int load_auth_image(unsigned int image_id, image_info_t *image_data);
-#else
-
-int load_image(meminfo_t *mem_layout,
- unsigned int image_id,
- uintptr_t image_base,
- image_info_t *image_data,
- entry_point_info_t *entry_point_info);
-int load_auth_image(meminfo_t *mem_layout,
- unsigned int image_id,
- uintptr_t image_base,
- image_info_t *image_data,
- entry_point_info_t *entry_point_info);
-void reserve_mem(uintptr_t *free_base, size_t *free_size,
- uintptr_t addr, size_t size);
-
-#endif /* LOAD_IMAGE_V2 */
-
#if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH)
/*
* API to dynamically disable authentication. Only meant for development
diff --git a/include/common/desc_image_load.h b/include/common/desc_image_load.h
index 73aa27c..1ed2b15 100644
--- a/include/common/desc_image_load.h
+++ b/include/common/desc_image_load.h
@@ -8,7 +8,6 @@
#include <bl_common.h>
-#if LOAD_IMAGE_V2
/* Following structure is used to store BL ep/image info. */
typedef struct bl_mem_params_node {
unsigned int image_id;
@@ -38,5 +37,4 @@
bl_params_t *get_next_bl_params_from_mem_params_desc(void);
void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params);
-#endif /* LOAD_IMAGE_V2 */
#endif /* __DESC_IMAGE_LOAD_H__ */
diff --git a/include/drivers/arm/arm_gic.h b/include/drivers/arm/arm_gic.h
deleted file mode 100644
index 8d2a232..0000000
--- a/include/drivers/arm/arm_gic.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __ARM_GIC_H__
-#define __ARM_GIC_H__
-
-#include <cdefs.h>
-#include <stdint.h>
-
-/*******************************************************************************
- * Function declarations
- ******************************************************************************/
-void arm_gic_init(uintptr_t gicc_base,
- uintptr_t gicd_base,
- uintptr_t gicr_base,
- const unsigned int *irq_sec_ptr,
- unsigned int num_irqs) __deprecated;
-void arm_gic_setup(void) __deprecated;
-void arm_gic_cpuif_deactivate(void) __deprecated;
-void arm_gic_cpuif_setup(void) __deprecated;
-void arm_gic_pcpu_distif_setup(void) __deprecated;
-
-uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
- uint32_t security_state) __deprecated;
-uint32_t arm_gic_get_pending_interrupt_type(void) __deprecated;
-uint32_t arm_gic_get_pending_interrupt_id(void) __deprecated;
-uint32_t arm_gic_acknowledge_interrupt(void) __deprecated;
-void arm_gic_end_of_interrupt(uint32_t id) __deprecated;
-uint32_t arm_gic_get_interrupt_type(uint32_t id) __deprecated;
-
-#endif /* __GIC_H__ */
diff --git a/include/drivers/arm/cci400.h b/include/drivers/arm/cci400.h
deleted file mode 100644
index e11dad4..0000000
--- a/include/drivers/arm/cci400.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __CCI_400_H__
-#define __CCI_400_H__
-
-/**************************************************************
- * THIS DRIVER IS DEPRECATED. Please use the driver in cci.h
- **************************************************************/
-#if ERROR_DEPRECATED
-#error " The CCI-400 specific driver is deprecated."
-#endif
-
-
-/* Slave interface offsets from PERIPHBASE */
-#define SLAVE_IFACE4_OFFSET 0x5000
-#define SLAVE_IFACE3_OFFSET 0x4000
-#define SLAVE_IFACE2_OFFSET 0x3000
-#define SLAVE_IFACE1_OFFSET 0x2000
-#define SLAVE_IFACE0_OFFSET 0x1000
-#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + \
- (0x1000 * (index))
-
-/* Control and ID register offsets */
-#define CTRL_OVERRIDE_REG 0x0
-#define SPEC_CTRL_REG 0x4
-#define SECURE_ACCESS_REG 0x8
-#define STATUS_REG 0xc
-#define IMPRECISE_ERR_REG 0x10
-#define PERFMON_CTRL_REG 0x100
-
-/* Slave interface register offsets */
-#define SNOOP_CTRL_REG 0x0
-#define SH_OVERRIDE_REG 0x4
-#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
-#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
-#define QOS_CTRL_REG 0x10c
-#define MAX_OT_REG 0x110
-#define TARGET_LATENCY_REG 0x130
-#define LATENCY_REGULATION_REG 0x134
-#define QOS_RANGE_REG 0x138
-
-/* Snoop Control register bit definitions */
-#define DVM_EN_BIT (1 << 1)
-#define SNOOP_EN_BIT (1 << 0)
-
-/* Status register bit definitions */
-#define CHANGE_PENDING_BIT (1 << 0)
-
-#ifndef __ASSEMBLY__
-
-#include <stdint.h>
-
-/* Function declarations */
-
-/*
- * The CCI-400 driver must be initialized with the base address of the
- * CCI-400 device in the platform memory map, and the cluster indices for
- * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully
- * coherent ACE slave interfaces of CCI-400.
- * The cluster indices must either be 0 or 1, corresponding to the level 1
- * affinity instance of the mpidr representing the cluster. A negative cluster
- * index indicates that no cluster is present on that slave interface.
- */
-void cci_init(uintptr_t cci_base,
- int slave_iface3_cluster_ix,
- int slave_iface4_cluster_ix) __deprecated;
-
-void cci_enable_cluster_coherency(unsigned long mpidr) __deprecated;
-void cci_disable_cluster_coherency(unsigned long mpidr) __deprecated;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __CCI_400_H__ */
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
deleted file mode 100644
index 258b898..0000000
--- a/include/drivers/arm/gic_v2.h
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __GIC_V2_H__
-#define __GIC_V2_H__
-
-/* The macros required here are additional to those in gic_common.h. */
-#include <gic_common.h>
-
-/******************************************************************************
- * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
- * and for GICv3 systems, use the driver in gicv3.h.
- *****************************************************************************/
-#if ERROR_DEPRECATED
-#error " The legacy ARM GIC driver is deprecated."
-#endif
-
-#define GIC400_NUM_SPIS U(480)
-#define MAX_PPIS U(14)
-#define MAX_SGIS U(16)
-
-
-#define GRP0 U(0)
-#define GRP1 U(1)
-#define GIC_TARGET_CPU_MASK U(0xff)
-
-#define ENABLE_GRP0 (U(1) << 0)
-#define ENABLE_GRP1 (U(1) << 1)
-
-/* Distributor interface definitions */
-#define GICD_ITARGETSR U(0x800)
-#define GICD_SGIR U(0xF00)
-#define GICD_CPENDSGIR U(0xF10)
-#define GICD_SPENDSGIR U(0xF20)
-
-#define CPENDSGIR_SHIFT U(2)
-#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
-
-/* GICD_TYPER bit definitions */
-#define IT_LINES_NO_MASK U(0x1f)
-
-/* Physical CPU Interface registers */
-#define GICC_CTLR U(0x0)
-#define GICC_PMR U(0x4)
-#define GICC_BPR U(0x8)
-#define GICC_IAR U(0xC)
-#define GICC_EOIR U(0x10)
-#define GICC_RPR U(0x14)
-#define GICC_HPPIR U(0x18)
-#define GICC_AHPPIR U(0x28)
-#define GICC_IIDR U(0xFC)
-#define GICC_DIR U(0x1000)
-#define GICC_PRIODROP GICC_EOIR
-
-/* Common CPU Interface definitions */
-#define INT_ID_MASK U(0x3ff)
-
-/* GICC_CTLR bit definitions */
-#define EOI_MODE_NS (U(1) << 10)
-#define EOI_MODE_S (U(1) << 9)
-#define IRQ_BYP_DIS_GRP1 (U(1) << 8)
-#define FIQ_BYP_DIS_GRP1 (U(1) << 7)
-#define IRQ_BYP_DIS_GRP0 (U(1) << 6)
-#define FIQ_BYP_DIS_GRP0 (U(1) << 5)
-#define CBPR (U(1) << 4)
-#define FIQ_EN (U(1) << 3)
-#define ACK_CTL (U(1) << 2)
-
-/* GICC_IIDR bit masks and shifts */
-#define GICC_IIDR_PID_SHIFT U(20)
-#define GICC_IIDR_ARCH_SHIFT U(16)
-#define GICC_IIDR_REV_SHIFT U(12)
-#define GICC_IIDR_IMP_SHIFT U(0)
-
-#define GICC_IIDR_PID_MASK U(0xfff)
-#define GICC_IIDR_ARCH_MASK U(0xf)
-#define GICC_IIDR_REV_MASK U(0xf)
-#define GICC_IIDR_IMP_MASK U(0xfff)
-
-/* HYP view virtual CPU Interface registers */
-#define GICH_CTL U(0x0)
-#define GICH_VTR U(0x4)
-#define GICH_ELRSR0 U(0x30)
-#define GICH_ELRSR1 U(0x34)
-#define GICH_APR0 U(0xF0)
-#define GICH_LR_BASE U(0x100)
-
-/* Virtual CPU Interface registers */
-#define GICV_CTL U(0x0)
-#define GICV_PRIMASK U(0x4)
-#define GICV_BP U(0x8)
-#define GICV_INTACK U(0xC)
-#define GICV_EOI U(0x10)
-#define GICV_RUNNINGPRI U(0x14)
-#define GICV_HIGHESTPEND U(0x18)
-#define GICV_DEACTIVATE U(0x1000)
-
-#ifndef __ASSEMBLY__
-
-#include <mmio.h>
-#include <stdint.h>
-
-/*******************************************************************************
- * GIC Distributor function prototypes
- ******************************************************************************/
-
-unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
-unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
-unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
-unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
-unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
-unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
-unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
-unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
-unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
-unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
-unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
-unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
-void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
-void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
-void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
-void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
-void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
-unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
-void gicd_set_igroupr(uintptr_t, unsigned int);
-void gicd_clr_igroupr(uintptr_t, unsigned int);
-void gicd_set_isenabler(uintptr_t, unsigned int);
-void gicd_set_icenabler(uintptr_t, unsigned int);
-void gicd_set_ispendr(uintptr_t, unsigned int);
-void gicd_set_icpendr(uintptr_t, unsigned int);
-void gicd_set_isactiver(uintptr_t, unsigned int);
-void gicd_set_icactiver(uintptr_t, unsigned int);
-void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
-void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
-
-
-/*******************************************************************************
- * GIC Distributor interface accessors for reading entire registers
- ******************************************************************************/
-
-static inline unsigned int gicd_read_ctlr(uintptr_t base)
-{
- return mmio_read_32(base + GICD_CTLR);
-}
-
-static inline unsigned int gicd_read_typer(uintptr_t base)
-{
- return mmio_read_32(base + GICD_TYPER);
-}
-
-static inline unsigned int gicd_read_sgir(uintptr_t base)
-{
- return mmio_read_32(base + GICD_SGIR);
-}
-
-
-/*******************************************************************************
- * GIC Distributor interface accessors for writing entire registers
- ******************************************************************************/
-
-static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICD_CTLR, val);
-}
-
-static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICD_SGIR, val);
-}
-
-
-/*******************************************************************************
- * GIC CPU interface accessors for reading entire registers
- ******************************************************************************/
-
-static inline unsigned int gicc_read_ctlr(uintptr_t base)
-{
- return mmio_read_32(base + GICC_CTLR);
-}
-
-static inline unsigned int gicc_read_pmr(uintptr_t base)
-{
- return mmio_read_32(base + GICC_PMR);
-}
-
-static inline unsigned int gicc_read_BPR(uintptr_t base)
-{
- return mmio_read_32(base + GICC_BPR);
-}
-
-static inline unsigned int gicc_read_IAR(uintptr_t base)
-{
- return mmio_read_32(base + GICC_IAR);
-}
-
-static inline unsigned int gicc_read_EOIR(uintptr_t base)
-{
- return mmio_read_32(base + GICC_EOIR);
-}
-
-static inline unsigned int gicc_read_hppir(uintptr_t base)
-{
- return mmio_read_32(base + GICC_HPPIR);
-}
-
-static inline unsigned int gicc_read_ahppir(uintptr_t base)
-{
- return mmio_read_32(base + GICC_AHPPIR);
-}
-
-static inline unsigned int gicc_read_dir(uintptr_t base)
-{
- return mmio_read_32(base + GICC_DIR);
-}
-
-static inline unsigned int gicc_read_iidr(uintptr_t base)
-{
- return mmio_read_32(base + GICC_IIDR);
-}
-
-
-/*******************************************************************************
- * GIC CPU interface accessors for writing entire registers
- ******************************************************************************/
-
-static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_CTLR, val);
-}
-
-static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_PMR, val);
-}
-
-static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_BPR, val);
-}
-
-
-static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_IAR, val);
-}
-
-static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_EOIR, val);
-}
-
-static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_HPPIR, val);
-}
-
-static inline void gicc_write_dir(uintptr_t base, unsigned int val)
-{
- mmio_write_32(base + GICC_DIR, val);
-}
-
-/*******************************************************************************
- * Prototype of function to map an interrupt type to the interrupt line used to
- * signal it.
- ******************************************************************************/
-uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
-
-#endif /*__ASSEMBLY__*/
-
-#endif /* __GIC_V2_H__ */
diff --git a/include/drivers/arm/gic_v3.h b/include/drivers/arm/gic_v3.h
deleted file mode 100644
index 549b4d9..0000000
--- a/include/drivers/arm/gic_v3.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __GIC_V3_H__
-#define __GIC_V3_H__
-
-/******************************************************************************
- * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
- * and for GICv3 systems, use the driver in gicv3.h.
- *****************************************************************************/
-#if ERROR_DEPRECATED
-#error " The legacy ARM GIC driver is deprecated."
-#endif
-
-#include <mmio.h>
-#include <stdint.h>
-
-/* GICv3 Re-distributor interface registers & shifts */
-#define GICR_PCPUBASE_SHIFT 0x11
-#define GICR_TYPER 0x08
-#define GICR_WAKER 0x14
-
-/* GICR_WAKER bit definitions */
-#define WAKER_CA (U(1) << 2)
-#define WAKER_PS (U(1) << 1)
-
-/* GICR_TYPER bit definitions */
-#define GICR_TYPER_AFF_SHIFT 32
-#define GICR_TYPER_AFF_MASK 0xffffffff
-#define GICR_TYPER_LAST (U(1) << 4)
-
-/* GICv3 ICC_SRE register bit definitions*/
-#define ICC_SRE_EN (U(1) << 3)
-#define ICC_SRE_SRE (U(1) << 0)
-
-/*******************************************************************************
- * GICv3 defintions
- ******************************************************************************/
-#define GICV3_AFFLVL_MASK 0xff
-#define GICV3_AFF0_SHIFT 0
-#define GICV3_AFF1_SHIFT 8
-#define GICV3_AFF2_SHIFT 16
-#define GICV3_AFF3_SHIFT 24
-#define GICV3_AFFINITY_MASK 0xffffffff
-
-/*******************************************************************************
- * Function prototypes
- ******************************************************************************/
-uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr);
-
-/*******************************************************************************
- * GIC Redistributor interface accessors
- ******************************************************************************/
-static inline uint32_t gicr_read_waker(uintptr_t base)
-{
- return mmio_read_32(base + GICR_WAKER);
-}
-
-static inline void gicr_write_waker(uintptr_t base, uint32_t val)
-{
- mmio_write_32(base + GICR_WAKER, val);
-}
-
-static inline uint64_t gicr_read_typer(uintptr_t base)
-{
- return mmio_read_64(base + GICR_TYPER);
-}
-
-
-#endif /* __GIC_V3_H__ */
diff --git a/include/drivers/arm/gicv2.h b/include/drivers/arm/gicv2.h
index d0480db..c80f80b 100644
--- a/include/drivers/arm/gicv2.h
+++ b/include/drivers/arm/gicv2.h
@@ -7,6 +7,8 @@
#ifndef __GICV2_H__
#define __GICV2_H__
+#include <gic_common.h>
+
/*******************************************************************************
* GICv2 miscellaneous definitions
******************************************************************************/
@@ -132,14 +134,6 @@
* The 'gicc_base' field contains the base address of the CPU Interface
* programmer's view.
*
- * The 'g0_interrupt_array' field is a pointer to an array in which each entry
- * corresponds to an ID of a Group 0 interrupt. This field is ignored when
- * 'interrupt_props' field is used. This field is deprecated.
- *
- * The 'g0_interrupt_num' field contains the number of entries in the
- * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
- * used. This field is deprecated.
- *
* The 'target_masks' is a pointer to an array containing 'target_masks_num'
* elements. The GIC driver will populate the array with per-PE target mask to
* use to when targeting interrupts.
@@ -155,10 +149,6 @@
typedef struct gicv2_driver_data {
uintptr_t gicd_base;
uintptr_t gicc_base;
-#if !ERROR_DEPRECATED
- unsigned int g0_interrupt_num __deprecated;
- const unsigned int *g0_interrupt_array __deprecated;
-#endif
unsigned int *target_masks;
unsigned int target_masks_num;
const interrupt_prop_t *interrupt_props;
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index c9e28ba..9c291eb 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -276,23 +276,6 @@
* The 'gicr_base' field contains the base address of the Re-distributor
* interface programmer's view.
*
- * The 'g0_interrupt_array' field is a pointer to an array in which each entry
- * corresponds to an ID of a Group 0 interrupt. This field is ignored when
- * 'interrupt_props' field is used. This field is deprecated.
- *
- * The 'g0_interrupt_num' field contains the number of entries in the
- * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
- * used. This field is deprecated.
- *
- * The 'g1s_interrupt_array' field is a pointer to an array in which each entry
- * corresponds to an ID of a Group 1 interrupt. This field is ignored when
- * 'interrupt_props' field is used. This field is deprecated.
- *
- * The 'g1s_interrupt_num' field contains the number of entries in the
- * 'g1s_interrupt_array'. This field must be 0 if 'interrupt_props' field is
- * used. This field is ignored when 'interrupt_props' field is used. This field
- * is deprecated.
- *
* The 'interrupt_props' field is a pointer to an array that enumerates secure
* interrupts and their properties. If this field is not NULL, both
* 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
@@ -326,12 +309,6 @@
typedef struct gicv3_driver_data {
uintptr_t gicd_base;
uintptr_t gicr_base;
-#if !ERROR_DEPRECATED
- unsigned int g0_interrupt_num __deprecated;
- unsigned int g1s_interrupt_num __deprecated;
- const unsigned int *g0_interrupt_array __deprecated;
- const unsigned int *g1s_interrupt_array __deprecated;
-#endif
const interrupt_prop_t *interrupt_props;
unsigned int interrupt_props_num;
unsigned int rdistif_num;
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 7f354f8..095099c 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -86,16 +86,6 @@
TZC_REGION_ATTR_F_EN_SHIFT)
/*
- * Define some macros for backward compatibility with existing tzc400 clients.
- */
-#if !ERROR_DEPRECATED
-#define REG_ATTR_FILTER_BIT(x) ((1 << x) \
- << TZC_REGION_ATTR_F_EN_SHIFT)
-#define REG_ATTR_FILTER_BIT_ALL (TZC_400_REGION_ATTR_F_EN_MASK << \
- TZC_REGION_ATTR_F_EN_SHIFT)
-#endif /* __ERROR_DEPRECATED__ */
-
-/*
* All TZC region configuration registers are placed one after another. It
* depicts size of block of registers for programming each region.
*/
@@ -123,24 +113,6 @@
void tzc400_enable_filters(void);
void tzc400_disable_filters(void);
-/*
- * Deprecated APIs
- */
-static inline void tzc_init(uintptr_t base) __deprecated;
-static inline void tzc_configure_region0(
- tzc_region_attributes_t sec_attr,
- unsigned int ns_device_access) __deprecated;
-static inline void tzc_configure_region(
- unsigned int filters,
- int region,
- unsigned long long region_base,
- unsigned long long region_top,
- tzc_region_attributes_t sec_attr,
- unsigned int ns_device_access) __deprecated;
-static inline void tzc_set_action(tzc_action_t action) __deprecated;
-static inline void tzc_enable_filters(void) __deprecated;
-static inline void tzc_disable_filters(void) __deprecated;
-
static inline void tzc_init(uintptr_t base)
{
tzc400_init(base);
diff --git a/include/drivers/auth/mbedtls/mbedtls_config.h b/include/drivers/auth/mbedtls/mbedtls_config.h
index 59aeea9..cc57b77 100644
--- a/include/drivers/auth/mbedtls/mbedtls_config.h
+++ b/include/drivers/auth/mbedtls/mbedtls_config.h
@@ -30,9 +30,6 @@
/* Prevent mbed TLS from using snprintf so that it can use tf_snprintf. */
#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-#if !ERROR_DEPRECATED
-#define MBEDTLS_PKCS1_V15
-#endif
#define MBEDTLS_PKCS1_V21
#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 50e0800..9900630 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -45,12 +45,12 @@
/* JEDEC 4.51 chapter 6.12 */
#define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
#define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY)
-#define MMC_RESPONSE_R2 (MMC_RSP_136 | MMC_RSP_CRC)
+#define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC)
#define MMC_RESPONSE_R3 (MMC_RSP_48)
#define MMC_RESPONSE_R4 (MMC_RSP_48)
-#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC)
-
-#define MMC_RESPONSE_R(_x) U(_x)
+#define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
+#define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX)
/* Value randomly chosen for eMMC RCA, it should be > 1 */
#define MMC_FIX_RCA 6
diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index f9ed56e..3536d20 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -126,10 +126,6 @@
#define SDCR_SPD_ENABLE U(0x3)
#define SDCR_RESET_VAL U(0x0)
-#if !ERROR_DEPRECATED
-#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
-#endif
-
/* HSCTLR definitions */
#define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
@@ -220,10 +216,6 @@
#define NSASEDIS_BIT (U(1) << 15)
#define NSTRCDIS_BIT (U(1) << 20)
/* NOTE: correct typo in the definitions */
-#if !ERROR_DEPRECATED
-#define NASCR_CP11_BIT (U(1) << 11)
-#define NASCR_CP10_BIT (U(1) << 10)
-#endif
#define NSACR_CP11_BIT (U(1) << 11)
#define NSACR_CP10_BIT (U(1) << 10)
#define NSACR_IMP_DEF_MASK (U(0x7) << 16)
@@ -576,7 +568,7 @@
#define PAR_F_SHIFT U(0)
#define PAR_F_MASK ULL(0x1)
#define PAR_ADDR_SHIFT U(12)
-#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
+#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
/*******************************************************************************
* Definitions for system register interface to AMU for ARMv8.4 onwards
diff --git a/include/lib/aarch32/smcc_helpers.h b/include/lib/aarch32/smcc_helpers.h
deleted file mode 100644
index 7f79f8f..0000000
--- a/include/lib/aarch32/smcc_helpers.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_HELPERS_H__
-#define __SMCC_HELPERS_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc_helpers.h>
-#endif
-
-#endif /* __SMCC_HELPERS_H__ */
diff --git a/include/lib/aarch32/smcc_macros.S b/include/lib/aarch32/smcc_macros.S
deleted file mode 100644
index 66f3d0e..0000000
--- a/include/lib/aarch32/smcc_macros.S
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef __SMCC_MACROS_S__
-#define __SMCC_MACROS_S__
-
-#if !ERROR_DEPRECATED
-#include <smccc_macros.S>
-
-#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs
-#endif
-
-#endif /* __SMCC_MACROS_S__ */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index fed5944..a6022cb 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -245,10 +245,6 @@
#define MDCR_TPM_BIT (U(1) << 6)
#define MDCR_EL3_RESET_VAL U(0x0)
-#if !ERROR_DEPRECATED
-#define MDCR_DEF_VAL (MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
-#endif
-
/* MDCR_EL2 definitions */
#define MDCR_EL2_TPMS (U(1) << 14)
#define MDCR_EL2_E2PB(x) ((x) << 12)
diff --git a/include/lib/aarch64/smcc_helpers.h b/include/lib/aarch64/smcc_helpers.h
deleted file mode 100644
index 11300b7..0000000
--- a/include/lib/aarch64/smcc_helpers.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_HELPERS_H__
-#define __SMCC_HELPERS_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc_helpers.h>
-#endif
-
-#endif /* __SMCC_HELPERS_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a53.h b/include/lib/cpus/aarch32/cortex_a53.h
index 8e86df4..a7a681f 100644
--- a/include/lib/cpus/aarch32/cortex_a53.h
+++ b/include/lib/cpus/aarch32/cortex_a53.h
@@ -67,16 +67,4 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR p15, 3, c15
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A53_ACTLR CORTEX_A53_CPUACTLR
-
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT
-#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_ENDCCASCI
-#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_DTAH
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a57.h b/include/lib/cpus/aarch32/cortex_a57.h
index 18cabe1..3f0fb04 100644
--- a/include/lib/cpus/aarch32/cortex_a57.h
+++ b/include/lib/cpus/aarch32/cortex_a57.h
@@ -79,22 +79,4 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR p15, 3, c15
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A57_ACTLR CORTEX_A57_CPUACTLR
-
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE
-#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_DIS_OVERREAD
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_DCC_AS_DCCI
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_FORCE_FPSCR_FLUSH
-#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_DIS_STREAMING
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_DIS_L1_STREAMING
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_DIS_INDIRECT_PREDICTOR
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 0331ace..1a3c014 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -54,16 +54,4 @@
******************************************************************************/
#define CORTEX_A72_L2MERRSR p15, 3, c15
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR
-
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A72_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h
index 22c6800..9aa118b 100644
--- a/include/lib/cpus/aarch64/cortex_a53.h
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -71,21 +71,4 @@
******************************************************************************/
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions
- * so as not to break platforms that continue using them.
- */
-#define CORTEX_A53_ACTLR_EL1 CORTEX_A53_CPUACTLR_EL1
-
-#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT
-#define CORTEX_A53_ACTLR_ENDCCASCI CORTEX_A53_CPUACTLR_EL1_ENDCCASCI
-#define CORTEX_A53_ACTLR_RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT
-#define CORTEX_A53_ACTLR_RADIS CORTEX_A53_CPUACTLR_EL1_RADIS
-#define CORTEX_A53_ACTLR_L1RADIS_SHIFT CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT
-#define CORTEX_A53_ACTLR_L1RADIS CORTEX_A53_CPUACTLR_EL1_L1RADIS
-#define CORTEX_A53_ACTLR_DTAH_SHIFT CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT
-#define CORTEX_A53_ACTLR_DTAH CORTEX_A53_CPUACTLR_EL1_DTAH
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 83ec934..97d074e 100644
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -81,22 +81,4 @@
******************************************************************************/
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A57_ACTLR_EL1 CORTEX_A57_CPUACTLR_EL1
-
-#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB
-#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE
-#define CORTEX_A57_ACTLR_DIS_OVERREAD CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD
-#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA
-#define CORTEX_A57_ACTLR_DCC_AS_DCCI CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI
-#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH
-#define CORTEX_A57_ACTLR_DIS_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING
-#define CORTEX_A57_ACTLR_DIS_L1_STREAMING CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING
-#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index f5ca2ee..5b9e06d 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -61,16 +61,4 @@
******************************************************************************/
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
-#if !ERROR_DEPRECATED
-/*
- * These registers were previously wrongly named. Provide previous definitions so
- * as not to break platforms that continue using them.
- */
-#define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR_EL1
-
-#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
-#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA
-#define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI
-#endif /* !ERROR_DEPRECATED */
-
#endif /* __CORTEX_A72_H__ */
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index e3f7726..c5bbb2b 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -47,16 +47,6 @@
void cm_set_next_eret_context(uint32_t security_state);
uint32_t cm_get_scr_el3(uint32_t security_state);
-
-void cm_init_context(uint64_t mpidr,
- const struct entry_point_info *ep) __deprecated;
-
-void *cm_get_context_by_mpidr(uint64_t mpidr,
- uint32_t security_state) __deprecated;
-void cm_set_context_by_mpidr(uint64_t mpidr,
- void *context,
- uint32_t security_state) __deprecated;
-
/* Inline definitions */
/*******************************************************************************
diff --git a/include/lib/psci/psci.h b/include/lib/psci/psci.h
index fa0da9f..b27e481 100644
--- a/include/lib/psci/psci.h
+++ b/include/lib/psci/psci.h
@@ -10,9 +10,6 @@
#include <bakery_lock.h>
#include <bl_common.h>
#include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */
-#if ENABLE_PLAT_COMPAT
-#include <psci_compat.h>
-#endif
#include <psci_lib.h> /* To maintain compatibility for SPDs */
#include <utils_def.h>
@@ -350,12 +347,6 @@
void __dead2 psci_power_down_wfi(void);
void psci_arch_setup(void);
-/*
- * The below API is deprecated. This is now replaced by bl31_warmboot_entry in
- * AArch64.
- */
-void psci_entrypoint(void) __deprecated;
-
#endif /*__ASSEMBLY__*/
#endif /* PSCI_H */
diff --git a/include/lib/psci/psci_compat.h b/include/lib/psci/psci_compat.h
deleted file mode 100644
index 11ed16d..0000000
--- a/include/lib/psci/psci_compat.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PSCI_COMPAT_H
-#define PSCI_COMPAT_H
-
-#include <arch.h>
-#include <platform_def.h>
-#include <utils_def.h>
-
-#ifndef __ASSEMBLY__
-/*
- * The below declarations are to enable compatibility for the platform ports
- * using the old platform interface and psci helpers.
- */
-#define PLAT_MAX_PWR_LVL PLATFORM_MAX_AFFLVL
-#define PLAT_NUM_PWR_DOMAINS PLATFORM_NUM_AFFS
-
-/*******************************************************************************
- * PSCI affinity related constants. An affinity instance could
- * be present or absent physically to cater for asymmetric topologies.
- ******************************************************************************/
-#define PSCI_AFF_ABSENT 0x0
-#define PSCI_AFF_PRESENT 0x1
-
-#define PSCI_STATE_ON U(0x0)
-#define PSCI_STATE_OFF U(0x1)
-#define PSCI_STATE_ON_PENDING U(0x2)
-#define PSCI_STATE_SUSPEND U(0x3)
-
-/*
- * Using the compatibility platform interfaces means that the local states
- * used in psci_power_state_t need to only convey whether its power down
- * or standby state. The onus is on the platform port to do the right thing
- * including the state coordination in case multiple power down states are
- * involved. Hence if we assume 3 generic states viz, run, standby and
- * power down, we can assign 1 and 2 to standby and power down respectively.
- */
-#define PLAT_MAX_RET_STATE U(1)
-#define PLAT_MAX_OFF_STATE U(2)
-
-/*
- * Macro to represent invalid affinity level within PSCI.
- */
-#define PSCI_INVALID_DATA -1
-
-#define psci_get_pstate_afflvl(pstate) psci_get_pstate_pwrlvl(pstate)
-
-/*
- * This array stores the 'power_state' requests of each CPU during
- * CPU_SUSPEND and SYSTEM_SUSPEND which will be populated by the
- * compatibility layer when appropriate platform hooks are invoked.
- */
-extern unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT];
-
-/*******************************************************************************
- * Structure populated by platform specific code to export routines which
- * perform common low level pm functions
- ******************************************************************************/
-typedef struct plat_pm_ops {
- void (*affinst_standby)(unsigned int power_state);
- int (*affinst_on)(unsigned long mpidr,
- unsigned long sec_entrypoint,
- unsigned int afflvl,
- unsigned int state);
- void (*affinst_off)(unsigned int afflvl, unsigned int state);
- void (*affinst_suspend)(unsigned long sec_entrypoint,
- unsigned int afflvl,
- unsigned int state);
- void (*affinst_on_finish)(unsigned int afflvl, unsigned int state);
- void (*affinst_suspend_finish)(unsigned int afflvl,
- unsigned int state);
- void (*system_off)(void) __dead2;
- void (*system_reset)(void) __dead2;
- int (*validate_power_state)(unsigned int power_state);
- int (*validate_ns_entrypoint)(unsigned long ns_entrypoint);
- unsigned int (*get_sys_suspend_power_state)(void);
-} plat_pm_ops_t;
-
-/*******************************************************************************
- * Function & Data prototypes to enable compatibility for older platform ports
- ******************************************************************************/
-int psci_get_suspend_stateid_by_mpidr(unsigned long);
-int psci_get_suspend_stateid(void);
-int psci_get_suspend_powerstate(void);
-unsigned int psci_get_max_phys_off_afflvl(void);
-int psci_get_suspend_afflvl(void);
-
-#endif /* ____ASSEMBLY__ */
-#endif /* PSCI_COMPAT_H */
diff --git a/include/lib/smcc.h b/include/lib/smcc.h
deleted file mode 100644
index ed1da2c..0000000
--- a/include/lib/smcc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __SMCC_H__
-#define __SMCC_H__
-
-#if !ERROR_DEPRECATED
-#include <smccc.h>
-#endif
-
-#endif /* __SMCC_H__ */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index a07e510..b3dad10 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -57,17 +57,6 @@
* does not equal SMC_UNK. This is to ensure that the caller won't mistake the
* returned UUID in x0 for an invalid SMC error return
*/
-#if !ERROR_DEPRECATED
-#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \
- _n0, _n1, _n2, _n3, _n4, _n5) \
- CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
- static const uuid_t _name = { \
- _tl, _tm, _th, _cl, _ch, \
- { _n0, _n1, _n2, _n3, _n4, _n5 } \
- }
-#endif
-
-
#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
_n0, _n1, _n2, _n3, _n4, _n5) \
CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
diff --git a/include/lib/smccc_v1.h b/include/lib/smccc_v1.h
index 8718d15..98ef021 100644
--- a/include/lib/smccc_v1.h
+++ b/include/lib/smccc_v1.h
@@ -66,9 +66,6 @@
#define SMC_32 U(0)
#define SMC_TYPE_FAST ULL(1)
-#if !ERROR_DEPRECATED
-#define SMC_TYPE_STD ULL(0)
-#endif
#define SMC_TYPE_YIELD ULL(0)
#define SMC_OK ULL(0)
diff --git a/include/lib/utils.h b/include/lib/utils.h
index 09ec8d9..d46d846 100644
--- a/include/lib/utils.h
+++ b/include/lib/utils.h
@@ -7,10 +7,6 @@
#ifndef __UTILS_H__
#define __UTILS_H__
-#if !ERROR_DEPRECATED
-#include <utils_def.h>
-#endif
-
/*
* C code should be put in this part of the header to avoid breaking ASM files
* or linker scripts including it.
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 5b4fd78..1dd57cb 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -50,7 +50,7 @@
#define div_round_up(val, div) __extension__ ({ \
__typeof__(div) _div = (div); \
- ((val) + _div - 1) / _div; \
+ ((val) + _div - (__typeof__(div)) 1) / _div; \
})
#define MIN(x, y) __extension__ ({ \
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index ab491e3..85effca 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -67,11 +67,6 @@
#ifdef AARCH32
/* AArch32 specific translation table API */
-#if !ERROR_DEPRECATED
-void enable_mmu_secure(unsigned int flags);
-void enable_mmu_direct(unsigned int flags);
-#endif
-
void enable_mmu_svc_mon(unsigned int flags);
void enable_mmu_hyp(unsigned int flags);
diff --git a/include/lib/xlat_tables/xlat_tables.h b/include/lib/xlat_tables/xlat_tables.h
index 4097c76..050679d 100644
--- a/include/lib/xlat_tables/xlat_tables.h
+++ b/include/lib/xlat_tables/xlat_tables.h
@@ -71,10 +71,6 @@
#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE)
#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER)
-#if !ERROR_DEPRECATED
-typedef unsigned int mmap_attr_t;
-#endif
-
/*
* Structure for specifying a single region of memory.
*/
diff --git a/include/lib/xlat_tables/xlat_tables_v2.h b/include/lib/xlat_tables/xlat_tables_v2.h
index 52c4dc6..4bd0bb2 100644
--- a/include/lib/xlat_tables/xlat_tables_v2.h
+++ b/include/lib/xlat_tables/xlat_tables_v2.h
@@ -104,10 +104,6 @@
#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER)
#define MT_RW_DATA (MT_MEMORY | MT_RW | MT_EXECUTE_NEVER)
-#if !ERROR_DEPRECATED
-typedef unsigned int mmap_attr_t;
-#endif
-
/*
* Structure for specifying a single region of memory.
*/
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
index 9af8f8c..a927208 100644
--- a/include/plat/arm/board/common/board_arm_def.h
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -8,7 +8,6 @@
#include <v2m_def.h>
-
/*
* Required platform porting definitions common to all ARM
* development platforms
@@ -41,90 +40,6 @@
# define PLATFORM_STACK_SIZE 0x440
#endif
-/*
- * The constants below are not optimised for memory usage. Platforms that wish
- * to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and
- * provide there own values.
- */
-#if !ARM_BOARD_OPTIMISE_MEM
-/*
- * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
- * plat_arm_mmap array defined for each BL stage.
- *
- * Provide relatively optimised values for the runtime images (BL31 and BL32).
- * Optimisation is less important for the other, transient boot images so a
- * common, maximum value is used across these images.
- *
- * They are also used for the dynamically mapped regions in the images that
- * enable dynamic memory mapping.
- */
-#if defined(IMAGE_BL31)
-# if ENABLE_SPM
-# define PLAT_ARM_MMAP_ENTRIES 9
-# define MAX_XLAT_TABLES 7
-# define PLAT_SP_IMAGE_MMAP_REGIONS 7
-# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
-# else
-# define PLAT_ARM_MMAP_ENTRIES 8
-# define MAX_XLAT_TABLES 5
-# endif
-#elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES 8
-# define MAX_XLAT_TABLES 5
-#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES 11
-# define MAX_XLAT_TABLES 5
-#else
-# define PLAT_ARM_MMAP_ENTRIES 12
-# define MAX_XLAT_TABLES 6
-#endif
-
-/*
- * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
- * plus a little space for growth.
- */
-#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
-
-/*
- * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
- */
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
-#endif
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
-#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x11000
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of
- * BL2 and BL1-RW
- */
-#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
-
-#ifdef AARCH32
-/*
- * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
- * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
- * BL2 and BL1-RW
- */
-# define PLAT_ARM_MAX_BL32_SIZE 0x3B000
-#endif
-
-#endif /* ARM_BOARD_OPTIMISE_MEM */
-
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index c499417..23cd12f 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -166,21 +166,6 @@
#define ARM_IRQ_SEC_SGI_7 15
/*
- * List of secure interrupts are deprecated, but are retained only to support
- * legacy configurations.
- */
-#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \
- ARM_IRQ_SEC_SGI_1, \
- ARM_IRQ_SEC_SGI_2, \
- ARM_IRQ_SEC_SGI_3, \
- ARM_IRQ_SEC_SGI_4, \
- ARM_IRQ_SEC_SGI_5, \
- ARM_IRQ_SEC_SGI_7
-
-#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \
- ARM_IRQ_SEC_SGI_6
-
-/*
* Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 53b4a45..3f344ab 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -17,7 +17,6 @@
/*******************************************************************************
* Forward declarations
******************************************************************************/
-struct bl31_params;
struct meminfo;
struct image_info;
struct bl_params;
@@ -197,13 +196,8 @@
void arm_bl2u_plat_arch_setup(void);
/* BL31 utility functions */
-#if LOAD_IMAGE_V2
void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
uintptr_t hw_config, void *plat_params_from_bl2);
-#else
-void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config,
- uintptr_t hw_config, void *plat_params_from_bl2);
-#endif /* LOAD_IMAGE_V2 */
void arm_bl31_platform_setup(void);
void arm_bl31_plat_runtime_setup(void);
void arm_bl31_plat_arch_setup(void);
@@ -252,13 +246,11 @@
unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
#endif
-#if LOAD_IMAGE_V2
/*
* This function is called after loading SCP_BL2 image and it is used to perform
* any platform-specific actions required to handle the SCP firmware.
*/
int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
-#endif
/*
* Optional functions required in ARM standard platforms
diff --git a/include/plat/common/common_def.h b/include/plat/common/common_def.h
index e66af78..64807fd 100644
--- a/include/plat/common/common_def.h
+++ b/include/plat/common/common_def.h
@@ -31,7 +31,6 @@
*/
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-#if LOAD_IMAGE_V2
#define BL2_IMAGE_DESC { \
.image_id = BL2_IMAGE_ID, \
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \
@@ -42,17 +41,6 @@
VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\
.ep_info.pc = BL2_BASE, \
}
-#else /* LOAD_IMAGE_V2 */
-#define BL2_IMAGE_DESC { \
- .image_id = BL2_IMAGE_ID, \
- SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \
- VERSION_1, image_info_t, 0), \
- .image_info.image_base = BL2_BASE, \
- SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \
- VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),\
- .ep_info.pc = BL2_BASE, \
-}
-#endif /* LOAD_IMAGE_V2 */
/*
* The following constants identify the extents of the code & read-only data
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index e0297ae..a30b579 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -17,7 +17,6 @@
struct meminfo;
struct image_info;
struct entry_point_info;
-struct bl31_params;
struct image_desc;
struct bl_load_info;
struct bl_params;
@@ -38,7 +37,6 @@
/*******************************************************************************
* Mandatory common functions
******************************************************************************/
-unsigned long long plat_get_syscnt_freq(void) __deprecated;
unsigned int plat_get_syscnt_freq2(void);
int plat_get_image_source(unsigned int image_id,
@@ -136,10 +134,6 @@
/*******************************************************************************
* Optional BL1 functions (may be overridden)
******************************************************************************/
-#if !ERROR_DEPRECATED
-void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout,
- struct meminfo *bl2_mem_layout);
-#endif
/*
* The following functions are used for image loading process in BL1.
*/
@@ -169,14 +163,10 @@
* Mandatory BL2 functions
******************************************************************************/
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3);
-#if !ERROR_DEPRECATED
-void bl2_early_platform_setup(struct meminfo *mem_layout);
-#endif
void bl2_plat_arch_setup(void);
void bl2_platform_setup(void);
struct meminfo *bl2_plat_sec_mem_layout(void);
-#if LOAD_IMAGE_V2
/*
* This function can be used by the platforms to update/use image
* information for given `image_id`.
@@ -184,67 +174,8 @@
int bl2_plat_handle_pre_image_load(unsigned int image_id);
int bl2_plat_handle_post_image_load(unsigned int image_id);
-#else /* LOAD_IMAGE_V2 */
-
-/*
- * This function returns a pointer to the shared memory that the platform has
- * kept aside to pass trusted firmware related information that BL31
- * could need
- */
-struct bl31_params *bl2_plat_get_bl31_params(void);
-
-/*
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- */
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void);
-
-/*
- * This function flushes to main memory all the params that are
- * passed to BL31
- */
-void bl2_plat_flush_bl31_params(void);
-
-/*
- * The next 2 functions allow the platform to change the entrypoint information
- * for the mandatory 3rd level BL images, BL31 and BL33. This is done after
- * BL2 has loaded those images into memory but before BL31 is executed.
- */
-void bl2_plat_set_bl31_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-void bl2_plat_set_bl33_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-/* Gets the memory layout for BL33 */
-void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
-
-/*******************************************************************************
- * Conditionally mandatory BL2 functions: must be implemented if SCP_BL2 image
- * is supported
- ******************************************************************************/
-/* Gets the memory layout for SCP_BL2 */
-void bl2_plat_get_scp_bl2_meminfo(struct meminfo *mem_info);
-
-/*
- * This function is called after loading SCP_BL2 image and it is used to perform
- * any platform-specific actions required to handle the SCP firmware.
- */
-int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info);
/*******************************************************************************
- * Conditionally mandatory BL2 functions: must be implemented if BL32 image
- * is supported
- ******************************************************************************/
-void bl2_plat_set_bl32_ep_info(struct image_info *image,
- struct entry_point_info *ep);
-
-/* Gets the memory layout for BL32 */
-void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
-
-#endif /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
* Optional BL2 functions (may be overridden)
******************************************************************************/
@@ -283,15 +214,6 @@
/*******************************************************************************
* Mandatory BL31 functions
******************************************************************************/
-#if !ERROR_DEPRECATED
-#if LOAD_IMAGE_V2
-void bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2);
-#else
-void bl31_early_platform_setup(struct bl31_params *from_bl2,
- void *plat_params_from_bl2);
-#endif
-#endif /* ERROR_DEPRECATED */
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3);
void bl31_plat_arch_setup(void);
@@ -345,7 +267,6 @@
const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
void *cookie);
-#if LOAD_IMAGE_V2
/*******************************************************************************
* Mandatory BL image load functions(may be overridden).
******************************************************************************/
@@ -368,36 +289,11 @@
*/
void plat_flush_next_bl_params(void);
-#endif /* LOAD_IMAGE_V2 */
-
-#if ENABLE_PLAT_COMPAT
-/*
- * The below declarations are to enable compatibility for the platform ports
- * using the old platform interface.
- */
-
-/*******************************************************************************
- * Optional common functions (may be overridden)
- ******************************************************************************/
-unsigned int platform_get_core_pos(unsigned long mpidr);
-
-/*******************************************************************************
- * Mandatory PSCI Compatibility functions (BL31)
- ******************************************************************************/
-int platform_setup_pm(const plat_pm_ops_t **);
-
-unsigned int plat_get_aff_count(unsigned int, unsigned long);
-unsigned int plat_get_aff_state(unsigned int, unsigned long);
-
-#else /* __ENABLE_PLAT_COMPAT__ */
/*
* The below function enable Trusted Firmware components like SPDs which
* haven't migrated to the new platform API to compile on platforms which
* have the compatibility layer disabled.
*/
unsigned int platform_core_pos_helper(unsigned long mpidr);
-unsigned int platform_get_core_pos(unsigned long mpidr) __deprecated;
-
-#endif /* __ENABLE_PLAT_COMPAT__ */
#endif /* PLATFORM_H */
diff --git a/include/plat/marvell/a8k/common/board_marvell_def.h b/include/plat/marvell/a8k/common/board_marvell_def.h
index b1054db..e67543e 100644
--- a/include/plat/marvell/a8k/common/board_marvell_def.h
+++ b/include/plat/marvell/a8k/common/board_marvell_def.h
@@ -14,9 +14,7 @@
*/
/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-# define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
+#if IMAGE_BL1
#if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
#else
diff --git a/include/plat/marvell/a8k/common/plat_marvell.h b/include/plat/marvell/a8k/common/plat_marvell.h
index 9ca68d3..a62a7cb 100644
--- a/include/plat/marvell/a8k/common/plat_marvell.h
+++ b/include/plat/marvell/a8k/common/plat_marvell.h
@@ -24,6 +24,15 @@
<= MAX_MMAP_REGIONS, \
assert_max_mmap_regions)
+struct marvell_bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+};
+
/*
* Utility functions common to Marvell standard platforms
*/
@@ -67,7 +76,7 @@
uint32_t marvell_get_spsr_for_bl33_entry(void);
/* BL31 utility functions */
-void marvell_bl31_early_platform_setup(struct bl31_params *from_bl2,
+void marvell_bl31_early_platform_setup(void *from_bl2,
uintptr_t soc_fw_config,
uintptr_t hw_config,
void *plat_params_from_bl2);
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 3c64d3c..1a075aa 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -56,16 +56,6 @@
endfunc smc
/* -----------------------------------------------------------------------
- * void zeromem16(void *mem, unsigned int length);
- *
- * Initialise a memory region to 0.
- * The memory address must be 16-byte aligned.
- * NOTE: This function is deprecated and zeromem should be used instead.
- * -----------------------------------------------------------------------
- */
-.equ zeromem16, zeromem
-
-/* -----------------------------------------------------------------------
* void zero_normalmem(void *mem, unsigned int length);
*
* Initialise a region in normal memory to 0. This functions complies with the
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
deleted file mode 100644
index 04cbf3c..0000000
--- a/lib/aarch64/xlat_tables.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/*
- * This file is deprecated and is retained here only for compatibility.
- * The xlat_tables library can be found in `lib/xlat_tables` directory.
- */
-#if !ERROR_DEPRECATED
-#include "../xlat_tables/xlat_tables_common.c"
-#include "../xlat_tables/aarch64/xlat_tables.c"
-#endif
diff --git a/lib/locks/exclusive/spinlock.S b/lib/locks/exclusive/spinlock.S
deleted file mode 100644
index 2141f98..0000000
--- a/lib/locks/exclusive/spinlock.S
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "./aarch64/spinlock.S"
-#endif
diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S
index 06d6636..88db1c9 100644
--- a/lib/psci/aarch64/psci_helpers.S
+++ b/lib/psci/aarch64/psci_helpers.S
@@ -12,9 +12,6 @@
.globl psci_do_pwrdown_cache_maintenance
.globl psci_do_pwrup_cache_maintenance
.globl psci_power_down_wfi
-#if !ERROR_DEPRECATED
- .globl psci_entrypoint
-#endif
/* -----------------------------------------------------------------------
* void psci_do_pwrdown_cache_maintenance(unsigned int power level);
@@ -131,12 +128,3 @@
wfi
no_ret plat_panic_handler
endfunc psci_power_down_wfi
-
-/* -----------------------------------------------------------------------
- * void psci_entrypoint(void);
- * The deprecated entry point for PSCI on warm boot for AArch64.
- * -----------------------------------------------------------------------
- */
-func_deprecated psci_entrypoint
- b bl31_warm_entrypoint
-endfunc_deprecated psci_entrypoint
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index ec74a8c..b877b4b 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -938,84 +938,6 @@
return (n_valid > 1U) ? 1 : 0;
}
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
- * PSCI Compatibility helper function to return the 'power_state' parameter of
- * the PSCI CPU SUSPEND request for the current CPU. Returns PSCI_INVALID_DATA
- * if not invoked within CPU_SUSPEND for the current CPU.
- ******************************************************************************/
-int psci_get_suspend_powerstate(void)
-{
- /* Sanity check to verify that CPU is within CPU_SUSPEND */
- if (psci_get_aff_info_state() == AFF_STATE_ON &&
- !is_local_state_run(psci_get_cpu_local_state()))
- return psci_power_state_compat[plat_my_core_pos()];
-
- return PSCI_INVALID_DATA;
-}
-
-/*******************************************************************************
- * PSCI Compatibility helper function to return the state id of the current
- * cpu encoded in the 'power_state' parameter. Returns PSCI_INVALID_DATA
- * if not invoked within CPU_SUSPEND for the current CPU.
- ******************************************************************************/
-int psci_get_suspend_stateid(void)
-{
- unsigned int power_state;
- power_state = psci_get_suspend_powerstate();
- if (power_state != PSCI_INVALID_DATA)
- return psci_get_pstate_id(power_state);
-
- return PSCI_INVALID_DATA;
-}
-
-/*******************************************************************************
- * PSCI Compatibility helper function to return the state id encoded in the
- * 'power_state' parameter of the CPU specified by 'mpidr'. Returns
- * PSCI_INVALID_DATA if the CPU is not in CPU_SUSPEND.
- ******************************************************************************/
-int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr)
-{
- int cpu_idx = plat_core_pos_by_mpidr(mpidr);
-
- if (cpu_idx == -1)
- return PSCI_INVALID_DATA;
-
- /* Sanity check to verify that the CPU is in CPU_SUSPEND */
- if ((psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_ON) &&
- (!is_local_state_run(psci_get_cpu_local_state_by_idx(cpu_idx))))
- return psci_get_pstate_id(psci_power_state_compat[cpu_idx]);
-
- return PSCI_INVALID_DATA;
-}
-
-/*******************************************************************************
- * This function returns highest affinity level which is in OFF
- * state. The affinity instance with which the level is associated is
- * determined by the caller.
- ******************************************************************************/
-unsigned int psci_get_max_phys_off_afflvl(void)
-{
- psci_power_state_t state_info;
-
- zeromem(&state_info, sizeof(state_info));
- psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info);
-
- return psci_find_target_suspend_lvl(&state_info);
-}
-
-/*******************************************************************************
- * PSCI Compatibility helper function to return target affinity level requested
- * for the CPU_SUSPEND. This function assumes affinity levels correspond to
- * power domain levels on the platform.
- ******************************************************************************/
-int psci_get_suspend_afflvl(void)
-{
- return psci_get_suspend_pwrlvl();
-}
-
-#endif
-
/*******************************************************************************
* Initiate power down sequence, by calling power down operations registered for
* this CPU.
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index 033e237..5595703 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -61,22 +61,6 @@
assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
}
-/*******************************************************************************
- * Function for enabling the MMU in Secure PL1, assuming that the
- * page-tables have already been created.
- ******************************************************************************/
-#if !ERROR_DEPRECATED
-void enable_mmu_secure(unsigned int flags)
-{
- enable_mmu_svc_mon(flags);
-}
-
-void enable_mmu_direct(unsigned int flags)
-{
- enable_mmu_direct_svc_mon(flags);
-}
-#endif
-
void enable_mmu_svc_mon(unsigned int flags)
{
unsigned int mair0, ttbcr, sctlr;
diff --git a/lib/xlat_tables/xlat_tables_private.h b/lib/xlat_tables/xlat_tables_private.h
index f882f7e..fad967e 100644
--- a/lib/xlat_tables/xlat_tables_private.h
+++ b/lib/xlat_tables/xlat_tables_private.h
@@ -15,23 +15,6 @@
#error xlat tables v2 must be used with HW_ASSISTED_COHERENCY
#endif
-/*
- * If the platform hasn't defined a physical and a virtual address space size
- * default to ADDR_SPACE_SIZE.
- */
-#if ERROR_DEPRECATED
-# ifdef ADDR_SPACE_SIZE
-# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead."
-# endif
-#elif defined(ADDR_SPACE_SIZE)
-# ifndef PLAT_PHY_ADDR_SPACE_SIZE
-# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
-# endif
-# ifndef PLAT_VIRT_ADDR_SPACE_SIZE
-# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
-# endif
-#endif
-
CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(PLAT_VIRT_ADDR_SPACE_SIZE),
assert_valid_virt_addr_space_size);
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index bf0cc9f..4a4cb94 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -19,24 +19,6 @@
uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
/*
- * Each platform can define the size of its physical and virtual address spaces.
- * If the platform hasn't defined one or both of them, default to
- * ADDR_SPACE_SIZE. The latter is deprecated, though.
- */
-#if ERROR_DEPRECATED
-# ifdef ADDR_SPACE_SIZE
-# error "ADDR_SPACE_SIZE is deprecated. Use PLAT_xxx_ADDR_SPACE_SIZE instead."
-# endif
-#elif defined(ADDR_SPACE_SIZE)
-# ifndef PLAT_PHY_ADDR_SPACE_SIZE
-# define PLAT_PHY_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
-# endif
-# ifndef PLAT_VIRT_ADDR_SPACE_SIZE
-# define PLAT_VIRT_ADDR_SPACE_SIZE ADDR_SPACE_SIZE
-# endif
-#endif
-
-/*
* Allocate and initialise the default translation context for the BL image
* currently executing.
*/
@@ -121,18 +103,6 @@
#ifdef AARCH32
-#if !ERROR_DEPRECATED
-void enable_mmu_secure(unsigned int flags)
-{
- enable_mmu_svc_mon(flags);
-}
-
-void enable_mmu_direct(unsigned int flags)
-{
- enable_mmu_direct_svc_mon(flags);
-}
-#endif
-
void enable_mmu_svc_mon(unsigned int flags)
{
setup_mmu_cfg((uint64_t *)&mmu_cfg_params, flags,
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 908da22..7df4cd2 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -23,10 +23,6 @@
ARM_ARCH_MAJOR := 8
ARM_ARCH_MINOR := 0
-# Determine the version of ARM GIC architecture to use for interrupt management
-# in EL3. The platform port can change this value if needed.
-ARM_GIC_ARCH := 2
-
# Base commit to perform code check on
BASE_COMMIT := origin/master
@@ -116,9 +112,6 @@
# Set the default algorithm for the generation of Trusted Board Boot keys
KEY_ALG := rsa
-# Flag to enable new version of image loading
-LOAD_IMAGE_V2 := 0
-
# Enable use of the console API allowing multiple consoles to be registered
# at the same time.
MULTI_CONSOLE_API := 0
@@ -169,14 +162,14 @@
# Flags to build TF with Trusted Boot support
TRUSTED_BOARD_BOOT := 0
-# Build option to choose whether Trusted firmware uses Coherent memory or not.
+# Build option to choose whether Trusted Firmware uses Coherent memory or not.
USE_COHERENT_MEM := 1
-# Build option to choose wheter Trusted firmware uses library at ROM
-USE_ROMLIB := 0
+# Build option to choose whether Trusted Firmware uses library at ROM
+USE_ROMLIB := 0
# Use tbbr_oid.h instead of platform_oid.h
-USE_TBBR_DEFS = $(ERROR_DEPRECATED)
+USE_TBBR_DEFS := 1
# Build verbosity
V := 0
diff --git a/drivers/allwinner/sunxi_i2c.c b/plat/allwinner/common/include/mentor_i2c_plat.h
similarity index 90%
rename from drivers/allwinner/sunxi_i2c.c
rename to plat/allwinner/common/include/mentor_i2c_plat.h
index cc91ca5..f547f9a 100644
--- a/drivers/allwinner/sunxi_i2c.c
+++ b/plat/allwinner/common/include/mentor_i2c_plat.h
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
-
/* This driver provides I2C support for Allwinner sunXi SoCs */
-#include <mmio.h>
+#ifndef SUNXI_I2C_H
+#define SUNXI_I2C_H
#define CONFIG_SYS_TCLK 24000000
#define CONFIG_SYS_I2C_SPEED 100000
@@ -25,4 +25,4 @@
uint32_t soft_reset;
};
-#include "../mentor/i2c/mi2cv.c"
+#endif
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index e2868af..2216654 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -42,14 +42,8 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
-# Disable the PSCI platform compatibility layer.
-ENABLE_PLAT_COMPAT := 0
-
MULTI_CONSOLE_API := 1
-# Prohibit using deprecated interfaces. We rely on this for this platform.
-ERROR_DEPRECATED := 1
-
# The reset vector can be changed for each CPU.
PROGRAMMABLE_RESET_ADDRESS := 1
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index c3901d0..4fb8986 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -15,8 +15,8 @@
-I${AW_PLAT}/${PLAT}/include
PLAT_BL_COMMON_SOURCES := drivers/console/${ARCH}/console.S \
+ drivers/mentor/i2c/mi2cv.c \
drivers/ti/uart/${ARCH}/16550_console.S \
- ${AW_DRIVERS}/sunxi_i2c.c \
${XLAT_TABLES_LIB_SRCS} \
${AW_PLAT}/common/plat_helpers.S \
${AW_PLAT}/common/sunxi_common.c
@@ -44,14 +44,8 @@
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
-# Disable the PSCI platform compatibility layer.
-ENABLE_PLAT_COMPAT := 0
-
MULTI_CONSOLE_API := 1
-# Prohibit using deprecated interfaces. We rely on this for this platform.
-ERROR_DEPRECATED := 1
-
# The reset vector can be changed for each CPU.
PROGRAMMABLE_RESET_ADDRESS := 1
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index f109cce..12438b3 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -28,13 +28,8 @@
{
uint32_t reg;
- /* get currently configured function for pins PL0 and PL1 */
- reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x00);
- if ((reg & 0xff) == 0x33) {
- NOTICE("PMIC: already configured for TWI\n");
- }
-
/* switch pins PL0 and PL1 to I2C */
+ reg = mmio_read_32(SUNXI_R_PIO_BASE + 0x00);
mmio_write_32(SUNXI_R_PIO_BASE + 0x00, (reg & ~0xff) | 0x33);
/* level 2 drive strength */
@@ -47,13 +42,11 @@
/* assert & de-assert reset of R_I2C */
reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
- mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, 0);
- reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
- mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | 0x00010000);
+ mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg & ~BIT(16));
+ mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | BIT(16));
/* un-gate R_I2C clock */
- reg = mmio_read_32(SUNXI_R_PRCM_BASE + 0x19c);
- mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | 0x00000001);
+ mmio_write_32(SUNXI_R_PRCM_BASE + 0x19c, reg | BIT(16) | BIT(0));
/* call mi2cv driver */
i2c_init((void *)SUNXI_R_I2C_BASE);
@@ -127,10 +120,9 @@
switch (pmic) {
case AXP805:
- val = 0x26; /* Default value for REG 32H */
+ sunxi_init_r_i2c();
axp_i2c_read(AXP805_ADDR, 0x32, &val);
- val |= 0x80;
- axp_i2c_write(AXP805_ADDR, 0x32, val);
+ axp_i2c_write(AXP805_ADDR, 0x32, val | 0x80);
break;
default:
break;
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index af47c0d..8b46c4b 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -43,10 +43,3 @@
BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c
endif
-
-# This flag controls whether memory usage needs to be optimised
-ARM_BOARD_OPTIMISE_MEM ?= 0
-
-# Process flags
-$(eval $(call assert_boolean,ARM_BOARD_OPTIMISE_MEM))
-$(eval $(call add_define,ARM_BOARD_OPTIMISE_MEM))
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 1b0c764..3f7857e 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -24,7 +24,6 @@
/* Defines for GIC Driver build time selection */
#define FVP_GICV2 1
#define FVP_GICV3 2
-#define FVP_GICV3_LEGACY 3
/*******************************************************************************
* arm_config holds the characteristics of the differences between the three FVP
@@ -92,9 +91,9 @@
#if TRUSTED_BOARD_BOOT
/* To access the Root of Trust Public Key registers. */
MAP_DEVICE2,
-#if LOAD_IMAGE_V2 && !BL2_AT_EL3
+#if !BL2_AT_EL3
ARM_MAP_BL1_RW,
-#endif /* LOAD_IMAGE_V2 && !BL2_AT_EL3 */
+#endif
#endif /* TRUSTED_BOARD_BOOT */
#if ENABLE_SPM
ARM_SP_IMAGE_MMAP,
@@ -399,7 +398,7 @@
#endif
}
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
assert(heap_addr != NULL);
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index f22a8ec..e4df227 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -64,7 +64,75 @@
*/
#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + U(0x8000000))
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if defined(IMAGE_BL31)
+# if ENABLE_SPM
+# define PLAT_ARM_MMAP_ENTRIES 9
+# define MAX_XLAT_TABLES 7
+# define PLAT_SP_IMAGE_MMAP_REGIONS 7
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
+# else
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 5
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 5
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 5
+#else
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+
+/*
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+ */
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
+#else
+# define PLAT_ARM_MAX_BL2_SIZE 0x11000
+#endif
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of
+ * BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
+#ifdef AARCH32
+/*
+ * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
+ * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
+ * BL2 and BL1-RW
+ */
+# define PLAT_ARM_MAX_BL32_SIZE 0x3B000
+#endif
+
/*
* PL011 related constants
*/
@@ -145,12 +213,6 @@
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
-#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
- FVP_IRQ_TZ_WDOG, \
- FVP_IRQ_SEC_SYS_TIMER
-
-#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
-
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index fd93b99..4cd6a24 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -69,19 +69,6 @@
plat/arm/common/arm_gicv2.c
FVP_DT_PREFIX := fvp-base-gicv2-psci
-
-else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY)
- ifeq (${ARCH}, aarch32)
- $(error "GICV3 Legacy driver not supported for AArch32 build")
- endif
-FVP_GIC_SOURCES := drivers/arm/gic/arm_gic.c \
- drivers/arm/gic/gic_v2.c \
- drivers/arm/gic/gic_v3.c \
- plat/common/plat_gic.c \
- plat/arm/common/arm_gicv3_legacy.c
-
-FVP_DT_PREFIX := fvp-base-gicv2-psci
-
else
$(error "Incorrect GIC driver chosen on FVP port")
endif
@@ -208,9 +195,6 @@
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config))
endif
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
# Enable Activity Monitor Unit extensions by default
ENABLE_AMU := 1
@@ -247,9 +231,7 @@
include plat/arm/common/arm_common.mk
# FVP being a development platform, enable capability to disable Authentication
-# dynamically if TRUSTED_BOARD_BOOT and LOAD_IMAGE_V2 is set.
+# dynamically if TRUSTED_BOARD_BOOT is set.
ifeq (${TRUSTED_BOARD_BOOT}, 1)
- ifeq (${LOAD_IMAGE_V2}, 1)
DYN_DISABLE_AUTH := 1
- endif
endif
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 3f71d73..d130beb 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -76,11 +76,6 @@
#endif /* TRUSTED_BOARD_BOOT */
/*
- * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values
- * defined for ARM development platforms.
- */
-#if ARM_BOARD_OPTIMISE_MEM
-/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
@@ -173,8 +168,6 @@
*/
#define PLAT_LOG_LEVEL_ASSERT 40
-#endif /* ARM_BOARD_OPTIMISE_MEM */
-
/* CCI related constants */
#define PLAT_ARM_CCI_BASE 0x2c090000
#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 481844f..90fa938 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -115,12 +115,6 @@
# power down sequence
SKIP_A57_L1_FLUSH_PWR_DWN := 1
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
-# Enable memory map related constants optimisation
-ARM_BOARD_OPTIMISE_MEM := 1
-
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index d9104ee..717e96f 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -76,16 +76,6 @@
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
-
-#if !LOAD_IMAGE_V2
- /* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = ARM_BL_RAM_BASE;
- bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE;
- reserve_mem(&bl1_tzram_layout.free_base,
- &bl1_tzram_layout.free_size,
- BL1_RAM_BASE,
- BL1_RAM_LIMIT - BL1_RAM_BASE);
-#endif /* LOAD_IMAGE_V2 */
}
void bl1_early_platform_setup(void)
@@ -111,8 +101,11 @@
*****************************************************************************/
void arm_bl1_plat_arch_setup(void)
{
-#if USE_COHERENT_MEM
- /* ARM platforms dont use coherent memory in BL1 */
+#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
+ /*
+ * Ensure ARM platforms don't use coherent memory in BL1 unless
+ * cryptocell integration is enabled.
+ */
assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
#endif
@@ -122,7 +115,10 @@
#if USE_ROMLIB
ARM_MAP_ROMLIB_CODE,
ARM_MAP_ROMLIB_DATA,
- #endif
+#endif
+#if ARM_CRYPTOCELL_INTEG
+ ARM_MAP_BL_COHERENT_RAM,
+#endif
{0}
};
@@ -149,13 +145,12 @@
{
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
-#if LOAD_IMAGE_V2
arm_load_tb_fw_config();
#if TRUSTED_BOARD_BOOT
/* Share the Mbed TLS heap info with other images */
arm_bl1_set_mbedtls_heap();
#endif /* TRUSTED_BOARD_BOOT */
-#endif /* LOAD_IMAGE_V2 */
+
/*
* Allow access to the System counter timer module and program
* counter frequency for non secure images during FWU
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index a8ea075..d31f6dc 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -40,138 +40,9 @@
bl2_tzram_layout.total_size, \
MT_MEMORY | MT_RW | MT_SECURE)
-#if LOAD_IMAGE_V2
#pragma weak arm_bl2_plat_handle_post_image_load
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
- bl31_params_t bl31_params;
- image_info_t bl31_image_info;
- image_info_t bl32_image_info;
- image_info_t bl33_image_info;
- entry_point_info_t bl33_ep_info;
- entry_point_info_t bl32_ep_info;
- entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-
-/* Weak definitions may be overridden in specific ARM standard platform */
-#pragma weak bl2_plat_get_bl31_params
-#pragma weak bl2_plat_get_bl31_ep_info
-#pragma weak bl2_plat_flush_bl31_params
-#pragma weak bl2_plat_set_bl31_ep_info
-#pragma weak bl2_plat_get_scp_bl2_meminfo
-#pragma weak bl2_plat_get_bl32_meminfo
-#pragma weak bl2_plat_set_bl32_ep_info
-#pragma weak bl2_plat_get_bl33_meminfo
-#pragma weak bl2_plat_set_bl33_ep_info
-
-#if ARM_BL31_IN_DRAM
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
- static meminfo_t bl2_dram_layout
- __aligned(CACHE_WRITEBACK_GRANULE) = {
- .total_base = BL31_BASE,
- .total_size = (ARM_AP_TZC_DRAM1_BASE +
- ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
- .free_base = BL31_BASE,
- .free_size = (ARM_AP_TZC_DRAM1_BASE +
- ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
- };
-
- return &bl2_dram_layout;
-}
-#else
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
- return &bl2_tzram_layout;
-}
-#endif /* ARM_BL31_IN_DRAM */
-
-/*******************************************************************************
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem_t structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- ******************************************************************************/
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
- bl31_params_t *bl2_to_bl31_params;
-
- /*
- * Initialise the memory for all the arguments that needs to
- * be passed to BL31
- */
- zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
-
- /* Assign memory for TF related information */
- bl2_to_bl31_params = &bl31_params_mem.bl31_params;
- SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
- /* Fill BL31 related information */
- bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- /* Fill BL32 related information if it exists */
-#ifdef BL32_BASE
- bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
- VERSION_1, 0);
- bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-#endif /* BL32_BASE */
-
- /* Fill BL33 related information */
- bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
- PARAM_EP, VERSION_1, 0);
-
- /* BL33 expects to receive the primary CPU MPID (through x0) */
- bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
- bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- return bl2_to_bl31_params;
-}
-
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
-{
- flush_dcache_range((unsigned long)&bl31_params_mem,
- sizeof(bl2_to_bl31_params_mem_t));
-}
-
-/*******************************************************************************
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- ******************************************************************************/
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
- bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL;
-#endif
-
- return &bl31_params_mem.bl31_ep_info;
-}
-#endif /* LOAD_IMAGE_V2 */
-
/*******************************************************************************
* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
@@ -189,10 +60,8 @@
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
-#if LOAD_IMAGE_V2
if (tb_fw_config != 0U)
arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
-#endif
}
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
@@ -208,9 +77,7 @@
*/
void bl2_plat_preload_setup(void)
{
-#if LOAD_IMAGE_V2
arm_bl2_dyn_cfg_init();
-#endif
}
/*
@@ -237,9 +104,11 @@
******************************************************************************/
void arm_bl2_plat_arch_setup(void)
{
-
-#if USE_COHERENT_MEM
- /* Ensure ARM platforms dont use coherent memory in BL2 */
+#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
+ /*
+ * Ensure ARM platforms don't use coherent memory in BL2 unless
+ * cryptocell integration is enabled.
+ */
assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
#endif
@@ -250,6 +119,9 @@
ARM_MAP_ROMLIB_CODE,
ARM_MAP_ROMLIB_DATA,
#endif
+#if ARM_CRYPTOCELL_INTEG
+ ARM_MAP_BL_COHERENT_RAM,
+#endif
{0}
};
@@ -269,7 +141,6 @@
arm_bl2_plat_arch_setup();
}
-#if LOAD_IMAGE_V2
int arm_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
@@ -337,86 +208,3 @@
{
return arm_bl2_plat_handle_post_image_load(image_id);
}
-
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * Populate the extents of memory available for loading SCP_BL2 (if used),
- * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
- ******************************************************************************/
-void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
-{
- *scp_bl2_meminfo = bl2_tzram_layout;
-}
-
-/*******************************************************************************
- * Before calling this function BL31 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
- entry_point_info_t *bl31_ep_info)
-{
- SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
- bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
-}
-
-
-/*******************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-#ifdef BL32_BASE
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
- entry_point_info_t *bl32_ep_info)
-{
- SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
- bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
- /*
- * Populate the extents of memory available for loading BL32.
- */
- bl32_meminfo->total_base = BL32_BASE;
- bl32_meminfo->free_base = BL32_BASE;
- bl32_meminfo->total_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
- bl32_meminfo->free_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-}
-#endif /* BL32_BASE */
-
-/*******************************************************************************
- * Before calling this function BL33 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
- entry_point_info_t *bl33_ep_info)
-{
- SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
- bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL33
- ******************************************************************************/
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
- bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
- bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
- bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
- bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
-}
-
-#endif /* LOAD_IMAGE_V2 */
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 4e16e3b..364e46a 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -71,13 +71,8 @@
* while creating page tables. BL2 has flushed this information to memory, so
* we are guaranteed to pick up good data.
******************************************************************************/
-#if LOAD_IMAGE_V2
void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
uintptr_t hw_config, void *plat_params_from_bl2)
-#else
-void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config,
- uintptr_t hw_config, void *plat_params_from_bl2)
-#endif
{
/* Initialize the console to provide early debug support */
arm_console_boot_init();
@@ -135,7 +130,6 @@
assert(((unsigned long long)plat_params_from_bl2) ==
ARM_BL31_PLAT_PARAM_VAL);
-# if LOAD_IMAGE_V2
/*
* Check params passed from BL2 should not be NULL,
*/
@@ -162,29 +156,6 @@
if (bl33_image_ep_info.pc == 0U)
panic();
-
-# else /* LOAD_IMAGE_V2 */
-
- /*
- * Check params passed from BL2 should not be NULL,
- */
- assert(from_bl2 != NULL);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
-
- /* Dynamic Config is not supported for LOAD_IMAGE_V1 */
- assert(soc_fw_config == 0U);
- assert(hw_config == 0U);
-
- /*
- * Copy BL32 (if populated by BL2) and BL33 entry point information.
- * They are stored in Secure RAM, in BL2's address space.
- */
- if (from_bl2->bl32_ep_info)
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
-
-# endif /* LOAD_IMAGE_V2 */
#endif /* RESET_TO_BL31 */
}
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index ed43c37..28ff5d9 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -21,9 +21,7 @@
/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid
* conflicts with the definition in plat/common. */
-#if ERROR_DEPRECATED
#pragma weak plat_get_syscnt_freq2
-#endif
void arm_setup_romlib(void)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index d8eda35..a8df5ba 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -122,22 +122,24 @@
# mapping the former as executable and the latter as execute-never.
SEPARATE_CODE_AND_RODATA := 1
-# Enable new version of image loading on ARM platforms
-LOAD_IMAGE_V2 := 1
-
# Use the multi console API, which is only available for AArch64 for now
ifeq (${ARCH}, aarch64)
MULTI_CONSOLE_API := 1
endif
-# Use generic OID definition (tbbr_oid.h)
-USE_TBBR_DEFS := 1
-
# Disable ARM Cryptocell by default
ARM_CRYPTOCELL_INTEG := 0
$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
+# CryptoCell integration relies on coherent buffers for passing data from
+# the AP CPU to the CryptoCell
+ifeq (${ARM_CRYPTOCELL_INTEG},1)
+ ifeq (${USE_COHERENT_MEM},0)
+ $(error "ARM_CRYPTOCELL_INTEG needs USE_COHERENT_MEM to be set.")
+ endif
+endif
+
PLAT_INCLUDES += -Iinclude/common/tbbr \
-Iinclude/plat/arm/common
@@ -194,7 +196,6 @@
BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c
endif
-ifeq (${LOAD_IMAGE_V2},1)
# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
# the AArch32 descriptors.
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
@@ -207,7 +208,6 @@
ifeq (${SPD},opteed)
BL2_SOURCES += lib/optee/optee_utils.c
endif
-endif
BL2U_SOURCES += drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 95fe2c5..057d772 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -17,9 +17,8 @@
#include <string.h>
#include <tbbr_img_def.h>
-#if LOAD_IMAGE_V2
-/* Variable to store the address of TB_FW_CONFIG file */
+/* Variable to store the address to TB_FW_CONFIG passed from BL1 */
static void *tb_fw_cfg_dtb;
static size_t tb_fw_cfg_dtb_size;
@@ -39,9 +38,7 @@
* - To allocate space for the Mbed TLS heap --only if-- Trusted Board Boot
* is enabled.
* - This implementation requires the DTB to be present so that BL1 has a
- * mechanism to pass the pointer to BL2. If LOAD_IMAGE_V2=0 then
- * TB_FW_CONFIG is not present, which means that this implementation
- * cannot be applied.
+ * mechanism to pass the pointer to BL2.
*/
int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
@@ -283,5 +280,3 @@
dyn_disable_auth();
#endif
}
-
-#endif /* LOAD_IMAGE_V2 */
diff --git a/plat/arm/common/arm_gicv3_legacy.c b/plat/arm/common/arm_gicv3_legacy.c
deleted file mode 100644
index e19799a..0000000
--- a/plat/arm/common/arm_gicv3_legacy.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arm_def.h>
-#include <arm_gic.h>
-#include <plat_arm.h>
-#include <platform.h>
-#include <platform_def.h>
-
-/******************************************************************************
- * The following function is defined as weak to allow a platform to override
- * the way the Legacy GICv3 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
-
-/*
- * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
- * 0 interrupts.
- */
-static const unsigned int irq_sec_array[] = {
- PLAT_ARM_G0_IRQS,
- PLAT_ARM_G1S_IRQS
-};
-
-void plat_arm_gic_driver_init(void)
-{
- arm_gic_init(PLAT_ARM_GICC_BASE,
- PLAT_ARM_GICD_BASE,
- PLAT_ARM_GICR_BASE,
- irq_sec_array,
- ARRAY_SIZE(irq_sec_array));
-}
-
-/******************************************************************************
- * ARM common helper to initialize the GIC.
- *****************************************************************************/
-void plat_arm_gic_init(void)
-{
- arm_gic_setup();
-}
-
-/******************************************************************************
- * ARM common helper to enable the GIC CPU interface
- *****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
-{
- arm_gic_cpuif_setup();
-}
-
-/******************************************************************************
- * ARM common helper to disable the GIC CPU interface
- *****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
-{
- arm_gic_cpuif_deactivate();
-}
-
-/******************************************************************************
- * ARM common helper to initialize the per-cpu distributor in GICv2 or
- * redistributor interface in GICv3.
- *****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
-{
- arm_gic_pcpu_distif_setup();
-}
-
-/******************************************************************************
- * Stubs for Redistributor power management. Although legacy configuration isn't
- * supported, these are provided for the sake of uniform GIC API
- *****************************************************************************/
-void plat_arm_gic_redistif_on(void)
-{
- return;
-}
-
-void plat_arm_gic_redistif_off(void)
-{
- return;
-}
-
-/******************************************************************************
- * ARM common helper to save & restore the GICv3 on resume from system suspend.
- *****************************************************************************/
-void plat_arm_gic_save(void)
-{
- return;
-}
-
-void plat_arm_gic_resume(void)
-{
- arm_gic_setup();
-}
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index 4257d3c..bf548c1 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -6,7 +6,6 @@
#include <arch_helpers.h>
#include <arm_def.h>
-#include <arm_gic.h>
#include <assert.h>
#include <errno.h>
#include <plat_arm.h>
diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c
index 33e7b2e..e41b1ca 100644
--- a/plat/arm/css/common/css_bl2_setup.c
+++ b/plat/arm/css/common/css_bl2_setup.c
@@ -14,21 +14,13 @@
#include "../drivers/scp/css_scp.h"
/* Weak definition may be overridden in specific CSS based platform */
-#if LOAD_IMAGE_V2
#pragma weak plat_arm_bl2_handle_scp_bl2
-#else
-#pragma weak bl2_plat_handle_scp_bl2
-#endif
/*******************************************************************************
* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
* Return 0 on success, -1 otherwise.
******************************************************************************/
-#if LOAD_IMAGE_V2
int plat_arm_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#else
-int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#endif
{
int ret;
diff --git a/plat/arm/css/sgi/include/platform_def.h b/plat/arm/css/sgi/include/platform_def.h
index c645d10..b87bded 100644
--- a/plat/arm/css/sgi/include/platform_def.h
+++ b/plat/arm/css/sgi/include/platform_def.h
@@ -26,29 +26,65 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER * \
CSS_SGI_MAX_PE_PER_CPU)
-#if ARM_BOARD_OPTIMISE_MEM
-
-#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES 6
-# define MAX_XLAT_TABLES 4
-#else
-# define PLAT_ARM_MMAP_ENTRIES 10
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if defined(IMAGE_BL31)
+# if ENABLE_SPM
+# define PLAT_ARM_MMAP_ENTRIES 9
+# define MAX_XLAT_TABLES 7
+# define PLAT_SP_IMAGE_MMAP_REGIONS 7
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
+# else
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 5
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 5
+#else
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
#endif
-#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+
+/*
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+ */
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
#else
-# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
#endif
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0xC000
+# define PLAT_ARM_MAX_BL2_SIZE 0x11000
#endif
-#endif /* ARM_BOARD_OPTIMISE_MEM */
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of
+ * BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
#define PLAT_ARM_NSTIMER_FRAME_ID 0
@@ -62,11 +98,6 @@
#define PLAT_MAX_PWR_LVL U(1)
-#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \
- CSS_IRQ_MHU
-
-#define PLAT_ARM_G0_IRQS ARM_G0_IRQS
-
#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
diff --git a/plat/arm/css/sgi/include/sgi_plat_config.h b/plat/arm/css/sgi/include/sgi_plat_config.h
index c9ff1fe..9b29d74 100644
--- a/plat/arm/css/sgi/include/sgi_plat_config.h
+++ b/plat/arm/css/sgi/include/sgi_plat_config.h
@@ -7,7 +7,6 @@
#ifndef __SGI_PLAT_CONFIG_H__
#define __SGI_PLAT_CONFIG_H__
-#include <arm_gic.h>
#include <ccn.h>
#include <gicv3.h>
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 74d255c..28f97b1 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -6,8 +6,6 @@
CSS_USE_SCMI_SDS_DRIVER := 1
-ENABLE_PLAT_COMPAT := 0
-
CSS_ENT_BASE := plat/arm/css/sgi
RAS_EXTENSION := 0
diff --git a/plat/arm/css/sgi/sgi_image_load.c b/plat/arm/css/sgi/sgi_image_load.c
index dda5e96..09403f8 100644
--- a/plat/arm/css/sgi/sgi_image_load.c
+++ b/plat/arm/css/sgi/sgi_image_load.c
@@ -39,10 +39,15 @@
platform_name = (char *)fdt_getprop(fdt, 0, "compatible", NULL);
+ if (platform_name == NULL) {
+ ERROR("Invalid HW_CONFIG DTB passed\n");
+ return -1;
+ }
+
if (strcmp(platform_name, "arm,sgi575") == 0) {
platid = mmio_read_32(SSC_VERSION);
} else {
- WARN("Invalid platform \n");
+ WARN("Invalid platform\n");
return -1;
}
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index 0a7e319..710430b 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -65,7 +65,7 @@
#if ENABLE_SPM
ARM_SP_IMAGE_MMAP,
#endif
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 && !BL2_AT_EL3
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
{0}
@@ -148,7 +148,7 @@
}
#endif /* ENABLE_SPM && defined(IMAGE_BL31) */
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
assert(heap_addr != NULL);
diff --git a/plat/arm/css/sgm/include/sgm_base_platform_def.h b/plat/arm/css/sgm/include/sgm_base_platform_def.h
index 2498430..7d35bd5 100644
--- a/plat/arm/css/sgm/include/sgm_base_platform_def.h
+++ b/plat/arm/css/sgm/include/sgm_base_platform_def.h
@@ -152,61 +152,39 @@
*/
/*
- * If ARM_BOARD_OPTIMISE_MEM=0 then use the default, unoptimised values
- * defined for ARM development platforms.
- */
-#if ARM_BOARD_OPTIMISE_MEM
-/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
-#if IMAGE_BL1
-# if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MMAP_ENTRIES 7
-# else
-# define PLAT_ARM_MMAP_ENTRIES 6
-# endif /* TRUSTED_BOARD_BOOT */
-#elif IMAGE_BL2
-# define PLAT_ARM_MMAP_ENTRIES 8
-#elif IMAGE_BL2U
-# define PLAT_ARM_MMAP_ENTRIES 4
-#elif IMAGE_BL31
-# define PLAT_ARM_MMAP_ENTRIES 6
-#elif IMAGE_BL32
-# define PLAT_ARM_MMAP_ENTRIES 5
+#if defined(IMAGE_BL31)
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 5
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 5
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 5
+#else
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
#endif
/*
- * Platform specific page table and MMU setup constants
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
*/
-#if IMAGE_BL1
-# if TRUSTED_BOARD_BOOT
-# define MAX_XLAT_TABLES 4
-# else
-# define MAX_XLAT_TABLES 3
-#endif
-#elif IMAGE_BL2
-# define MAX_XLAT_TABLES 4
-#elif IMAGE_BL2U
-# define MAX_XLAT_TABLES 4
-#elif IMAGE_BL31
-# define MAX_XLAT_TABLES 2
-#elif IMAGE_BL32
-# if ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
-# define MAX_XLAT_TABLES 3
-# else
-# define MAX_XLAT_TABLES 2
-# endif
-#endif
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
/*
- * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
- * plus a little space for growth.
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
*/
-#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
#else
-# define PLAT_ARM_MAX_BL1_RW_SIZE 0x7000
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
#endif
/*
@@ -216,10 +194,15 @@
#if TRUSTED_BOARD_BOOT
# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0xD000
+# define PLAT_ARM_MAX_BL2_SIZE 0x11000
#endif
-#endif /* ARM_BOARD_OPTIMISE_MEM */
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of
+ * BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
/*******************************************************************************
* Memprotect definitions
diff --git a/plat/arm/css/sgm/include/sgm_plat_config.h b/plat/arm/css/sgm/include/sgm_plat_config.h
index b171d9a..75abeff 100644
--- a/plat/arm/css/sgm/include/sgm_plat_config.h
+++ b/plat/arm/css/sgm/include/sgm_plat_config.h
@@ -7,7 +7,6 @@
#ifndef __SGM_PLAT_CONFIG_H__
#define __SGM_PLAT_CONFIG_H__
-#include <arm_gic.h>
#include <ccn.h>
#include <gicv3.h>
diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk
index 6a3caba..b10e14c 100644
--- a/plat/arm/css/sgm/sgm-common.mk
+++ b/plat/arm/css/sgm/sgm-common.mk
@@ -48,9 +48,6 @@
# sgm uses CCI-500 as Cache Coherent Interconnect
ARM_CCI_PRODUCT_ID := 500
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
# System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1
diff --git a/plat/arm/css/sgm/sgm_mmap_config.c b/plat/arm/css/sgm/sgm_mmap_config.c
index 8a4a8ab..0f04109 100644
--- a/plat/arm/css/sgm/sgm_mmap_config.c
+++ b/plat/arm/css/sgm/sgm_mmap_config.c
@@ -43,7 +43,7 @@
#ifdef SPD_opteed
ARM_OPTEE_PAGEABLE_LOAD_MEM,
#endif
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2 && !BL2_AT_EL3
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
{0}
diff --git a/plat/arm/css/sgm/sgm_plat_config.c b/plat/arm/css/sgm/sgm_plat_config.c
index 97b16a8..e977e61 100644
--- a/plat/arm/css/sgm/sgm_plat_config.c
+++ b/plat/arm/css/sgm/sgm_plat_config.c
@@ -68,7 +68,7 @@
return css_plat_info;
}
-#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
+#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
assert(heap_addr != NULL);
diff --git a/plat/common/aarch32/plat_sp_min_common.c b/plat/common/aarch32/plat_sp_min_common.c
index 67ae817..a9a92c7 100644
--- a/plat/common/aarch32/plat_sp_min_common.c
+++ b/plat/common/aarch32/plat_sp_min_common.c
@@ -23,14 +23,3 @@
*/
console_uninit();
}
-
-#if !ERROR_DEPRECATED
-
-#pragma weak sp_min_early_platform_setup2
-
-void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- sp_min_early_platform_setup((void *)arg0, (void *)arg1);
-}
-#endif
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 5f2972c..e6f5f20 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -19,10 +19,6 @@
* platforms but may also be overridden by a platform if required.
*/
#pragma weak bl31_plat_runtime_setup
-#if !ERROR_DEPRECATED
-#pragma weak plat_get_syscnt_freq2
-#pragma weak bl31_early_platform_setup2
-#endif /* ERROR_DEPRECATED */
#if SDEI_SUPPORT
#pragma weak plat_sdei_handle_masked_trigger
@@ -40,7 +36,6 @@
#endif
}
-#if !ENABLE_PLAT_COMPAT
/*
* Helper function for platform_get_pos() when platform compatibility is
* disabled. This is to enable SPDs using the older platform API to continue
@@ -52,33 +47,6 @@
assert(idx >= 0);
return idx;
}
-#endif
-
-
-#if !ERROR_DEPRECATED
-unsigned int plat_get_syscnt_freq2(void)
-{
- WARN("plat_get_syscnt_freq() is deprecated\n");
- WARN("Please define plat_get_syscnt_freq2()\n");
- /*
- * Suppress deprecated declaration warning in compatibility function
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
- unsigned long long freq = plat_get_syscnt_freq();
-#pragma GCC diagnostic pop
-
- assert(freq >> 32 == 0);
-
- return (unsigned int)freq;
-}
-
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- bl31_early_platform_setup((void *) arg0, (void *)arg1);
-}
-#endif /* ERROR_DEPRECATED */
#if SDEI_SUPPORT
/*
diff --git a/plat/common/aarch64/plat_psci_common.c b/plat/common/aarch64/plat_psci_common.c
deleted file mode 100644
index 35afcdb..0000000
--- a/plat/common/aarch64/plat_psci_common.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#if !ERROR_DEPRECATED
-#include "../plat_psci_common.c"
-#endif
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index a5d26c0..7214588 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -24,33 +24,10 @@
.weak plat_handle_double_fault
.weak plat_handle_el3_ea
-#if !ENABLE_PLAT_COMPAT
.globl platform_get_core_pos
#define MPIDR_RES_BIT_MASK 0xff000000
- /* ------------------------------------------------------------------
- * int platform_get_core_pos(int mpidr)
- * Returns the CPU index of the CPU specified by mpidr. This is
- * defined when platform compatibility is disabled to enable Trusted
- * Firmware components like SPD using the old platform API to work.
- * This API is deprecated and it assumes that the mpidr specified is
- * that of a valid and present CPU. Instead, plat_my_core_pos()
- * should be used for CPU index of the current CPU and
- * plat_core_pos_by_mpidr() should be used for CPU index of a
- * CPU specified by its mpidr.
- * ------------------------------------------------------------------
- */
-func_deprecated platform_get_core_pos
- bic x0, x0, #MPIDR_RES_BIT_MASK
- mrs x1, mpidr_el1
- bic x1, x1, #MPIDR_RES_BIT_MASK
- cmp x0, x1
- beq plat_my_core_pos
- b platform_core_pos_helper
-endfunc_deprecated platform_get_core_pos
-#endif
-
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
diff --git a/plat/common/aarch64/platform_mp_stack.S b/plat/common/aarch64/platform_mp_stack.S
index 10323bf..f1cc6be 100644
--- a/plat/common/aarch64/platform_mp_stack.S
+++ b/plat/common/aarch64/platform_mp_stack.S
@@ -10,81 +10,11 @@
#include <platform_def.h>
.local platform_normal_stacks
-#if ENABLE_PLAT_COMPAT
- .globl plat_get_my_stack
- .globl plat_set_my_stack
- .weak platform_get_stack
- .weak platform_set_stack
-#else
.weak plat_get_my_stack
.weak plat_set_my_stack
.globl platform_get_stack
.globl platform_set_stack
-#endif /* __ENABLE_PLAT_COMPAT__ */
-#if ENABLE_PLAT_COMPAT
- /* ---------------------------------------------------------------------
- * When the compatility layer is enabled, the new platform APIs
- * viz plat_get_my_stack() and plat_set_my_stack() need to be
- * defined using the previous APIs platform_get_stack() and
- * platform_set_stack(). Also we need to provide weak definitions
- * of platform_get_stack() and platform_set_stack() for the platforms
- * to reuse.
- * --------------------------------------------------------------------
- */
-
- /* -----------------------------------------------------
- * unsigned long plat_get_my_stack ()
- *
- * For the current CPU, this function returns the stack
- * pointer for a stack allocated in device memory.
- * -----------------------------------------------------
- */
-func plat_get_my_stack
- mrs x0, mpidr_el1
- b platform_get_stack
-endfunc plat_get_my_stack
-
- /* -----------------------------------------------------
- * void plat_set_my_stack ()
- *
- * For the current CPU, this function sets the stack
- * pointer to a stack allocated in normal memory.
- * -----------------------------------------------------
- */
-func plat_set_my_stack
- mrs x0, mpidr_el1
- b platform_set_stack
-endfunc plat_set_my_stack
-
- /* -----------------------------------------------------
- * unsigned long platform_get_stack (unsigned long mpidr)
- *
- * For a given CPU, this function returns the stack
- * pointer for a stack allocated in device memory.
- * -----------------------------------------------------
- */
-func platform_get_stack
- mov x10, x30 // lr
- get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE
- ret x10
-endfunc platform_get_stack
-
- /* -----------------------------------------------------
- * void platform_set_stack (unsigned long mpidr)
- *
- * For a given CPU, this function sets the stack pointer
- * to a stack allocated in normal memory.
- * -----------------------------------------------------
- */
-func platform_set_stack
- mov x9, x30 // lr
- bl platform_get_stack
- mov sp, x0
- ret x9
-endfunc platform_set_stack
-
-#else
/* ---------------------------------------------------------------------
* When the compatility layer is disabled, the new platform APIs
* viz plat_get_my_stack() and plat_set_my_stack() are
@@ -95,46 +25,8 @@
* old platform APIs to continue to work.
* --------------------------------------------------------------------
*/
-
- /* -------------------------------------------------------
- * unsigned long platform_get_stack (unsigned long mpidr)
- *
- * For the current CPU, this function returns the stack
- * pointer for a stack allocated in device memory. The
- * 'mpidr' should correspond to that of the current CPU.
- * This function is deprecated and plat_get_my_stack()
- * should be used instead.
- * -------------------------------------------------------
- */
-func_deprecated platform_get_stack
-#if ENABLE_ASSERTIONS
- mrs x1, mpidr_el1
- cmp x0, x1
- ASM_ASSERT(eq)
-#endif
- b plat_get_my_stack
-endfunc_deprecated platform_get_stack
/* -----------------------------------------------------
- * void platform_set_stack (unsigned long mpidr)
- *
- * For the current CPU, this function sets the stack pointer
- * to a stack allocated in normal memory. The
- * 'mpidr' should correspond to that of the current CPU.
- * This function is deprecated and plat_get_my_stack()
- * should be used instead.
- * -----------------------------------------------------
- */
-func_deprecated platform_set_stack
-#if ENABLE_ASSERTIONS
- mrs x1, mpidr_el1
- cmp x0, x1
- ASM_ASSERT(eq)
-#endif
- b plat_set_my_stack
-endfunc_deprecated platform_set_stack
-
- /* -----------------------------------------------------
* uintptr_t plat_get_my_stack ()
*
* For the current CPU, this function returns the stack
@@ -161,8 +53,6 @@
ret x9
endfunc plat_set_my_stack
-#endif /*__ENABLE_PLAT_COMPAT__*/
-
/* -----------------------------------------------------
* Per-cpu stacks in normal memory. Each cpu gets a
* stack of PLATFORM_STACK_SIZE bytes.
diff --git a/plat/common/aarch64/platform_up_stack.S b/plat/common/aarch64/platform_up_stack.S
index a99a7cc..0ff6930 100644
--- a/plat/common/aarch64/platform_up_stack.S
+++ b/plat/common/aarch64/platform_up_stack.S
@@ -43,32 +43,6 @@
endfunc plat_set_my_stack
/* -----------------------------------------------------
- * unsigned long platform_get_stack ()
- *
- * For cold-boot BL images, only the primary CPU needs a
- * stack. This function returns the stack pointer for a
- * stack allocated in device memory. This function
- * is deprecated.
- * -----------------------------------------------------
- */
-func_deprecated platform_get_stack
- b plat_get_my_stack
-endfunc_deprecated platform_get_stack
-
- /* -----------------------------------------------------
- * void platform_set_stack ()
- *
- * For cold-boot BL images, only the primary CPU needs a
- * stack. This function sets the stack pointer to a stack
- * allocated in normal memory.This function is
- * deprecated.
- * -----------------------------------------------------
- */
-func_deprecated platform_set_stack
- b plat_set_my_stack
-endfunc_deprecated platform_set_stack
-
- /* -----------------------------------------------------
* Single cpu stack in normal memory.
* Used for C code during boot, PLATFORM_STACK_SIZE bytes
* are allocated
diff --git a/plat/common/plat_bl1_common.c b/plat/common/plat_bl1_common.c
index 6777979..824f9e5 100644
--- a/plat/common/plat_bl1_common.c
+++ b/plat/common/plat_bl1_common.c
@@ -104,18 +104,9 @@
* to BL2. BL2 will read the memory layout before using its
* memory for other purposes.
*/
-#if LOAD_IMAGE_V2
bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
-#else
- bl2_tzram_layout = (meminfo_t *) round_up(bl1_tzram_layout->free_base,
- sizeof(uint64_t));
-#endif /* LOAD_IMAGE_V2 */
-#if !ERROR_DEPRECATED
- bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
-#else
bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
-#endif
ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c
index 95d73e3..264d518 100644
--- a/plat/common/plat_bl_common.c
+++ b/plat/common/plat_bl_common.c
@@ -40,7 +40,6 @@
{
}
-#if LOAD_IMAGE_V2
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
return 0;
@@ -50,28 +49,12 @@
{
return 0;
}
-#endif
int plat_try_next_boot_source(void)
{
return 0;
}
-#if !ERROR_DEPRECATED
-#pragma weak bl2_early_platform_setup2
-
-/*
- * The following platform API implementation that allow compatibility for
- * the older platform APIs.
- */
-void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- bl2_early_platform_setup((void *)arg1);
-}
-#endif
-
-
#if TRUSTED_BOARD_BOOT
/*
* The following default implementation of the function simply returns the
diff --git a/plat/common/plat_gic.c b/plat/common/plat_gic.c
deleted file mode 100644
index 5363c92..0000000
--- a/plat/common/plat_gic.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#include <arm_gic.h>
-
-/*
- * The following platform GIC functions are weakly defined. They
- * provide typical implementations that may be re-used by multiple
- * platforms but may also be overridden by a platform if required.
- */
-#pragma weak plat_ic_get_pending_interrupt_id
-#pragma weak plat_ic_get_pending_interrupt_type
-#pragma weak plat_ic_acknowledge_interrupt
-#pragma weak plat_ic_get_interrupt_type
-#pragma weak plat_ic_end_of_interrupt
-#pragma weak plat_interrupt_type_to_line
-
-uint32_t plat_ic_get_pending_interrupt_id(void)
-{
- return arm_gic_get_pending_interrupt_id();
-}
-
-uint32_t plat_ic_get_pending_interrupt_type(void)
-{
- return arm_gic_get_pending_interrupt_type();
-}
-
-uint32_t plat_ic_acknowledge_interrupt(void)
-{
- return arm_gic_acknowledge_interrupt();
-}
-
-uint32_t plat_ic_get_interrupt_type(uint32_t id)
-{
- return arm_gic_get_interrupt_type(id);
-}
-
-void plat_ic_end_of_interrupt(uint32_t id)
-{
- arm_gic_end_of_interrupt(id);
-}
-
-uint32_t plat_interrupt_type_to_line(uint32_t type,
- uint32_t security_state)
-{
- return arm_gic_interrupt_type_to_line(type, security_state);
-}
diff --git a/plat/compat/aarch64/plat_helpers_compat.S b/plat/compat/aarch64/plat_helpers_compat.S
deleted file mode 100644
index 0c5551b..0000000
--- a/plat/compat/aarch64/plat_helpers_compat.S
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <platform_def.h>
-
- .globl plat_my_core_pos
- .globl plat_is_my_cpu_primary
- .globl plat_get_my_entrypoint
- .weak platform_get_core_pos
-
- /* -----------------------------------------------------
- * Compatibility wrappers for new platform APIs.
- * -----------------------------------------------------
- */
-func plat_my_core_pos
- mrs x0, mpidr_el1
- b platform_get_core_pos
-endfunc plat_my_core_pos
-
-func plat_is_my_cpu_primary
- mrs x0, mpidr_el1
- b platform_is_primary_cpu
-endfunc plat_is_my_cpu_primary
-
-func plat_get_my_entrypoint
- mrs x0, mpidr_el1
- b platform_get_entrypoint
-endfunc plat_get_my_entrypoint
-
- /* -----------------------------------------------------
- * int platform_get_core_pos(int mpidr);
- * With this function: CorePos = (ClusterId * 4) +
- * CoreId
- * -----------------------------------------------------
- */
-func platform_get_core_pos
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- add x0, x1, x0, LSR #6
- ret
-endfunc platform_get_core_pos
diff --git a/plat/compat/plat_compat.mk b/plat/compat/plat_compat.mk
deleted file mode 100644
index f1867da..0000000
--- a/plat/compat/plat_compat.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${PSCI_EXTENDED_STATE_ID}, 1)
- $(error "PSCI Compatibility mode can be enabled only if \
- PSCI_EXTENDED_STATE_ID is not set")
-endif
-
-ifneq (${ARCH}, aarch64)
- $(error "PSCI Compatibility mode is only supported for AArch64 platforms")
-endif
-
-PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S
-
-BL31_SOURCES += plat/common/plat_psci_common.c \
- plat/compat/plat_pm_compat.c \
- plat/compat/plat_topology_compat.c
-
-# Do not enable SVE
-ENABLE_SVE_FOR_NS := 0
diff --git a/plat/compat/plat_pm_compat.c b/plat/compat/plat_pm_compat.c
deleted file mode 100644
index 6e40ad6..0000000
--- a/plat/compat/plat_pm_compat.c
+++ /dev/null
@@ -1,313 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <errno.h>
-#include <platform.h>
-#include <psci.h>
-
-/*
- * The platform hooks exported by the platform using the earlier version of
- * platform interface
- */
-const plat_pm_ops_t *pm_ops;
-
-/*
- * The hooks exported by the compatibility layer
- */
-static plat_psci_ops_t compat_psci_ops;
-
-/*
- * The secure entry point to be used on warm reset.
- */
-static unsigned long secure_entrypoint;
-
-/*
- * This array stores the 'power_state' requests of each CPU during
- * CPU_SUSPEND and SYSTEM_SUSPEND to support querying of state-ID
- * by the platform.
- */
-unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT];
-
-/*******************************************************************************
- * The PSCI compatibility helper to parse the power state and populate the
- * 'pwr_domain_state' for each power level. It is assumed that, when in
- * compatibility mode, the PSCI generic layer need to know only whether the
- * affinity level will be OFF or in RETENTION and if the platform supports
- * multiple power down and retention states, it will be taken care within
- * the platform layer.
- ******************************************************************************/
-static int parse_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- int i;
- int pstate = psci_get_pstate_type(power_state);
- int aff_lvl = psci_get_pstate_pwrlvl(power_state);
-
- if (aff_lvl > PLATFORM_MAX_AFFLVL)
- return PSCI_E_INVALID_PARAMS;
-
- /* Sanity check the requested state */
- if (pstate == PSTATE_TYPE_STANDBY) {
- /*
- * Set the CPU local state as retention and ignore the higher
- * levels. This allows the generic PSCI layer to invoke
- * plat_psci_ops 'cpu_standby' hook and the compatibility
- * layer invokes the 'affinst_standby' handler with the
- * correct power_state parameter thus preserving the correct
- * behavior.
- */
- req_state->pwr_domain_state[0] =
- PLAT_MAX_RET_STATE;
- } else {
- for (i = 0; i <= aff_lvl; i++)
- req_state->pwr_domain_state[i] =
- PLAT_MAX_OFF_STATE;
- }
-
- return PSCI_E_SUCCESS;
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper to set the 'power_state' in
- * psci_power_state_compat[] at index corresponding to the current core.
- ******************************************************************************/
-static void set_psci_power_state_compat(unsigned int power_state)
-{
- unsigned int my_core_pos = plat_my_core_pos();
-
- psci_power_state_compat[my_core_pos] = power_state;
- flush_dcache_range((uintptr_t) &psci_power_state_compat[my_core_pos],
- sizeof(psci_power_state_compat[my_core_pos]));
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'validate_power_state'
- * hook.
- ******************************************************************************/
-static int validate_power_state_compat(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- int rc;
- assert(req_state);
-
- if (pm_ops->validate_power_state) {
- rc = pm_ops->validate_power_state(power_state);
- if (rc != PSCI_E_SUCCESS)
- return rc;
- }
-
- /* Store the 'power_state' parameter for the current CPU. */
- set_psci_power_state_compat(power_state);
-
- return parse_power_state(power_state, req_state);
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t
- * 'get_sys_suspend_power_state' hook.
- ******************************************************************************/
-void get_sys_suspend_power_state_compat(psci_power_state_t *req_state)
-{
- unsigned int power_state;
- assert(req_state);
-
- power_state = pm_ops->get_sys_suspend_power_state();
-
- /* Store the 'power_state' parameter for the current CPU. */
- set_psci_power_state_compat(power_state);
-
- if (parse_power_state(power_state, req_state) != PSCI_E_SUCCESS)
- assert(0);
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'validate_ns_entrypoint'
- * hook.
- ******************************************************************************/
-static int validate_ns_entrypoint_compat(uintptr_t ns_entrypoint)
-{
- return pm_ops->validate_ns_entrypoint(ns_entrypoint);
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'affinst_standby' hook.
- ******************************************************************************/
-static void cpu_standby_compat(plat_local_state_t cpu_state)
-{
- unsigned int powerstate = psci_get_suspend_powerstate();
-
- assert(powerstate != PSCI_INVALID_DATA);
-
- pm_ops->affinst_standby(powerstate);
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'affinst_on' hook.
- ******************************************************************************/
-static int pwr_domain_on_compat(u_register_t mpidr)
-{
- int level, rc;
-
- /*
- * The new PSCI framework does not hold the locks for higher level
- * power domain nodes when this hook is invoked. Hence figuring out the
- * target state of the parent power domains does not make much sense.
- * Hence we hard-code the state as PSCI_STATE_OFF for all the levels.
- * We expect the platform to perform the necessary CPU_ON operations
- * when the 'affinst_on' is invoked only for level 0.
- */
- for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) {
- rc = pm_ops->affinst_on((unsigned long)mpidr, secure_entrypoint,
- level, PSCI_STATE_OFF);
- if (rc != PSCI_E_SUCCESS)
- break;
- }
-
- return rc;
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'affinst_off' hook.
- ******************************************************************************/
-static void pwr_domain_off_compat(const psci_power_state_t *target_state)
-{
- int level;
- unsigned int plat_state;
-
- for (level = 0; level <= PLATFORM_MAX_AFFLVL; level++) {
- plat_state = (is_local_state_run(
- target_state->pwr_domain_state[level]) ?
- PSCI_STATE_ON : PSCI_STATE_OFF);
- pm_ops->affinst_off(level, plat_state);
- }
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'affinst_suspend' hook.
- ******************************************************************************/
-static void pwr_domain_suspend_compat(const psci_power_state_t *target_state)
-{
- int level;
- unsigned int plat_state;
-
- for (level = 0; level <= psci_get_suspend_afflvl(); level++) {
- plat_state = (is_local_state_run(
- target_state->pwr_domain_state[level]) ?
- PSCI_STATE_ON : PSCI_STATE_OFF);
- pm_ops->affinst_suspend(secure_entrypoint, level, plat_state);
- }
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'affinst_on_finish'
- * hook.
- ******************************************************************************/
-static void pwr_domain_on_finish_compat(const psci_power_state_t *target_state)
-{
- int level;
- unsigned int plat_state;
-
- for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) {
- plat_state = (is_local_state_run(
- target_state->pwr_domain_state[level]) ?
- PSCI_STATE_ON : PSCI_STATE_OFF);
- pm_ops->affinst_on_finish(level, plat_state);
- }
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t
- * 'affinst_suspend_finish' hook.
- ******************************************************************************/
-static void pwr_domain_suspend_finish_compat(
- const psci_power_state_t *target_state)
-{
- int level;
- unsigned int plat_state;
-
- for (level = psci_get_suspend_afflvl(); level >= 0; level--) {
- plat_state = (is_local_state_run(
- target_state->pwr_domain_state[level]) ?
- PSCI_STATE_ON : PSCI_STATE_OFF);
- pm_ops->affinst_suspend_finish(level, plat_state);
- }
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'system_off' hook.
- ******************************************************************************/
-static void __dead2 system_off_compat(void)
-{
- pm_ops->system_off();
-}
-
-/*******************************************************************************
- * The PSCI compatibility helper for plat_pm_ops_t 'system_reset' hook.
- ******************************************************************************/
-static void __dead2 system_reset_compat(void)
-{
- pm_ops->system_reset();
-}
-
-/*******************************************************************************
- * Export the compatibility compat_psci_ops. The assumption made is that the
- * power domains correspond to affinity instances on the platform.
- ******************************************************************************/
-int plat_setup_psci_ops(uintptr_t sec_entrypoint,
- const plat_psci_ops_t **psci_ops)
-{
- platform_setup_pm(&pm_ops);
-
- secure_entrypoint = (unsigned long) sec_entrypoint;
-
- /*
- * It is compulsory for the platform ports using the new porting
- * interface to export a hook to validate the power state parameter
- */
- compat_psci_ops.validate_power_state = validate_power_state_compat;
-
- /*
- * Populate the compatibility plat_psci_ops_t hooks if available
- */
- if (pm_ops->validate_ns_entrypoint)
- compat_psci_ops.validate_ns_entrypoint =
- validate_ns_entrypoint_compat;
-
- if (pm_ops->affinst_standby)
- compat_psci_ops.cpu_standby = cpu_standby_compat;
-
- if (pm_ops->affinst_on)
- compat_psci_ops.pwr_domain_on = pwr_domain_on_compat;
-
- if (pm_ops->affinst_off)
- compat_psci_ops.pwr_domain_off = pwr_domain_off_compat;
-
- if (pm_ops->affinst_suspend)
- compat_psci_ops.pwr_domain_suspend = pwr_domain_suspend_compat;
-
- if (pm_ops->affinst_on_finish)
- compat_psci_ops.pwr_domain_on_finish =
- pwr_domain_on_finish_compat;
-
- if (pm_ops->affinst_suspend_finish)
- compat_psci_ops.pwr_domain_suspend_finish =
- pwr_domain_suspend_finish_compat;
-
- if (pm_ops->system_off)
- compat_psci_ops.system_off = system_off_compat;
-
- if (pm_ops->system_reset)
- compat_psci_ops.system_reset = system_reset_compat;
-
- if (pm_ops->get_sys_suspend_power_state)
- compat_psci_ops.get_sys_suspend_power_state =
- get_sys_suspend_power_state_compat;
-
- *psci_ops = &compat_psci_ops;
- return 0;
-}
diff --git a/plat/compat/plat_topology_compat.c b/plat/compat/plat_topology_compat.c
deleted file mode 100644
index 48d565c..0000000
--- a/plat/compat/plat_topology_compat.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <psci.h>
-
-/* The power domain tree descriptor */
-static unsigned char power_domain_tree_desc
- [PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1];
-
-/*******************************************************************************
- * Simple routine to set the id of an affinity instance at a given level
- * in the mpidr. The assumption is that the affinity level and the power
- * domain level are the same.
- ******************************************************************************/
-unsigned long mpidr_set_aff_inst(unsigned long mpidr,
- unsigned char aff_inst,
- int aff_lvl)
-{
- unsigned long aff_shift;
-
- assert(aff_lvl <= MPIDR_AFFLVL3);
-
- /*
- * Decide the number of bits to shift by depending upon
- * the power level
- */
- aff_shift = get_afflvl_shift(aff_lvl);
-
- /* Clear the existing power instance & set the new one*/
- mpidr &= ~((unsigned long)MPIDR_AFFLVL_MASK << aff_shift);
- mpidr |= (unsigned long)aff_inst << aff_shift;
-
- return mpidr;
-}
-
-/******************************************************************************
- * This function uses insertion sort to sort a given list of mpidr's in the
- * ascending order of the index returned by platform_get_core_pos.
- *****************************************************************************/
-void sort_mpidr_by_cpu_idx(unsigned int aff_count, unsigned long mpidr_list[])
-{
- int i, j;
- unsigned long temp_mpidr;
-
- for (i = 1; i < aff_count; i++) {
- temp_mpidr = mpidr_list[i];
-
- for (j = i;
- j > 0 &&
- platform_get_core_pos(mpidr_list[j-1]) >
- platform_get_core_pos(temp_mpidr);
- j--)
- mpidr_list[j] = mpidr_list[j-1];
-
- mpidr_list[j] = temp_mpidr;
- }
-}
-
-/*******************************************************************************
- * The compatibility routine to construct the power domain tree description.
- * The assumption made is that the power domains correspond to affinity
- * instances on the platform. This routine's aim is to traverse to the target
- * affinity level and populate the number of siblings at that level in
- * 'power_domain_tree_desc' array. It uses the current affinity level to keep
- * track of how many levels from the root of the tree have been traversed.
- * If the current affinity level != target affinity level, then the platform
- * is asked to return the number of children that each affinity instance has
- * at the current affinity level. Traversal is then done for each child at the
- * next lower level i.e. current affinity level - 1.
- *
- * The power domain description needs to be constructed in such a way that
- * affinity instances containing CPUs with lower cpu indices need to be
- * described first. Hence when traversing the power domain levels, the list
- * of mpidrs at that power domain level is sorted in the ascending order of CPU
- * indices before the lower levels are recursively described.
- *
- * CAUTION: This routine assumes that affinity instance ids are allocated in a
- * monotonically increasing manner at each affinity level in a mpidr starting
- * from 0. If the platform breaks this assumption then this code will have to
- * be reworked accordingly.
- ******************************************************************************/
-static unsigned int init_pwr_domain_tree_desc(unsigned long mpidr,
- unsigned int affmap_idx,
- unsigned int cur_afflvl,
- unsigned int tgt_afflvl)
-{
- unsigned int ctr, aff_count;
-
- /*
- * Temporary list to hold the MPIDR list at a particular power domain
- * level so as to sort them.
- */
- unsigned long mpidr_list[PLATFORM_CORE_COUNT];
-
- assert(cur_afflvl >= tgt_afflvl);
-
- /*
- * Find the number of siblings at the current power level &
- * assert if there are none 'cause then we have been invoked with
- * an invalid mpidr.
- */
- aff_count = plat_get_aff_count(cur_afflvl, mpidr);
- assert(aff_count);
-
- if (tgt_afflvl < cur_afflvl) {
- for (ctr = 0; ctr < aff_count; ctr++) {
- mpidr_list[ctr] = mpidr_set_aff_inst(mpidr, ctr,
- cur_afflvl);
- }
-
- /* Need to sort mpidr list according to CPU index */
- sort_mpidr_by_cpu_idx(aff_count, mpidr_list);
- for (ctr = 0; ctr < aff_count; ctr++) {
- affmap_idx = init_pwr_domain_tree_desc(mpidr_list[ctr],
- affmap_idx,
- cur_afflvl - 1,
- tgt_afflvl);
- }
- } else {
- power_domain_tree_desc[affmap_idx++] = aff_count;
- }
- return affmap_idx;
-}
-
-
-/*******************************************************************************
- * This function constructs the topology tree description at runtime
- * and returns it. The assumption made is that the power domains correspond
- * to affinity instances on the platform.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- int afflvl;
- unsigned int affmap_idx;
-
- /*
- * We assume that the platform allocates affinity instance ids from
- * 0 onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0
- */
- affmap_idx = 0;
- for (afflvl = (int) PLATFORM_MAX_AFFLVL;
- afflvl >= (int) MPIDR_AFFLVL0; afflvl--) {
- affmap_idx = init_pwr_domain_tree_desc(FIRST_MPIDR,
- affmap_idx,
- PLATFORM_MAX_AFFLVL,
- (unsigned int) afflvl);
- }
-
- assert(affmap_idx == (PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1));
-
- return power_domain_tree_desc;
-}
-
-/******************************************************************************
- * The compatibility helper function for plat_core_pos_by_mpidr(). It
- * validates the 'mpidr' by making sure that it is within acceptable bounds
- * for the platform and queries the platform layer whether the CPU specified
- * by the mpidr is present or not. If present, it returns the index of the
- * core corresponding to the 'mpidr'. Else it returns -1.
- *****************************************************************************/
-int plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- unsigned long shift, aff_inst;
- int i;
-
- /* Ignore the Reserved bits and U bit in MPIDR */
- mpidr &= MPIDR_AFFINITY_MASK;
-
- /*
- * Check if any affinity field higher than
- * the PLATFORM_MAX_AFFLVL is set.
- */
- shift = get_afflvl_shift(PLATFORM_MAX_AFFLVL + 1);
- if (mpidr >> shift)
- return -1;
-
- for (i = PLATFORM_MAX_AFFLVL; i >= 0; i--) {
- shift = get_afflvl_shift(i);
- aff_inst = ((mpidr &
- ((unsigned long)MPIDR_AFFLVL_MASK << shift)) >> shift);
- if (aff_inst >= plat_get_aff_count(i, mpidr))
- return -1;
- }
-
- if (plat_get_aff_state(0, mpidr) == PSCI_AFF_ABSENT)
- return -1;
-
- return platform_get_core_pos(mpidr);
-}
diff --git a/plat/hisilicon/hikey/aarch64/hikey_common.c b/plat/hisilicon/hikey/aarch64/hikey_common.c
index 658760b..60e4d86 100644
--- a/plat/hisilicon/hikey/aarch64/hikey_common.c
+++ b/plat/hisilicon/hikey/aarch64/hikey_common.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index ec779f4..2fc99a0 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -37,28 +37,6 @@
return &bl1_tzram_layout;
}
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
-
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
-
- /*
- * Cannot remove BL1 RW data from the scope of memory visible to BL2
- * like arm platforms because they overlap in hikey
- */
- bl2_mem_layout->total_base = BL2_BASE;
- bl2_mem_layout->total_size = BL32_SRAM_LIMIT - BL2_BASE;
-
- flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
-}
-
/*
* Perform any BL1 specific platform actions.
*/
diff --git a/plat/hisilicon/hikey/hikey_bl31_setup.c b/plat/hisilicon/hikey/hikey_bl31_setup.c
index a193b5a..525412c 100644
--- a/plat/hisilicon/hikey/hikey_bl31_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl31_setup.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
@@ -17,6 +16,7 @@
#include <hikey_def.h>
#include <hisi_ipc.h>
#include <hisi_pwrc.h>
+#include <interrupt_props.h>
#include <mmio.h>
#include <platform_def.h>
@@ -48,9 +48,11 @@
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
/*
@@ -61,8 +63,8 @@
gicv2_driver_data_t hikey_gic_data = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicc_base = PLAT_ARM_GICC_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
static const int cci_map[] = {
@@ -82,9 +84,13 @@
return NULL;
}
-void bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+ void *from_bl2;
+
+ from_bl2 = (void *) arg0;
+
/* Initialize the console to provide early debug support */
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
diff --git a/plat/hisilicon/hikey/include/plat_macros.S b/plat/hisilicon/hikey/include/plat_macros.S
index 1ad217a..fda0e39 100644
--- a/plat/hisilicon/hikey/include/plat_macros.S
+++ b/plat/hisilicon/hikey/include/plat_macros.S
@@ -8,7 +8,7 @@
#define __PLAT_MACROS_S__
#include <cci.h>
-#include <gic_v2.h>
+#include <gicv2.h>
#include <hi6220.h>
#include <platform_def.h>
@@ -16,8 +16,7 @@
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
- " Offset:\t\t\tvalue\n"
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
diff --git a/plat/hisilicon/hikey/include/platform_def.h b/plat/hisilicon/hikey/include/platform_def.h
index 54be978..f2d358a 100644
--- a/plat/hisilicon/hikey/include/platform_def.h
+++ b/plat/hisilicon/hikey/include/platform_def.h
@@ -52,7 +52,8 @@
/*
* Platform specific page table and MMU setup constants
*/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
#define MAX_XLAT_TABLES 3
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index ccc7296..c8e760d 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -4,9 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-# Enable version2 of image loading
-LOAD_IMAGE_V2 := 1
-
# Non-TF Boot ROM
BL2_AT_EL3 := 1
@@ -45,16 +42,15 @@
$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
endif
-ENABLE_PLAT_COMPAT := 0
-
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Iinclude/drivers/synopsys \
-Iplat/hisilicon/hikey/include
-PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
- lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
+ lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
plat/hisilicon/hikey/aarch64/hikey_common.c
BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
@@ -108,7 +104,7 @@
drivers/arm/sp804/sp804_delay_timer.c \
drivers/delay_timer/delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
- plat/common/aarch64/plat_psci_common.c \
+ plat/common/plat_psci_common.c \
plat/hisilicon/hikey/aarch64/hikey_helpers.S \
plat/hisilicon/hikey/hikey_bl31_setup.c \
plat/hisilicon/hikey/hikey_pm.c \
@@ -127,8 +123,6 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-USE_TBBR_DEFS := 1
-
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
diff --git a/plat/hisilicon/hikey960/aarch64/hikey960_common.c b/plat/hisilicon/hikey960/aarch64/hikey960_common.c
index 67571ff..1ed3eaa 100644
--- a/plat/hisilicon/hikey960/aarch64/hikey960_common.c
+++ b/plat/hisilicon/hikey960/aarch64/hikey960_common.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
diff --git a/plat/hisilicon/hikey960/hikey960_bl1_setup.c b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
index a928576..ea5eb47 100644
--- a/plat/hisilicon/hikey960/hikey960_bl1_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl1_setup.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
@@ -16,6 +15,7 @@
#include <generic_delay_timer.h>
#include <gicv2.h>
#include <hi3660.h>
+#include <interrupt_props.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
@@ -45,16 +45,18 @@
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
const gicv2_driver_data_t hikey960_gic_data = {
.gicd_base = GICD_REG_BASE,
.gicc_base = GICC_REG_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
meminfo_t *bl1_plat_sec_mem_layout(void)
@@ -62,28 +64,6 @@
return &bl1_tzram_layout;
}
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
-
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
-
- /*
- * Cannot remove BL1 RW data from the scope of memory visible to BL2
- * like arm platforms because they overlap in hikey960
- */
- bl2_mem_layout->total_base = BL2_BASE;
- bl2_mem_layout->total_size = NS_BL1U_LIMIT - BL2_BASE;
-
- flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
-}
-
/*
* Perform any BL1 specific platform actions.
*/
diff --git a/plat/hisilicon/hikey960/hikey960_bl31_setup.c b/plat/hisilicon/hikey960/hikey960_bl31_setup.c
index f8921f2..d7164ff 100644
--- a/plat/hisilicon/hikey960/hikey960_bl31_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl31_setup.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
@@ -17,6 +16,7 @@
#include <hi3660.h>
#include <hisi_ipc.h>
#include <interrupt_mgmt.h>
+#include <interrupt_props.h>
#include <platform.h>
#include <platform_def.h>
@@ -49,16 +49,18 @@
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
- IRQ_SEC_PHY_TIMER,
- IRQ_SEC_SGI_0
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
const gicv2_driver_data_t hikey960_gic_data = {
.gicd_base = GICD_REG_BASE,
.gicc_base = GICC_REG_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
static const int cci_map[] = {
@@ -78,10 +80,13 @@
return NULL;
}
-void bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
unsigned int id, uart_base;
+ void *from_bl2;
+
+ from_bl2 = (void *) arg0;
generic_delay_timer_init();
hikey960_read_boardid(&id);
diff --git a/plat/hisilicon/hikey960/include/plat_macros.S b/plat/hisilicon/hikey960/include/plat_macros.S
index 5137f9e..4a2b957 100644
--- a/plat/hisilicon/hikey960/include/plat_macros.S
+++ b/plat/hisilicon/hikey960/include/plat_macros.S
@@ -8,7 +8,7 @@
#define __PLAT_MACROS_S__
#include <cci.h>
-#include <gic_v2.h>
+#include <gicv2.h>
#include <hi3660.h>
#include <platform_def.h>
@@ -16,8 +16,7 @@
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
- .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
- " Offset:\t\t\tvalue\n"
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 40304eb..3717ff8 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -113,7 +113,8 @@
/*
* Platform specific page table and MMU setup constants
*/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32)
#define MAX_XLAT_TABLES 3
diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index 6f3a403..3b37740 100644
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -4,9 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-# Enable version2 of image loading
-LOAD_IMAGE_V2 := 1
-
# Non-TF Boot ROM
BL2_AT_EL3 := 1
@@ -40,17 +37,16 @@
$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
endif
-ENABLE_PLAT_COMPAT := 0
-
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Iplat/hisilicon/hikey960/include
-PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \
+PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- lib/aarch64/xlat_tables.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
plat/hisilicon/hikey960/aarch64/hikey960_common.c \
plat/hisilicon/hikey960/hikey960_boardid.c
@@ -99,7 +95,7 @@
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a73.S \
- plat/common/aarch64/plat_psci_common.c \
+ plat/common/plat_psci_common.c \
plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
plat/hisilicon/hikey960/hikey960_bl31_setup.c \
plat/hisilicon/hikey960/hikey960_pm.c \
@@ -113,8 +109,6 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
-USE_TBBR_DEFS := 1
-
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
diff --git a/plat/hisilicon/poplar/aarch64/platform_common.c b/plat/hisilicon/poplar/aarch64/platform_common.c
index 5498065..d408209 100644
--- a/plat/hisilicon/poplar/aarch64/platform_common.c
+++ b/plat/hisilicon/poplar/aarch64/platform_common.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
@@ -29,24 +28,20 @@
TSP_SEC_MEM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
-#if LOAD_IMAGE_V2
#ifdef SPD_opteed
#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
POPLAR_OPTEE_PAGEABLE_LOAD_BASE, \
POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#endif
-#endif
static const mmap_region_t poplar_mmap[] = {
MAP_DDR,
MAP_DEVICE,
MAP_TSP_MEM,
-#if LOAD_IMAGE_V2
#ifdef SPD_opteed
MAP_OPTEE_PAGEABLE,
#endif
-#endif
{0}
};
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index 6fc4f33..c2adc44 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -25,35 +25,39 @@
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
+static meminfo_t bl2_tzram_layout;
-meminfo_t *bl1_plat_sec_mem_layout(void)
+/*
+ * Cannot use default weak implementation in bl1_main.c because BL1 RW data is
+ * not at the top of the secure memory.
+ */
+int bl1_plat_handle_post_image_load(unsigned int image_id)
{
- return &bl1_tzram_layout;
-}
+ image_desc_t *image_desc;
+ entry_point_info_t *ep_info;
-#if LOAD_IMAGE_V2
-/*******************************************************************************
- * Function that takes a memory layout into which BL2 has been loaded and
- * populates a new memory layout for BL2 that ensures that BL1's data sections
- * resident in secure RAM are not visible to BL2.
- ******************************************************************************/
-void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
- meminfo_t *bl2_mem_layout)
-{
+ if (image_id != BL2_IMAGE_ID)
+ return 0;
+
+ /* Get the image descriptor */
+ image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+ assert(image_desc != NULL);
+
+ /* Get the entry point info */
+ ep_info = &image_desc->ep_info;
+
+ bl2_tzram_layout.total_base = BL2_BASE;
+ bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
- assert(bl1_mem_layout != NULL);
- assert(bl2_mem_layout != NULL);
+ flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
- /*
- * Cannot use default weak implementation in bl1main.c because
- * BL1 RW data is not at the top of bl1_mem_layout
- */
- bl2_mem_layout->total_base = BL2_BASE;
- bl2_mem_layout->total_size = BL32_LIMIT - BL2_BASE;
+ ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
- flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
+ VERBOSE("BL1: BL2 memory layout address = %p\n",
+ (void *)&bl2_tzram_layout);
+
+ return 0;
}
-#endif /* LOAD_IMAGE_V2 */
void bl1_early_platform_setup(void)
{
@@ -64,17 +68,6 @@
bl1_tzram_layout.total_base = BL1_RW_BASE;
bl1_tzram_layout.total_size = BL1_RW_SIZE;
-#if !LOAD_IMAGE_V2
- /* Calculate how much RAM BL1 is using and how much remains free */
- bl1_tzram_layout.free_base = BL1_RW_BASE;
- bl1_tzram_layout.free_size = BL1_RW_SIZE;
-
- reserve_mem(&bl1_tzram_layout.free_base,
- &bl1_tzram_layout.free_size,
- BL1_RAM_BASE,
- BL1_RAM_LIMIT - BL1_RAM_BASE);
-#endif
-
INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
BL1_RAM_LIMIT - BL1_RAM_BASE);
}
@@ -92,8 +85,8 @@
void bl1_platform_setup(void)
{
int i;
- struct mmc_device_info info;
#if !POPLAR_RECOVERY
+ struct mmc_device_info info;
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c
index 041ed4a..a253d3f 100644
--- a/plat/hisilicon/poplar/bl2_plat_setup.c
+++ b/plat/hisilicon/poplar/bl2_plat_setup.c
@@ -32,49 +32,11 @@
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-#if !LOAD_IMAGE_V2
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
- bl31_params_t bl31_params;
- image_info_t bl31_image_info;
- image_info_t bl32_image_info;
- image_info_t bl33_image_info;
- entry_point_info_t bl33_ep_info;
- entry_point_info_t bl32_ep_info;
- entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
- return &bl2_tzram_layout;
-}
-
-#ifdef SCP_BL2_BASE
-void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
-{
- /*
- * This platform has no SCP_BL2 yet
- */
-}
-#endif
-#endif /* LOAD_IMAGE_V2 */
-
/*******************************************************************************
* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
* Return 0 on success, -1 otherwise.
******************************************************************************/
-#if LOAD_IMAGE_V2
int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
-#else
-int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info)
-#endif
{
/*
* This platform has no SCP_BL2 yet
@@ -138,7 +100,6 @@
}
#endif /* AARCH32 */
-#if LOAD_IMAGE_V2
int poplar_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
@@ -210,132 +171,13 @@
return poplar_bl2_handle_post_image_load(image_id);
}
-#else /* LOAD_IMAGE_V2 */
-
-bl31_params_t *bl2_plat_get_bl31_params(void)
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- bl31_params_t *bl2_to_bl31_params = NULL;
-
- /*
- * Initialise the memory for all the arguments that needs to
- * be passed to BL3-1
- */
- memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
-
- /* Assign memory for TF related information */
- bl2_to_bl31_params = &bl31_params_mem.bl31_params;
- SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
- /* Fill BL3-1 related information */
- bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
- PARAM_IMAGE_BINARY, VERSION_1, 0);
-
- /* Fill BL3-2 related information if it exists */
-#ifdef BL32_BASE
- bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
- VERSION_1, 0);
- bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-#endif
-
- /* Fill BL3-3 related information */
- bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
- PARAM_EP, VERSION_1, 0);
-
- /* BL3-3 expects to receive the primary CPU MPID (through x0) */
- bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
- bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
- PARAM_IMAGE_BINARY, VERSION_1, 0);
-
- return bl2_to_bl31_params;
-}
-
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
- bl31_params_mem.bl31_ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL;
-#endif
-
- return &bl31_params_mem.bl31_ep_info;
-}
-
-void bl2_plat_set_bl31_ep_info(image_info_t *image,
- entry_point_info_t *bl31_ep_info)
-{
- SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
- bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
-}
-
-/*******************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On Poplar we only set the security state of the entrypoint
- ******************************************************************************/
-#ifdef BL32_BASE
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
- entry_point_info_t *bl32_ep_info)
-{
- SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
- /*
- * The Secure Payload Dispatcher service is responsible for
- * setting the SPSR prior to entry into the BL32 image.
- */
- bl32_ep_info->spsr = 0;
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
- /*
- * Populate the extents of memory available for loading BL32.
- */
- bl32_meminfo->total_base = BL32_BASE;
- bl32_meminfo->free_base = BL32_BASE;
- bl32_meminfo->total_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
- bl32_meminfo->free_size =
- (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
-}
-#endif /* BL32_BASE */
-
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
- entry_point_info_t *bl33_ep_info)
-{
- SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
- bl33_ep_info->spsr = poplar_get_spsr_for_bl33_entry();
- bl33_ep_info->args.arg2 = image->image_size;
-}
-
-void bl2_plat_flush_bl31_params(void)
-{
- flush_dcache_range((unsigned long)&bl31_params_mem,
- sizeof(bl2_to_bl31_params_mem_t));
-}
-
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
- bl33_meminfo->total_base = DDR_BASE;
- bl33_meminfo->total_size = DDR_SIZE;
- bl33_meminfo->free_base = DDR_BASE;
- bl33_meminfo->free_size = DDR_SIZE;
-}
-#endif /* LOAD_IMAGE_V2 */
-
-void bl2_early_platform_setup(meminfo_t *mem_layout)
-{
+ struct meminfo *mem_layout = (struct meminfo *)arg1;
+#if !POPLAR_RECOVERY
struct mmc_device_info info;
-#if !POPLAR_RECOVERY
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
diff --git a/plat/hisilicon/poplar/bl31_plat_setup.c b/plat/hisilicon/poplar/bl31_plat_setup.c
index ec72acd..b45693f 100644
--- a/plat/hisilicon/poplar/bl31_plat_setup.c
+++ b/plat/hisilicon/poplar/bl31_plat_setup.c
@@ -6,7 +6,6 @@
#include <arch.h>
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl31.h>
#include <bl_common.h>
@@ -67,65 +66,45 @@
* while creating page tables. BL2 has flushed this information to memory, so
* we are guaranteed to pick up good data.
******************************************************************************/
-#if LOAD_IMAGE_V2
-void bl31_early_platform_setup(void *from_bl2,
- void *plat_params_from_bl2)
-#else
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
-#endif
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+ void *from_bl2;
+
+ from_bl2 = (void *) arg0;
+
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
/* Init console for crash report */
plat_crash_console_init();
-#if LOAD_IMAGE_V2
- /*
- * Check params passed from BL2 should not be NULL,
- */
- bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
-
- assert(params_from_bl2 != NULL);
- assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
- assert(params_from_bl2->h.version >= VERSION_2);
-
- bl_params_node_t *bl_params = params_from_bl2->head;
-
- /*
- * Copy BL33 and BL32 (if present), entry point information.
- * They are stored in Secure RAM, in BL2's address space.
- */
- while (bl_params) {
- if (bl_params->image_id == BL32_IMAGE_ID)
- bl32_image_ep_info = *bl_params->ep_info;
-
- if (bl_params->image_id == BL33_IMAGE_ID)
- bl33_image_ep_info = *bl_params->ep_info;
-
- bl_params = bl_params->next_params_info;
- }
-
- if (bl33_image_ep_info.pc == 0)
- panic();
-
-#else /* LOAD_IMAGE_V2 */
-
/*
* Check params passed from BL2 should not be NULL,
*/
+ bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+
assert(params_from_bl2 != NULL);
- assert(params_from_bl2->h.type == PARAM_BL31);
- assert(params_from_bl2->h.version >= VERSION_1);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
/*
- * Copy BL32 (if populated by BL2) and BL33 entry point information.
+ * Copy BL33 and BL32 (if present), entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- if (from_bl2->bl32_ep_info)
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
-#endif /* LOAD_IMAGE_V2 */
+ while (bl_params) {
+ if (bl_params->image_id == BL32_IMAGE_ID)
+ bl32_image_ep_info = *bl_params->ep_info;
+
+ if (bl_params->image_id == BL33_IMAGE_ID)
+ bl33_image_ep_info = *bl_params->ep_info;
+
+ bl_params = bl_params->next_params_info;
+ }
+
+ if (bl33_image_ep_info.pc == 0)
+ panic();
}
void bl31_platform_setup(void)
diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h
index 824ca34..99fd996 100644
--- a/plat/hisilicon/poplar/include/platform_def.h
+++ b/plat/hisilicon/poplar/include/platform_def.h
@@ -88,13 +88,11 @@
#define BL32_DRAM_BASE 0x03000000
#define BL32_DRAM_LIMIT 0x04000000
-#if LOAD_IMAGE_V2
#ifdef SPD_opteed
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */
#endif
-#endif
#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
@@ -122,7 +120,8 @@
#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
/* Page table and MMU setup constants */
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define MAX_XLAT_TABLES (4)
#define MAX_MMAP_REGIONS (16)
diff --git a/plat/hisilicon/poplar/plat_pm.c b/plat/hisilicon/poplar/plat_pm.c
index 3e43d4d..e59cac9 100644
--- a/plat/hisilicon/poplar/plat_pm.c
+++ b/plat/hisilicon/poplar/plat_pm.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
diff --git a/plat/hisilicon/poplar/platform.mk b/plat/hisilicon/poplar/platform.mk
index 3cdbe59..9d2b617 100644
--- a/plat/hisilicon/poplar/platform.mk
+++ b/plat/hisilicon/poplar/platform.mk
@@ -4,9 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-# Enable version2 of image loading
-LOAD_IMAGE_V2 := 1
-
# On Poplar, the TSP can execute from TZC secure area in DRAM.
POPLAR_TSP_RAM_LOCATION ?= dram
ifeq (${POPLAR_TSP_RAM_LOCATION}, dram)
@@ -45,7 +42,6 @@
COLD_BOOT_SINGLE_CPU := 1
PROGRAMMABLE_RESET_ADDRESS := 1
CTX_INCLUDE_FPREGS := 1
-ENABLE_PLAT_COMPAT := 0
ERRATA_A53_855873 := 1
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
@@ -53,9 +49,6 @@
WORKAROUND_CVE_2017_5715 := 0
-ARM_GIC_ARCH := 2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
PLAT_PL061_MAX_GPIOS := 104
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
@@ -67,12 +60,13 @@
-Iinclude/drivers/io
PLAT_BL_COMMON_SOURCES := \
- lib/aarch64/xlat_tables.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/delay_timer/delay_timer.c \
- drivers/arm/pl011/pl011_console.S \
+ drivers/arm/pl011/aarch64/pl011_console.S \
drivers/arm/gic/v2/gicv2_main.c \
plat/arm/common/aarch64/arm_helpers.S \
plat/arm/common/arm_gicv2.c \
@@ -104,7 +98,6 @@
plat/hisilicon/poplar/bl2_plat_setup.c \
plat/hisilicon/poplar/plat_storage.c
-ifeq (${LOAD_IMAGE_V2},1)
BL2_SOURCES += \
plat/hisilicon/poplar/bl2_plat_mem_params_desc.c \
plat/hisilicon/poplar/poplar_image_load.c \
@@ -114,12 +107,11 @@
BL2_SOURCES += \
lib/optee/optee_utils.c
endif
-endif
BL31_SOURCES += \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
- plat/common/aarch64/plat_psci_common.c \
+ plat/common/plat_psci_common.c \
plat/hisilicon/poplar/bl31_plat_setup.c \
plat/hisilicon/poplar/plat_topology.c \
plat/hisilicon/poplar/plat_pm.c
diff --git a/plat/imx/common/plat_imx8_gic.c b/plat/imx/common/plat_imx8_gic.c
index 242e31b..2da9cc0 100644
--- a/plat/imx/common/plat_imx8_gic.c
+++ b/plat/imx/common/plat_imx8_gic.c
@@ -6,6 +6,7 @@
#include <bl_common.h>
#include <gicv3.h>
+#include <interrupt_props.h>
#include <plat_imx8.h>
#include <platform.h>
#include <platform_def.h>
@@ -14,11 +15,12 @@
/* the GICv3 driver only needs to be initialized in EL3 */
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
-/* array of Group1 secure interrupts to be configured by the gic driver */
-const unsigned int g1s_interrupt_array[] = { 6 };
-
-/* array of Group0 interrupts to be configured by the gic driver */
-const unsigned int g0_interrupt_array[] = { 7 };
+static const interrupt_prop_t g01s_interrupt_props[] = {
+ INTR_PROP_DESC(6, GIC_HIGHEST_SEC_PRIORITY,
+ INTR_GROUP1S, GIC_INTR_CFG_LEVEL),
+ INTR_PROP_DESC(7, GIC_HIGHEST_SEC_PRIORITY,
+ INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+};
static unsigned int plat_imx_mpidr_to_core_pos(unsigned long mpidr)
{
@@ -28,10 +30,8 @@
const gicv3_driver_data_t arm_gic_data = {
.gicd_base = PLAT_GICD_BASE,
.gicr_base = PLAT_GICR_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
- .g1s_interrupt_array = g1s_interrupt_array,
+ .interrupt_props = g01s_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = plat_imx_mpidr_to_core_pos,
diff --git a/plat/imx/imx7/warp7/platform.mk b/plat/imx/imx7/warp7/platform.mk
index 279b5d2..deb4c41 100644
--- a/plat/imx/imx7/warp7/platform.mk
+++ b/plat/imx/imx7/warp7/platform.mk
@@ -68,9 +68,6 @@
WORKAROUND_CVE_2017_5715 := 0
-# Disable the PSCI platform compatibility layer by default
-ENABLE_PLAT_COMPAT := 0
-
# Enable reset to BL31 by default
RESET_TO_BL31 := 0
@@ -86,9 +83,6 @@
# Use Coherent memory
USE_COHERENT_MEM := 1
-# Enable new version of image loading required for AArch32
-LOAD_IMAGE_V2 := 1
-
# PLAT_WARP7_UART
PLAT_WARP7_UART :=1
$(eval $(call add_define,PLAT_WARP7_UART))
@@ -96,10 +90,6 @@
# Verify build config
# -------------------
-ifneq (${LOAD_IMAGE_V2}, 1)
- $(error Error: warp7 needs LOAD_IMAGE_V2=1)
-endif
-
ifeq (${ARCH},aarch64)
$(error Error: AArch64 not supported on i.mx7)
endif
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 14f86a1..10c4160 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -245,7 +245,7 @@
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
}
/*
- * bl2_early_platform_setup()
+ * bl2_el3_early_platform_setup()
* MMU off
*/
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index 6cfdaf8..7410ac1 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -291,8 +291,8 @@
}
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
#if DEBUG_CONSOLE
static console_lpuart_t console;
diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk
index 022ad99..ce84e2b 100644
--- a/plat/imx/imx8qm/platform.mk
+++ b/plat/imx/imx8qm/platform.mk
@@ -32,10 +32,8 @@
include plat/imx/common/sci/sci_api.mk
-ENABLE_PLAT_COMPAT := 0
USE_COHERENT_MEM := 1
RESET_TO_BL31 := 1
-ARM_GIC_ARCH := 3
A53_DISABLE_NON_TEMPORAL_HINT := 0
MULTI_CONSOLE_API := 1
ERRATA_A72_859971 := 1
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index 8dac943..6384a85 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -250,8 +250,8 @@
NOTICE("Non-secure Partitioning Succeeded\n");
}
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
#if DEBUG_CONSOLE
static console_lpuart_t console;
diff --git a/plat/imx/imx8qx/platform.mk b/plat/imx/imx8qx/platform.mk
index 0676618..02559b4 100644
--- a/plat/imx/imx8qx/platform.mk
+++ b/plat/imx/imx8qx/platform.mk
@@ -30,8 +30,6 @@
include plat/imx/common/sci/sci_api.mk
-ENABLE_PLAT_COMPAT := 0
USE_COHERENT_MEM := 1
RESET_TO_BL31 := 1
-ARM_GIC_ARCH := 3
MULTI_CONSOLE_API := 1
diff --git a/plat/layerscape/board/ls1043/platform.mk b/plat/layerscape/board/ls1043/platform.mk
index 163d25e..c554ac3 100644
--- a/plat/layerscape/board/ls1043/platform.mk
+++ b/plat/layerscape/board/ls1043/platform.mk
@@ -63,7 +63,6 @@
${LS1043_SECURITY_SOURCES}
# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
# Enable workarounds for selected Cortex-A53 erratas.
diff --git a/plat/layerscape/common/ls_bl31_setup.c b/plat/layerscape/common/ls_bl31_setup.c
index 25fe407..1114a51 100644
--- a/plat/layerscape/common/ls_bl31_setup.c
+++ b/plat/layerscape/common/ls_bl31_setup.c
@@ -7,8 +7,10 @@
#include <assert.h>
#include <bl_common.h>
#include <console.h>
-#include <mmio.h>
#include <gicv2.h>
+#include <interrupt_props.h>
+#include <mmio.h>
+
#include "ls_16550.h"
#include "plat_ls.h"
#include "soc.h"
@@ -20,15 +22,16 @@
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
-const unsigned int g0_interrupt_array1[] = {
- 9
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
gicv2_driver_data_t ls_gic_data = {
.gicd_base = GICD_BASE,
.gicc_base = GICC_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array1),
- .g0_interrupt_array = g0_interrupt_array1,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
diff --git a/plat/layerscape/common/ls_common.mk b/plat/layerscape/common/ls_common.mk
index 1a80e9f..5d96aed 100644
--- a/plat/layerscape/common/ls_common.mk
+++ b/plat/layerscape/common/ls_common.mk
@@ -13,13 +13,6 @@
# mapping the former as executable and the latter as execute-never.
SEPARATE_CODE_AND_RODATA := 1
-# Enable new version of image loading on Layerscape platforms
-LOAD_IMAGE_V2 := 1
-
-# Use generic OID definition (tbbr_oid.h)
-USE_TBBR_DEFS := 1
-
-
COLD_BOOT_SINGLE_CPU := 1
PLAT_INCLUDES += -Iinclude/common/tbbr
@@ -54,9 +47,3 @@
plat/layerscape/common/ls_topology.c \
plat/layerscape/common/ns_access.c \
plat/common/plat_psci_common.c
-# Verify build config
-# -------------------
-
-ifneq (${LOAD_IMAGE_V2}, 1)
- $(error Error: Layerscape needs LOAD_IMAGE_V2=1)
-endif
diff --git a/plat/layerscape/common/tsp/ls_tsp_setup.c b/plat/layerscape/common/tsp/ls_tsp_setup.c
index 82ac965..a046e2f 100644
--- a/plat/layerscape/common/tsp/ls_tsp_setup.c
+++ b/plat/layerscape/common/tsp/ls_tsp_setup.c
@@ -4,23 +4,26 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <gicv2.h>
#include <debug.h>
+#include <gicv2.h>
+#include <interrupt_props.h>
+
#include "ls_16550.h"
#include "plat_ls.h"
#include "soc.h"
#define BL32_END (unsigned long)(&__BL32_END__)
-const unsigned int g0_interrupt_array1[] = {
- 9
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
gicv2_driver_data_t ls_gic_data = {
.gicd_base = GICD_BASE,
.gicc_base = GICC_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array1),
- .g0_interrupt_array = g0_interrupt_array1,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
/*******************************************************************************
diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk
index 5956737..364935c 100644
--- a/plat/marvell/a8k/common/a8k_common.mk
+++ b/plat/marvell/a8k/common/a8k_common.mk
@@ -57,9 +57,9 @@
MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c
-BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \
+BLE_SOURCES := drivers/mentor/i2c/mi2cv.c \
+ $(PLAT_COMMON_BASE)/plat_ble_setup.c \
$(MARVELL_MOCHI_DRV) \
- $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \
$(PLAT_COMMON_BASE)/plat_pm.c \
$(MARVELL_DRV_BASE)/thermal.c \
$(PLAT_COMMON_BASE)/plat_thermal.c \
@@ -97,11 +97,6 @@
# Add trace functionality for PM
BL31_SOURCES += $(PLAT_COMMON_BASE)/plat_pm_trace.c
-# Disable the PSCI platform compatibility layer (allows porting
-# from Old Platform APIs to the new APIs).
-# It is not needed since Marvell platform already used the new platform APIs.
-ENABLE_PLAT_COMPAT := 0
-
# Force builds with BL2 image on a80x0 platforms
ifndef SCP_BL2
$(error "Error: SCP_BL2 image is mandatory for a8k family")
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h
index 4ed8c7e..1b7e954 100644
--- a/plat/marvell/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/a8k/common/include/a8k_plat_def.h
@@ -148,7 +148,8 @@
* it is discarded and BL31 is loaded over the top.
*/
#ifdef SCP_IMAGE
-#define SCP_BL2_BASE BL31_BASE
+#define SCP_BL2_BASE BL31_BASE
+#define SCP_BL2_SIZE BL31_LIMIT
#endif
#ifndef __ASSEMBLER__
diff --git a/drivers/marvell/i2c/a8k_i2c.c b/plat/marvell/a8k/common/include/mentor_i2c_plat.h
similarity index 91%
rename from drivers/marvell/i2c/a8k_i2c.c
rename to plat/marvell/a8k/common/include/mentor_i2c_plat.h
index 1c0f922..8829a92 100644
--- a/drivers/marvell/i2c/a8k_i2c.c
+++ b/plat/marvell/a8k/common/include/mentor_i2c_plat.h
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
-
/* This driver provides I2C support for Marvell A8K and compatible SoCs */
-#include <mmio.h>
+#ifndef A8K_I2C_H
+#define A8K_I2C_H
#define CONFIG_SYS_TCLK 250000000
#define CONFIG_SYS_I2C_SPEED 100000
@@ -30,4 +30,4 @@
uint32_t unstuck;
};
-#include "../../mentor/i2c/mi2cv.c"
+#endif
diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h
index 06d4fa9..ed7bb63 100644
--- a/plat/marvell/a8k/common/include/platform_def.h
+++ b/plat/marvell/a8k/common/include/platform_def.h
@@ -71,14 +71,6 @@
* PLAT_MARVELL_FIP_BASE = 0x4120000
*/
-/*
- * Since BL33 is loaded by BL2 (and validated by BL31) to DRAM offset 0,
- * it is allowed to load/copy images to 'NULL' pointers
- */
-#if defined(IMAGE_BL2) || defined(IMAGE_BL31)
-#define PLAT_ALLOW_ZERO_ADDR_COPY
-#endif
-
#define PLAT_MARVELL_SRAM_BASE 0xFFE1C048
#define PLAT_MARVELL_SRAM_END 0xFFE78000
@@ -199,7 +191,10 @@
#define TRUSTED_DRAM_BASE PLAT_MARVELL_TRUSTED_DRAM_BASE
#define TRUSTED_DRAM_SIZE PLAT_MARVELL_TRUSTED_DRAM_SIZE
+#ifdef BL32
#define BL32_BASE TRUSTED_DRAM_BASE
+#define BL32_LIMIT TRUSTED_DRAM_SIZE
+#endif
#define MVEBU_PMU_IRQ_WA
diff --git a/plat/marvell/common/aarch64/marvell_bl2_mem_params_desc.c b/plat/marvell/common/aarch64/marvell_bl2_mem_params_desc.c
new file mode 100644
index 0000000..17f8771
--- /dev/null
+++ b/plat/marvell/common/aarch64/marvell_bl2_mem_params_desc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <desc_image_load.h>
+#include <marvell_def.h>
+#include <platform.h>
+#include <platform_def.h>
+
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+#ifdef SCP_BL2_BASE
+ /* Fill SCP_BL2 related information if it exists */
+ {
+ .image_id = SCP_BL2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = SCP_BL2_BASE,
+ .image_info.image_max_size = SCP_BL2_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+#endif /* SCP_BL2_BASE */
+
+#ifdef EL3_PAYLOAD_BASE
+ /* Fill EL3 payload related information (BL31 is EL3 payload)*/
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = EL3_PAYLOAD_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+#else /* EL3_PAYLOAD_BASE */
+
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+#if DEBUG
+ .ep_info.args.arg3 = MARVELL_BL31_PLAT_PARAM_VAL,
+#endif
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+# ifdef BL32_BASE
+ .next_handoff_image_id = BL32_IMAGE_ID,
+# else
+ .next_handoff_image_id = BL33_IMAGE_ID,
+# endif
+ },
+
+# ifdef BL32_BASE
+ /* Fill BL32 related information */
+ {
+ .image_id = BL32_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+ .ep_info.pc = BL32_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+# endif /* BL32_BASE */
+
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+# ifdef PRELOADED_BL33_BASE
+ .ep_info.pc = PRELOADED_BL33_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+# else
+ .ep_info.pc = MARVELL_DRAM_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = MARVELL_DRAM_BASE,
+ .image_info.image_max_size = MARVELL_DRAM_SIZE,
+# endif /* PRELOADED_BL33_BASE */
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ }
+#endif /* EL3_PAYLOAD_BASE */
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/marvell/common/marvell_bl1_setup.c b/plat/marvell/common/marvell_bl1_setup.c
index 981cfbe..4e1b256 100644
--- a/plat/marvell/common/marvell_bl1_setup.c
+++ b/plat/marvell/common/marvell_bl1_setup.c
@@ -21,7 +21,6 @@
#pragma weak bl1_platform_setup
#pragma weak bl1_plat_sec_mem_layout
-
/* Data structure which holds the extents of the RAM for BL1*/
static meminfo_t bl1_ram_layout;
@@ -35,8 +34,6 @@
*/
void marvell_bl1_early_platform_setup(void)
{
- const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
-
/* Initialize the console to provide early debug support */
console_init(PLAT_MARVELL_BOOT_UART_BASE,
PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
@@ -45,14 +42,6 @@
/* Allow BL1 to see the whole Trusted RAM */
bl1_ram_layout.total_base = MARVELL_BL_RAM_BASE;
bl1_ram_layout.total_size = MARVELL_BL_RAM_SIZE;
-
- /* Calculate how much RAM BL1 is using and how much remains free */
- bl1_ram_layout.free_base = MARVELL_BL_RAM_BASE;
- bl1_ram_layout.free_size = MARVELL_BL_RAM_SIZE;
- reserve_mem(&bl1_ram_layout.free_base,
- &bl1_ram_layout.free_size,
- BL1_RAM_BASE,
- bl1_size);
}
void bl1_early_platform_setup(void)
diff --git a/plat/marvell/common/marvell_bl2_setup.c b/plat/marvell/common/marvell_bl2_setup.c
index 7c87ce3..f7149c3 100644
--- a/plat/marvell/common/marvell_bl2_setup.c
+++ b/plat/marvell/common/marvell_bl2_setup.c
@@ -6,52 +6,25 @@
*/
#include <arch_helpers.h>
+#include <assert.h>
#include <bl_common.h>
#include <console.h>
+#include <debug.h>
+#include <desc_image_load.h>
#include <marvell_def.h>
#include <platform_def.h>
#include <plat_marvell.h>
#include <string.h>
+#include <utils.h>
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-
-/*****************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific parameters
- *****************************************************************************
- */
-typedef struct bl2_to_bl31_params_mem {
- bl31_params_t bl31_params;
- image_info_t bl31_image_info;
- image_info_t bl32_image_info;
- image_info_t bl33_image_info;
- entry_point_info_t bl33_ep_info;
- entry_point_info_t bl32_ep_info;
- entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-
/* Weak definitions may be overridden in specific MARVELL standard platform */
-#pragma weak bl2_early_platform_setup
+#pragma weak bl2_early_platform_setup2
#pragma weak bl2_platform_setup
#pragma weak bl2_plat_arch_setup
#pragma weak bl2_plat_sec_mem_layout
-#pragma weak bl2_plat_get_bl31_params
-#pragma weak bl2_plat_get_bl31_ep_info
-#pragma weak bl2_plat_flush_bl31_params
-#pragma weak bl2_plat_set_bl31_ep_info
-#pragma weak bl2_plat_get_scp_bl2_meminfo
-#pragma weak bl2_plat_get_bl32_meminfo
-#pragma weak bl2_plat_set_bl32_ep_info
-#pragma weak bl2_plat_get_bl33_meminfo
-#pragma weak bl2_plat_set_bl33_ep_info
-
meminfo_t *bl2_plat_sec_mem_layout(void)
{
@@ -59,81 +32,6 @@
}
/*****************************************************************************
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem_t structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- *****************************************************************************
- */
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
- bl31_params_t *bl2_to_bl31_params;
-
- /*
- * Initialise the memory for all the arguments that needs to
- * be passed to BL31
- */
- memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
-
- /* Assign memory for TF related information */
- bl2_to_bl31_params = &bl31_params_mem.bl31_params;
- SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
- /* Fill BL31 related information */
- bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- /* Fill BL32 related information if it exists */
-#if BL32_BASE
- bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
- VERSION_1, 0);
- bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-#endif
-
- /* Fill BL33 related information */
- bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
- PARAM_EP, VERSION_1, 0);
-
- /* BL33 expects to receive the primary CPU MPID (through x0) */
- bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
- bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- return bl2_to_bl31_params;
-}
-
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
-{
- flush_dcache_range((unsigned long)&bl31_params_mem,
- sizeof(bl2_to_bl31_params_mem_t));
-}
-
-/*****************************************************************************
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- *****************************************************************************
- */
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
- bl31_params_mem.bl31_ep_info.args.arg1 = MARVELL_BL31_PLAT_PARAM_VAL;
-#endif
-
- return &bl31_params_mem.bl31_ep_info;
-}
-
-/*****************************************************************************
* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
* Copy it to a safe location before its reclaimed by later BL2 functionality.
@@ -153,8 +51,12 @@
plat_marvell_io_setup();
}
-void bl2_early_platform_setup(meminfo_t *mem_layout)
+
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+ struct meminfo *mem_layout = (struct meminfo *)arg1;
+
marvell_bl2_early_platform_setup(mem_layout);
}
@@ -189,87 +91,36 @@
marvell_bl2_plat_arch_setup();
}
-/*****************************************************************************
- * Populate the extents of memory available for loading SCP_BL2 (if used),
- * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
- *****************************************************************************
- */
-void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
+int marvell_bl2_handle_post_image_load(unsigned int image_id)
{
- *scp_bl2_meminfo = bl2_tzram_layout;
-}
+ int err = 0;
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
-/*****************************************************************************
- * Before calling this function BL31 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On MARVELL std. platforms we only set the security state of the entrypoint
- *****************************************************************************
- */
-void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
- entry_point_info_t *bl31_ep_info)
-{
- SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
- bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
-}
+ assert(bl_mem_params);
-/*****************************************************************************
- * Populate the extents of memory available for loading BL32
- *****************************************************************************
- */
-#ifdef BL32_BASE
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
- /*
- * Populate the extents of memory available for loading BL32.
- */
- bl32_meminfo->total_base = BL32_BASE;
- bl32_meminfo->free_base = BL32_BASE;
- bl32_meminfo->total_size =
- (TRUSTED_DRAM_BASE + TRUSTED_DRAM_SIZE) - BL32_BASE;
- bl32_meminfo->free_size =
- (TRUSTED_DRAM_BASE + TRUSTED_DRAM_SIZE) - BL32_BASE;
-}
-#endif
+ switch (image_id) {
-/*****************************************************************************
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On MARVELL std. platforms we only set the security state of the entrypoint
- *****************************************************************************
- */
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
- entry_point_info_t *bl32_ep_info)
-{
- SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
- bl32_ep_info->spsr = marvell_get_spsr_for_bl32_entry();
-}
+ case BL33_IMAGE_ID:
+ /* BL33 expects to receive the primary CPU MPID (through r0) */
+ bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+ bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl33_entry();
+ break;
-/*****************************************************************************
- * Before calling this function BL33 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On MARVELL std. platforms we only set the security state of the entrypoint
- *****************************************************************************
- */
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
- entry_point_info_t *bl33_ep_info)
-{
+ default:
+ /* Do nothing in default case */
+ break;
+ }
+
+ return err;
- SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
- bl33_ep_info->spsr = marvell_get_spsr_for_bl33_entry();
}
-/*****************************************************************************
- * Populate the extents of memory available for loading BL33
- *****************************************************************************
- */
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
+/*******************************************************************************
+ * This function can be used by the platforms to update/use image
+ * information for given `image_id`.
+ ******************************************************************************/
+int bl2_plat_handle_post_image_load(unsigned int image_id)
{
- bl33_meminfo->total_base = MARVELL_DRAM_BASE;
- bl33_meminfo->total_size = MARVELL_DRAM_SIZE;
- bl33_meminfo->free_base = MARVELL_DRAM_BASE;
- bl33_meminfo->free_size = MARVELL_DRAM_SIZE;
+ return marvell_bl2_handle_post_image_load(image_id);
}
+
diff --git a/plat/marvell/common/marvell_bl31_setup.c b/plat/marvell/common/marvell_bl31_setup.c
index f381876..0bbb940 100644
--- a/plat/marvell/common/marvell_bl31_setup.c
+++ b/plat/marvell/common/marvell_bl31_setup.c
@@ -68,7 +68,7 @@
* we are guaranteed to pick up good data.
*****************************************************************************
*/
-void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2,
+void marvell_bl31_early_platform_setup(void *from_bl2,
uintptr_t soc_fw_config,
uintptr_t hw_config,
void *plat_params_from_bl2)
@@ -109,12 +109,6 @@
#else
/*
- * Check params passed from BL2 should not be NULL,
- */
- assert(from_bl2 != NULL);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
- /*
* In debug builds, we pass a special value in 'plat_params_from_bl2'
* to verify platform parameters from BL2 to BL31.
* In release builds, it's not used.
@@ -123,12 +117,28 @@
MARVELL_BL31_PLAT_PARAM_VAL);
/*
+ * Check params passed from BL2 should not be NULL,
+ */
+ bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+ assert(params_from_bl2 != NULL);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
+
+ /*
- * Copy BL32 (if populated by BL2) and BL33 entry point information.
+ * Copy BL33 and BL32 (if present), entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- if (from_bl2->bl32_ep_info)
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
+ while (bl_params != NULL) {
+ if (bl_params->image_id == BL32_IMAGE_ID)
+ bl32_image_ep_info = *bl_params->ep_info;
+
+ if (bl_params->image_id == BL33_IMAGE_ID)
+ bl33_image_ep_info = *bl_params->ep_info;
+
+ bl_params = bl_params->next_params_info;
+ }
#endif
}
diff --git a/plat/marvell/common/marvell_common.mk b/plat/marvell/common/marvell_common.mk
index 3ee2f3d..3a6bb03 100644
--- a/plat/marvell/common/marvell_common.mk
+++ b/plat/marvell/common/marvell_common.mk
@@ -20,7 +20,7 @@
LLC_ENABLE := 1
$(eval $(call add_define,LLC_ENABLE))
-PLAT_INCLUDES += -I. -Iinclude/common/tbbr \
+PLAT_INCLUDES += -I. -Iinclude/common -Iinclude/common/tbbr \
-I$(MARVELL_PLAT_INCLUDE_BASE)/common \
-I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64
@@ -46,8 +46,12 @@
BL2_SOURCES += drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
+ common/desc_image_load.c \
$(MARVELL_PLAT_BASE)/common/marvell_bl2_setup.c \
- $(MARVELL_PLAT_BASE)/common/marvell_io_storage.c
+ $(MARVELL_PLAT_BASE)/common/marvell_io_storage.c \
+ $(MARVELL_PLAT_BASE)/common/aarch64/marvell_bl2_mem_params_desc.c \
+ $(MARVELL_PLAT_BASE)/common/marvell_image_load.c
+
BL31_SOURCES += $(MARVELL_PLAT_BASE)/common/marvell_bl31_setup.c \
$(MARVELL_PLAT_BASE)/common/marvell_pm.c \
diff --git a/plat/marvell/common/marvell_image_load.c b/plat/marvell/common/marvell_image_load.c
new file mode 100644
index 0000000..d69b1b1
--- /dev/null
+++ b/plat/marvell/common/marvell_image_load.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <desc_image_load.h>
+#include <platform.h>
+#include <platform_def.h>
+
+/*******************************************************************************
+ * This function flushes the data structures so that they are visible
+ * in memory for the next BL image.
+ ******************************************************************************/
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of loadable images.
+ ******************************************************************************/
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of executable images.
+ ******************************************************************************/
+bl_params_t *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c
index a0ca50d..8bc633b 100644
--- a/plat/marvell/common/mrvl_sip_svc.c
+++ b/plat/marvell/common/mrvl_sip_svc.c
@@ -11,7 +11,7 @@
#include <marvell_plat_priv.h>
#include <plat_marvell.h>
#include <runtime_svc.h>
-#include <smcc.h>
+#include <smccc.h>
#include "comphy/phy-comphy-cp110.h"
/* #define DEBUG_COMPHY */
diff --git a/plat/mediatek/common/mtk_plat_common.c b/plat/mediatek/common/mtk_plat_common.c
index a15131d..bff83c7 100644
--- a/plat/mediatek/common/mtk_plat_common.c
+++ b/plat/mediatek/common/mtk_plat_common.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <bl_common.h>
#include <cci.h>
#include <console.h>
diff --git a/plat/mediatek/common/mtk_plat_common.h b/plat/mediatek/common/mtk_plat_common.h
index 501c339..923cf69 100644
--- a/plat/mediatek/common/mtk_plat_common.h
+++ b/plat/mediatek/common/mtk_plat_common.h
@@ -1,11 +1,15 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __MTK_PLAT_COMMON_H__
#define __MTK_PLAT_COMMON_H__
+
+#include <bl_common.h>
+#include <param_header.h>
#include <stdint.h>
+
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
@@ -45,6 +49,15 @@
uint64_t tee_info_addr;
};
+struct mtk_bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+};
+
/* Declarations for mtk_plat_common.c */
uint32_t plat_get_spsr_for_bl32_entry(void);
uint32_t plat_get_spsr_for_bl33_entry(void);
diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c
index 32f0157..d9577a6 100644
--- a/plat/mediatek/mt6795/bl31_plat_setup.c
+++ b/plat/mediatek/mt6795/bl31_plat_setup.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <cci.h>
@@ -172,16 +171,15 @@
* BL2 has flushed this information to memory, so we are guaranteed to pick up
* good data.
******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- struct mtk_bl_param_t *pmtk_bl_param =
- (struct mtk_bl_param_t *)from_bl2;
+ struct mtk_bl_param_t *pmtk_bl_param = (struct mtk_bl_param_t *)arg0;
struct atf_arg_t *teearg;
unsigned long long normal_base;
unsigned long long atf_base;
- assert(from_bl2 != NULL);
+ assert(pmtk_bl_param != NULL);
/*
* Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits
* of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit
@@ -190,8 +188,6 @@
*/
pmtk_bl_param =
(struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff);
- plat_params_from_bl2 =
- (void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff);
teearg = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr;
@@ -445,6 +441,6 @@
INFO("BL3-1: Next image address = 0x%llx\n",
(unsigned long long) next_image_info->pc);
INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr);
- cm_init_context(read_mpidr_el1(), next_image_info);
+ cm_init_my_context(next_image_info);
cm_prepare_el3_exit(image_type);
}
diff --git a/plat/mediatek/mt6795/include/plat_macros.S b/plat/mediatek/mt6795/include/plat_macros.S
index 48bf28f..7485647 100644
--- a/plat/mediatek/mt6795/include/plat_macros.S
+++ b/plat/mediatek/mt6795/include/plat_macros.S
@@ -5,7 +5,6 @@
*/
#include <cci.h>
-#include <gic_v2.h>
#include <platform_def.h>
.section .rodata.gic_reg_name, "aS"
diff --git a/plat/mediatek/mt6795/include/platform_def.h b/plat/mediatek/mt6795/include/platform_def.h
index 0fa63a1..0110e19 100644
--- a/plat/mediatek/mt6795/include/platform_def.h
+++ b/plat/mediatek/mt6795/include/platform_def.h
@@ -117,10 +117,6 @@
#define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5
-#define PLAT_ARM_G0_IRQS FIQ_SMP_CALL_SGI
-
-#define DEBUG_XLAT_TABLE 0
-
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
@@ -132,9 +128,7 @@
******************************************************************************/
/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
@@ -145,11 +139,10 @@
#endif
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-#if ENABLE_PLAT_COMPAT
-#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
-#else
#define PLAT_MAX_PWR_LVL U(2) /* MPIDR_AFFLVL2 */
-#endif
+
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(2)
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_SYSTEM_COUNT 1
@@ -198,7 +191,8 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define MAX_XLAT_TABLES 7
#define MAX_MMAP_REGIONS 16
diff --git a/plat/mediatek/mt6795/plat_mt_gic.c b/plat/mediatek/mt6795/plat_mt_gic.c
index 47a23df..11282fc 100644
--- a/plat/mediatek/mt6795/plat_mt_gic.c
+++ b/plat/mediatek/mt6795/plat_mt_gic.c
@@ -1,23 +1,24 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <gicv2.h>
-#include <plat_arm.h>
+#include <interrupt_props.h>
#include <platform.h>
#include <platform_def.h>
-const unsigned int g0_interrupt_array[] = {
- PLAT_ARM_G0_IRQS
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
gicv2_driver_data_t arm_gic_data = {
.gicd_base = BASE_GICD_BASE,
.gicc_base = BASE_GICC_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
void plat_mt_gic_driver_init(void)
diff --git a/plat/mediatek/mt6795/plat_pm.c b/plat/mediatek/mt6795/plat_pm.c
index bd47bd8..d050664 100644
--- a/plat/mediatek/mt6795/plat_pm.c
+++ b/plat/mediatek/mt6795/plat_pm.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bakery_lock.h>
#include <cci.h>
diff --git a/plat/mediatek/mt6795/platform.mk b/plat/mediatek/mt6795/platform.mk
index 1bdf30a..c2fd511 100644
--- a/plat/mediatek/mt6795/platform.mk
+++ b/plat/mediatek/mt6795/platform.mk
@@ -26,7 +26,8 @@
-Iinclude/common/tbbr/ \
${OEMS_INCLUDES}
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
plat/common/plat_gic.c
BL31_SOURCES += drivers/arm/cci/cci.c \
@@ -35,7 +36,7 @@
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c \
- drivers/console/console.S \
+ drivers/console/aarch64/console.S \
drivers/delay_timer/delay_timer.c \
lib/cpus/aarch64/cortex_a53.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
@@ -52,11 +53,6 @@
${MTK_PLAT_SOC}/scu.c \
${OEMS_SOURCES}
-# Flag used by the MTK_platform port to determine the version of ARM GIC
-# architecture to use for interrupt management in EL3.
-ARM_GIC_ARCH := 2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_826319 := 1
ERRATA_A53_836870 := 1
diff --git a/plat/mediatek/mt8173/aarch64/plat_helpers.S b/plat/mediatek/mt8173/aarch64/plat_helpers.S
index 3e0b4f4..d589499 100644
--- a/plat/mediatek/mt8173/aarch64/plat_helpers.S
+++ b/plat/mediatek/mt8173/aarch64/plat_helpers.S
@@ -36,7 +36,6 @@
ret
endfunc platform_is_primary_cpu
-#if !ENABLE_PLAT_COMPAT
/* -----------------------------------------------------
* unsigned int plat_my_core_pos(void);
*
@@ -50,7 +49,6 @@
add x0, x1, x0, LSR #6
ret
endfunc plat_my_core_pos
-#endif
/* ---------------------------------------------
* int plat_crash_console_init(void)
diff --git a/plat/mediatek/mt8173/aarch64/platform_common.c b/plat/mediatek/mt8173/aarch64/platform_common.c
index 996344d..a761992 100644
--- a/plat/mediatek/mt8173/aarch64/platform_common.c
+++ b/plat/mediatek/mt8173/aarch64/platform_common.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <bl_common.h>
#include <cci.h>
#include <debug.h>
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c
index e51bdbb..ce52309 100644
--- a/plat/mediatek/mt8173/bl31_plat_setup.c
+++ b/plat/mediatek/mt8173/bl31_plat_setup.c
@@ -12,6 +12,7 @@
#include <mcucfg.h>
#include <mmio.h>
#include <mtcmos.h>
+#include <mtk_plat_common.h>
#include <plat_arm.h>
#include <plat_private.h>
#include <platform.h>
@@ -91,19 +92,21 @@
* BL2 has flushed this information to memory, so we are guaranteed to pick up
* good data.
******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+ struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
+
console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
VERBOSE("bl31_setup\n");
- assert(from_bl2 != NULL);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
+ assert(arg_from_bl2 != NULL);
+ assert(arg_from_bl2->h.type == PARAM_BL31);
+ assert(arg_from_bl2->h.version >= VERSION_1);
- bl32_ep_info = *from_bl2->bl32_ep_info;
- bl33_ep_info = *from_bl2->bl33_ep_info;
+ bl32_ep_info = *arg_from_bl2->bl32_ep_info;
+ bl33_ep_info = *arg_from_bl2->bl33_ep_info;
}
/*******************************************************************************
@@ -120,11 +123,6 @@
plat_arm_gic_driver_init();
plat_arm_gic_init();
-#if ENABLE_PLAT_COMPAT
- /* Topologies are best known to the platform. */
- mt_setup_topology();
-#endif
-
/* Initialize spm at boot time */
spm_boot_init();
}
diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h
index 6e3f4a3..9bbed3c 100644
--- a/plat/mediatek/mt8173/include/platform_def.h
+++ b/plat/mediatek/mt8173/include/platform_def.h
@@ -36,11 +36,9 @@
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
-#if !ENABLE_PLAT_COMPAT
#define PLAT_MAX_PWR_LVL U(2)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(2)
-#endif
#define PLATFORM_SYSTEM_COUNT 1
#define PLATFORM_CLUSTER_COUNT 2
#define PLATFORM_CLUSTER0_CORE_COUNT 4
diff --git a/plat/mediatek/mt8173/plat_mt_gic.c b/plat/mediatek/mt8173/plat_mt_gic.c
index c955d61..16e36af 100644
--- a/plat/mediatek/mt8173/plat_mt_gic.c
+++ b/plat/mediatek/mt8173/plat_mt_gic.c
@@ -3,7 +3,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <arm_gic.h>
+
#include <bl_common.h>
#include <mt8173_def.h>
#include <utils.h>
diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c
index bc89ad9..b19d3f3 100644
--- a/plat/mediatek/mt8173/plat_pm.c
+++ b/plat/mediatek/mt8173/plat_pm.c
@@ -26,7 +26,6 @@
#include <spm_mcdi.h>
#include <spm_suspend.h>
-#if !ENABLE_PLAT_COMPAT
#define MTK_PWR_LVL0 0
#define MTK_PWR_LVL1 1
#define MTK_PWR_LVL2 2
@@ -36,7 +35,6 @@
#define MTK_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[MTK_PWR_LVL1]
#define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
(state)->pwr_domain_state[MTK_PWR_LVL2] : 0)
-#endif
#if PSCI_EXTENDED_STATE_ID
/*
@@ -234,59 +232,6 @@
mt_cpu_restore(mpidr);
}
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
-* Private function which is used to determine if any platform actions
-* should be performed for the specified affinity instance given its
-* state. Nothing needs to be done if the 'state' is not off or if this is not
-* the highest affinity level which will enter the 'state'.
-*******************************************************************************/
-static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state)
-{
- unsigned int max_phys_off_afflvl;
-
- assert(afflvl <= MPIDR_AFFLVL2);
-
- if (state != PSCI_STATE_OFF)
- return -EAGAIN;
-
- /*
- * Find the highest affinity level which will be suspended and postpone
- * all the platform specific actions until that level is hit.
- */
- max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
- assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
- if (afflvl != max_phys_off_afflvl)
- return -EAGAIN;
-
- return 0;
-}
-
-/*******************************************************************************
- * MTK_platform handler called when an affinity instance is about to enter
- * standby.
- ******************************************************************************/
-static void plat_affinst_standby(unsigned int power_state)
-{
- unsigned int target_afflvl;
-
- /* Sanity check the requested state */
- target_afflvl = psci_get_pstate_afflvl(power_state);
-
- /*
- * It's possible to enter standby only on affinity level 0 i.e. a cpu
- * on the MTK_platform. Ignore any other affinity level.
- */
- if (target_afflvl == MPIDR_AFFLVL0) {
- /*
- * Enter standby state. dsb is good practice before using wfi
- * to enter low power states.
- */
- dsb();
- wfi();
- }
-}
-#else
static void plat_cpu_standby(plat_local_state_t cpu_state)
{
unsigned int scr;
@@ -298,47 +243,11 @@
wfi();
write_scr_el3(scr);
}
-#endif
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be turned
* on. The level and mpidr determine the affinity instance.
******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static int plat_affinst_on(unsigned long mpidr,
- unsigned long sec_entrypoint,
- unsigned int afflvl,
- unsigned int state)
-{
- int rc = PSCI_E_SUCCESS;
- unsigned long cpu_id;
- unsigned long cluster_id;
- uintptr_t rv;
-
- /*
- * It's possible to turn on only affinity level 0 i.e. a cpu
- * on the MTK_platform. Ignore any other affinity level.
- */
- if (afflvl != MPIDR_AFFLVL0)
- return rc;
-
- cpu_id = mpidr & MPIDR_CPU_MASK;
- cluster_id = mpidr & MPIDR_CLUSTER_MASK;
-
- if (cluster_id)
- rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
- else
- rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
-
- mmio_write_32(rv, sec_entrypoint);
- INFO("mt_on[%ld:%ld], entry %x\n",
- cluster_id, cpu_id, mmio_read_32(rv));
-
- spm_hotplug_on(mpidr);
-
- return rc;
-}
-#else
static uintptr_t secure_entrypoint;
static int plat_power_domain_on(unsigned long mpidr)
@@ -363,7 +272,6 @@
spm_hotplug_on(mpidr);
return rc;
}
-#endif
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be turned
@@ -377,30 +285,6 @@
* dealt with. So do not write & read global variables across calls. It will be
* wise to do flush a write to the global to prevent unpredictable results.
******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_off(unsigned int afflvl, unsigned int state)
-{
- unsigned long mpidr = read_mpidr_el1();
-
- /* Determine if any platform actions need to be executed. */
- if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
- return;
-
- /* Prevent interrupts from spuriously waking up this cpu */
- gicv2_cpuif_disable();
-
- spm_hotplug_off(mpidr);
-
- trace_power_flow(mpidr, CPU_DOWN);
-
- if (afflvl != MPIDR_AFFLVL0) {
- /* Disable coherency if this cluster is to be turned off */
- plat_cci_disable();
-
- trace_power_flow(mpidr, CLUSTER_DOWN);
- }
-}
-#else
static void plat_power_domain_off(const psci_power_state_t *state)
{
unsigned long mpidr = read_mpidr_el1();
@@ -419,7 +303,6 @@
trace_power_flow(mpidr, CLUSTER_DOWN);
}
}
-#endif
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be
@@ -433,51 +316,6 @@
* dealt with. So do not write & read global variables across calls. It will be
* wise to do flush a write to the global to prevent unpredictable results.
******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_suspend(unsigned long sec_entrypoint,
- unsigned int afflvl,
- unsigned int state)
-{
- unsigned long mpidr = read_mpidr_el1();
- unsigned long cluster_id;
- unsigned long cpu_id;
- uintptr_t rv;
-
- /* Determine if any platform actions need to be executed. */
- if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
- return;
-
- cpu_id = mpidr & MPIDR_CPU_MASK;
- cluster_id = mpidr & MPIDR_CLUSTER_MASK;
-
- if (cluster_id)
- rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
- else
- rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
-
- mmio_write_32(rv, sec_entrypoint);
-
- if (afflvl < MPIDR_AFFLVL2)
- spm_mcdi_prepare_for_off_state(mpidr, afflvl);
-
- if (afflvl >= MPIDR_AFFLVL0)
- mt_platform_save_context(mpidr);
-
- /* Perform the common cluster specific operations */
- if (afflvl >= MPIDR_AFFLVL1) {
- /* Disable coherency if this cluster is to be turned off */
- plat_cci_disable();
- }
-
- if (afflvl >= MPIDR_AFFLVL2) {
- disable_scu(mpidr);
- generic_timer_backup();
- spm_system_suspend();
- /* Prevent interrupts from spuriously waking up this cpu */
- gicv2_cpuif_disable();
- }
-}
-#else
static void plat_power_domain_suspend(const psci_power_state_t *state)
{
unsigned long mpidr = read_mpidr_el1();
@@ -517,7 +355,6 @@
gicv2_cpuif_disable();
}
}
-#endif
/*******************************************************************************
* MTK_platform handler called when an affinity instance has just been powered
@@ -526,28 +363,6 @@
* was turned off prior to wakeup and do what's necessary to setup it up
* correctly.
******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state)
-{
- unsigned long mpidr = read_mpidr_el1();
-
- /* Determine if any platform actions need to be executed. */
- if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
- return;
-
- /* Perform the common cluster specific operations */
- if (afflvl >= MPIDR_AFFLVL1) {
- /* Enable coherency if this cluster was off */
- plat_cci_enable();
- trace_power_flow(mpidr, CLUSTER_UP);
- }
-
- /* Enable the gic cpu interface */
- gicv2_cpuif_enable();
- gicv2_pcpu_distif_init();
- trace_power_flow(mpidr, CPU_UP);
-}
-#else
void mtk_system_pwr_domain_resume(void);
static void plat_power_domain_on_finish(const psci_power_state_t *state)
@@ -574,44 +389,12 @@
gicv2_pcpu_distif_init();
trace_power_flow(mpidr, CPU_UP);
}
-#endif
/*******************************************************************************
* MTK_platform handler called when an affinity instance has just been powered
* on after having been suspended earlier. The level and mpidr determine the
* affinity instance.
******************************************************************************/
-#if ENABLE_PLAT_COMPAT
-static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
-{
- unsigned long mpidr = read_mpidr_el1();
-
- /* Determine if any platform actions need to be executed. */
- if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
- return;
-
- if (afflvl >= MPIDR_AFFLVL2) {
- /* Enable the gic cpu interface */
- plat_arm_gic_init();
- spm_system_suspend_finish();
- enable_scu(mpidr);
- }
-
- /* Perform the common cluster specific operations */
- if (afflvl >= MPIDR_AFFLVL1) {
- /* Enable coherency if this cluster was off */
- plat_cci_enable();
- }
-
- if (afflvl >= MPIDR_AFFLVL0)
- mt_platform_restore_context(mpidr);
-
- if (afflvl < MPIDR_AFFLVL2)
- spm_mcdi_finish_for_on_state(mpidr, afflvl);
-
- gicv2_pcpu_distif_init();
-}
-#else
static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
{
unsigned long mpidr = read_mpidr_el1();
@@ -642,15 +425,7 @@
gicv2_pcpu_distif_init();
}
-#endif
-#if ENABLE_PLAT_COMPAT
-static unsigned int plat_get_sys_suspend_power_state(void)
-{
- /* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */
- return psci_make_powerstate(0, 1, 2);
-}
-#else
static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
assert(PLAT_MAX_PWR_LVL >= 2);
@@ -658,7 +433,6 @@
for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = MTK_LOCAL_STATE_OFF;
}
-#endif
/*******************************************************************************
* MTK handlers to shutdown/reboot the system
@@ -690,7 +464,6 @@
panic();
}
-#if !ENABLE_PLAT_COMPAT
#if !PSCI_EXTENDED_STATE_ID
static int plat_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
@@ -775,34 +548,7 @@
plat_arm_gic_init();
}
-#endif
-
-#if ENABLE_PLAT_COMPAT
-/*******************************************************************************
- * Export the platform handlers to enable psci to invoke them
- ******************************************************************************/
-static const plat_pm_ops_t plat_plat_pm_ops = {
- .affinst_standby = plat_affinst_standby,
- .affinst_on = plat_affinst_on,
- .affinst_off = plat_affinst_off,
- .affinst_suspend = plat_affinst_suspend,
- .affinst_on_finish = plat_affinst_on_finish,
- .affinst_suspend_finish = plat_affinst_suspend_finish,
- .system_off = plat_system_off,
- .system_reset = plat_system_reset,
- .get_sys_suspend_power_state = plat_get_sys_suspend_power_state,
-};
-/*******************************************************************************
- * Export the platform specific power ops & initialize the mtk_platform power
- * controller
- ******************************************************************************/
-int platform_setup_pm(const plat_pm_ops_t **plat_ops)
-{
- *plat_ops = &plat_plat_pm_ops;
- return 0;
-}
-#else
static const plat_psci_ops_t plat_plat_pm_ops = {
.cpu_standby = plat_cpu_standby,
.pwr_domain_on = plat_power_domain_on,
@@ -852,4 +598,3 @@
return target;
}
-#endif
diff --git a/plat/mediatek/mt8173/plat_topology.c b/plat/mediatek/mt8173/plat_topology.c
index 5bb0451..d70fea5 100644
--- a/plat/mediatek/mt8173/plat_topology.c
+++ b/plat/mediatek/mt8173/plat_topology.c
@@ -7,31 +7,6 @@
#include <platform_def.h>
#include <psci.h>
-#if ENABLE_PLAT_COMPAT
-unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
-{
- /* Report 1 (absent) instance at levels higher that the cluster level */
- if (aff_lvl > MPIDR_AFFLVL1)
- return PLATFORM_SYSTEM_COUNT;
-
- if (aff_lvl == MPIDR_AFFLVL1)
- return PLATFORM_CLUSTER_COUNT;
-
- return mpidr & 0x100 ? PLATFORM_CLUSTER1_CORE_COUNT :
- PLATFORM_CLUSTER0_CORE_COUNT;
-}
-
-unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
-{
- return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
-}
-
-int mt_setup_topology(void)
-{
- /* [TODO] Make topology configurable via SCC */
- return 0;
-}
-#else
const unsigned char mtk_power_domain_tree_desc[] = {
/* No of root nodes */
@@ -82,4 +57,3 @@
return (cpu_id + (cluster_id * 4));
}
-#endif
diff --git a/plat/mediatek/mt8173/platform.mk b/plat/mediatek/mt8173/platform.mk
index 2eef81b..294aea4 100644
--- a/plat/mediatek/mt8173/platform.mk
+++ b/plat/mediatek/mt8173/platform.mk
@@ -56,11 +56,6 @@
${MTK_PLAT_SOC}/power_tracer.c \
${MTK_PLAT_SOC}/scu.c
-# Flag used by the MTK_platform port to determine the version of ARM GIC
-# architecture to use for interrupt management in EL3.
-ARM_GIC_ARCH := 2
-$(eval $(call add_define,ARM_GIC_ARCH))
-
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_826319 := 1
ERRATA_A53_836870 := 1
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 6599768..9410d44 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -23,13 +23,13 @@
#include <string.h>
#include <tegra_def.h>
#include <tegra_private.h>
+#include <utils.h>
#include <utils_def.h>
/* length of Trusty's input parameters (in bytes) */
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
extern void memcpy16(void *dest, const void *src, unsigned int length);
-extern void zeromem16(void *mem, unsigned int length);
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -72,7 +72,7 @@
; /* do nothing */
}
-bl31_params_t *plat_get_bl31_params(void)
+struct tegra_bl31_params *plat_get_bl31_params(void)
{
return NULL;
}
@@ -112,11 +112,11 @@
* Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
* info.
******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- plat_params_from_bl2_t *plat_params =
- (plat_params_from_bl2_t *)plat_params_from_bl2;
+ struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
+ plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
image_info_t bl32_img_info = { {0} };
uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
@@ -126,8 +126,8 @@
* might use custom ways to get arguments, so provide handlers which
* they can override.
*/
- if (from_bl2 == NULL)
- from_bl2 = plat_get_bl31_params();
+ if (arg_from_bl2 == NULL)
+ arg_from_bl2 = plat_get_bl31_params();
if (plat_params == NULL)
plat_params = plat_get_bl31_plat_params();
@@ -135,14 +135,14 @@
* Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
- assert(from_bl2);
- assert(from_bl2->bl33_ep_info);
- bl33_image_ep_info = *from_bl2->bl33_ep_info;
+ assert(arg_from_bl2);
+ assert(arg_from_bl2->bl33_ep_info);
+ bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
- if (from_bl2->bl32_ep_info) {
- bl32_image_ep_info = *from_bl2->bl32_ep_info;
- bl32_mem_size = from_bl2->bl32_ep_info->args.arg0;
- bl32_boot_params = from_bl2->bl32_ep_info->args.arg2;
+ if (arg_from_bl2->bl32_ep_info) {
+ bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
+ bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
+ bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
}
/*
@@ -191,9 +191,9 @@
* inside the TZDRAM. We check the BL32 image info to find out
* the base/PC values and relocate the image if necessary.
*/
- if (from_bl2->bl32_image_info) {
+ if (arg_from_bl2->bl32_image_info) {
- bl32_img_info = *from_bl2->bl32_image_info;
+ bl32_img_info = *arg_from_bl2->bl32_image_info;
/* Relocate BL32 if it resides outside of the TZDRAM */
tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
@@ -217,7 +217,7 @@
bl32_img_info.image_size);
/* clean up non-secure intermediate buffer */
- zeromem16((void *)(uintptr_t)bl32_start,
+ zeromem((void *)(uintptr_t)bl32_start,
bl32_img_info.image_size);
}
}
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 8f6c7b8..abb9bb8 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -13,8 +13,7 @@
COMMON_DIR := plat/nvidia/tegra/common
-BL31_SOURCES += drivers/arm/gic/gic_v2.c \
- drivers/console/aarch64/console.S \
+BL31_SOURCES += drivers/console/aarch64/console.S \
drivers/delay_timer/delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
${COMMON_DIR}/aarch64/tegra_helpers.S \
diff --git a/plat/nvidia/tegra/common/tegra_fiq_glue.c b/plat/nvidia/tegra/common/tegra_fiq_glue.c
index 2f43958..bc6d305 100644
--- a/plat/nvidia/tegra/common/tegra_fiq_glue.c
+++ b/plat/nvidia/tegra/common/tegra_fiq_glue.c
@@ -12,7 +12,6 @@
#include <context_mgmt.h>
#include <debug.h>
#include <denver.h>
-#include <gic_v2.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <tegra_def.h>
diff --git a/plat/nvidia/tegra/common/tegra_gic.c b/plat/nvidia/tegra/common/tegra_gic.c
index 3ace554..c3dc5f6 100644
--- a/plat/nvidia/tegra/common/tegra_gic.c
+++ b/plat/nvidia/tegra/common/tegra_gic.c
@@ -5,11 +5,9 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
-#include <gic_v2.h>
#include <interrupt_mgmt.h>
#include <platform.h>
#include <stdint.h>
@@ -188,14 +186,9 @@
* both normal and secure worlds are using ARM GICv2. This parameter
* will be used when the secure world starts using GICv3.
*/
-#if ARM_GIC_ARCH == 2
return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type);
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
}
-#if ARM_GIC_ARCH == 2
/*******************************************************************************
* This function returns the type of the highest priority pending interrupt at
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
@@ -296,10 +289,6 @@
return ret;
}
-#else
-#error "Invalid ARM GIC architecture version specified for platform port"
-#endif /* ARM_GIC_ARCH */
-
uint32_t plat_ic_get_pending_interrupt_id(void)
{
return tegra_gic_get_pending_interrupt_id();
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S
index f54e168..caf1148 100644
--- a/plat/nvidia/tegra/include/plat_macros.S
+++ b/plat/nvidia/tegra/include/plat_macros.S
@@ -7,7 +7,6 @@
#ifndef __PLAT_MACROS_S__
#define __PLAT_MACROS_S__
-#include <gic_v2.h>
#include <tegra_def.h>
.section .rodata.gic_reg_name, "aS"
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 7a06455..b6f2df7 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -50,6 +50,18 @@
uint32_t type;
} irq_sec_cfg_t;
+/*******************************************************************************
+ * Struct describing parameters passed to bl31
+ ******************************************************************************/
+struct tegra_bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+};
+
/* Declarations for plat_psci_handlers.c */
int32_t tegra_soc_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state);
@@ -58,7 +70,7 @@
const mmap_region_t *plat_get_mmio_map(void);
uint32_t plat_get_console_from_id(int id);
void plat_gic_setup(void);
-bl31_params_t *plat_get_bl31_params(void);
+struct tegra_bl31_params *plat_get_bl31_params(void);
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
/* Declarations for plat_secondary.c */
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index ad60620..33548b7 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -13,9 +13,6 @@
# enable assert() for release/debug builds
ENABLE_ASSERTIONS := 1
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
# enable dynamic memory mapping
PLAT_XLAT_TABLES_DYNAMIC := 1
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index fad6a59..233644b 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -217,13 +217,13 @@
/*******************************************************************************
* Return pointer to the BL31 params from previous bootloader
******************************************************************************/
-bl31_params_t *plat_get_bl31_params(void)
+struct tegra_bl31_params *plat_get_bl31_params(void)
{
uint32_t val;
val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
- return (bl31_params_t *)(uintptr_t)val;
+ return (struct tegra_bl31_params *)(uintptr_t)val;
}
/*******************************************************************************
diff --git a/plat/qemu/platform.mk b/plat/qemu/platform.mk
index 2ecbec7..9167c9f 100644
--- a/plat/qemu/platform.mk
+++ b/plat/qemu/platform.mk
@@ -25,12 +25,6 @@
include lib/libfdt/libfdt.mk
-# Enable new version of image loading on QEMU platforms
-LOAD_IMAGE_V2 := 1
-ifneq ($(LOAD_IMAGE_V2),1)
-$(error Error: qemu needs LOAD_IMAGE_V2=1)
-endif
-
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
@@ -68,8 +62,6 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
- USE_TBBR_DEFS := 1
-
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
@@ -181,9 +173,6 @@
MULTI_CONSOLE_API := 1
endif
-# Disable the PSCI platform compatibility layer
-ENABLE_PLAT_COMPAT := 0
-
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index 4a5d74a..fd53495 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -39,7 +39,7 @@
* does not do anything platform specific.
*****************************************************************************/
#ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
+#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#else
#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
#endif
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index b9a30d8..d76621d 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -20,103 +20,6 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-#if !LOAD_IMAGE_V2
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL3-1, e.g. while passing control to it from BL2, bl31_params
- * and other platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
- bl31_params_t bl31_params;
- image_info_t bl31_image_info;
- image_info_t bl32_image_info;
- image_info_t bl33_image_info;
- entry_point_info_t bl33_ep_info;
- entry_point_info_t bl32_ep_info;
- entry_point_info_t bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-
-static bl2_to_bl31_params_mem_t bl31_params_mem;
-
-
-meminfo_t *bl2_plat_sec_mem_layout(void)
-{
- return &bl2_tzram_layout;
-}
-
-/*******************************************************************************
- * This function assigns a pointer to the memory that the platform has kept
- * aside to pass platform specific and trusted firmware related information
- * to BL31. This memory is allocated by allocating memory to
- * bl2_to_bl31_params_mem_t structure which is a superset of all the
- * structure whose information is passed to BL31
- * NOTE: This function should be called only once and should be done
- * before generating params to BL31
- ******************************************************************************/
-bl31_params_t *bl2_plat_get_bl31_params(void)
-{
- bl31_params_t *bl2_to_bl31_params;
-
- /*
- * Initialise the memory for all the arguments that needs to
- * be passed to BL3-1
- */
- zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
-
- /* Assign memory for TF related information */
- bl2_to_bl31_params = &bl31_params_mem.bl31_params;
- SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
-
- /* Fill BL3-1 related information */
- bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- /* Fill BL3-2 related information */
- bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
- VERSION_1, 0);
- bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- /* Fill BL3-3 related information */
- bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
- PARAM_EP, VERSION_1, 0);
-
- /* BL3-3 expects to receive the primary CPU MPID (through x0) */
- bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
-
- bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
- SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
- VERSION_1, 0);
-
- return bl2_to_bl31_params;
-}
-
-/* Flush the TF params and the TF plat params */
-void bl2_plat_flush_bl31_params(void)
-{
- flush_dcache_range((unsigned long)&bl31_params_mem,
- sizeof(bl2_to_bl31_params_mem_t));
-}
-
-/*******************************************************************************
- * This function returns a pointer to the shared memory that the platform
- * has kept to point to entry point information of BL31 to BL2
- ******************************************************************************/
-struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
-{
-#if DEBUG
- bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
-#endif
-
- return &bl31_params_mem.bl31_ep_info;
-}
-#endif /* !LOAD_IMAGE_V2 */
-
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
@@ -174,7 +77,7 @@
}
#ifdef AARCH32
-#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
+#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#else
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
#endif
@@ -231,7 +134,6 @@
return spsr;
}
-#if LOAD_IMAGE_V2
static int qemu_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
@@ -304,75 +206,6 @@
{
return qemu_bl2_handle_post_image_load(image_id);
}
-
-#else /* LOAD_IMAGE_V2 */
-
-/*******************************************************************************
- * Before calling this function BL3-1 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-1 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
- entry_point_info_t *bl31_ep_info)
-{
- SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
- bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
-}
-
-/*******************************************************************************
- * Before calling this function BL3-2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-2 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
- entry_point_info_t *bl32_ep_info)
-{
- SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
- bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
-}
-
-/*******************************************************************************
- * Before calling this function BL3-3 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL3-3 and set SPSR and security state.
- * On ARM standard platforms we only set the security state of the entrypoint
- ******************************************************************************/
-void bl2_plat_set_bl33_ep_info(image_info_t *image,
- entry_point_info_t *bl33_ep_info)
-{
-
- SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
- bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL32
- ******************************************************************************/
-void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
-{
- /*
- * Populate the extents of memory available for loading BL32.
- */
- bl32_meminfo->total_base = BL32_BASE;
- bl32_meminfo->free_base = BL32_BASE;
- bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
- bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
-}
-
-/*******************************************************************************
- * Populate the extents of memory available for loading BL33
- ******************************************************************************/
-void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
-{
- bl33_meminfo->total_base = NS_DRAM0_BASE;
- bl33_meminfo->total_size = NS_DRAM0_SIZE;
- bl33_meminfo->free_base = NS_DRAM0_BASE;
- bl33_meminfo->free_size = NS_DRAM0_SIZE;
-}
-#endif /* !LOAD_IMAGE_V2 */
uintptr_t plat_get_ns_image_entrypoint(void)
{
diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c
index 2d4198b..376ff2f 100644
--- a/plat/qemu/qemu_common.c
+++ b/plat/qemu/qemu_common.c
@@ -131,7 +131,7 @@
/* Define EL1 and EL3 variants of the function initialising the MMU */
#ifdef AARCH32
-DEFINE_CONFIGURE_MMU_EL(secure)
+DEFINE_CONFIGURE_MMU_EL(svc_mon)
#else
DEFINE_CONFIGURE_MMU_EL(el1)
DEFINE_CONFIGURE_MMU_EL(el3)
diff --git a/plat/qemu/qemu_private.h b/plat/qemu/qemu_private.h
index 0fb7cd5..88b93da 100644
--- a/plat/qemu/qemu_private.h
+++ b/plat/qemu/qemu_private.h
@@ -11,7 +11,7 @@
#include "../../bl1/bl1_private.h"
-void qemu_configure_mmu_secure(unsigned long total_base,
+void qemu_configure_mmu_svc_mon(unsigned long total_base,
unsigned long total_size,
unsigned long code_start, unsigned long code_limit,
unsigned long ro_start, unsigned long ro_limit,
diff --git a/plat/qemu/sp_min/sp_min_setup.c b/plat/qemu/sp_min/sp_min_setup.c
index fd8fa1c..5b98079 100644
--- a/plat/qemu/sp_min/sp_min_setup.c
+++ b/plat/qemu/sp_min/sp_min_setup.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
@@ -108,9 +107,10 @@
return NULL;
}
-void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2)
+void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+ bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
/* Initialize the console to provide early debug support */
console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
@@ -142,7 +142,7 @@
void sp_min_plat_arch_setup(void)
{
- qemu_configure_mmu_secure(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
+ qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
BL32_RO_BASE, BL32_RO_LIMIT,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c
index 25eab43..9a74314 100644
--- a/plat/rockchip/common/aarch64/platform_common.c
+++ b/plat/rockchip/common/aarch64/platform_common.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <bl_common.h>
#include <cci.h>
#include <debug.h>
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index e5ee68f..b8ec8c1 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
@@ -61,10 +60,12 @@
* BL2 has flushed this information to memory, so we are guaranteed to pick up
* good data.
******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
static console_16550_t console;
+ struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
+ void *plat_params_from_bl2 = (void *) arg1;
params_early_setup(plat_params_from_bl2);
@@ -82,13 +83,13 @@
VERBOSE("bl31_setup\n");
/* Passing a NULL context is a critical programming error */
- assert(from_bl2);
+ assert(arg_from_bl2);
- assert(from_bl2->h.type == PARAM_BL31);
- assert(from_bl2->h.version >= VERSION_1);
+ assert(arg_from_bl2->h.type == PARAM_BL31);
+ assert(arg_from_bl2->h.version >= VERSION_1);
- bl32_ep_info = *from_bl2->bl32_ep_info;
- bl33_ep_info = *from_bl2->bl33_ep_info;
+ bl32_ep_info = *arg_from_bl2->bl32_ep_info;
+ bl33_ep_info = *arg_from_bl2->bl33_ep_info;
}
/*******************************************************************************
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 5456773..e1e4f33 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -28,6 +28,14 @@
extern uint32_t __sram_incbin_start, __sram_incbin_end;
extern uint32_t __sram_incbin_real_end;
+struct rockchip_bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+};
/******************************************************************************
* The register have write-mask bits, it is mean, if you want to set the bits,
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index 3dac013..a7ba83e 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -4,7 +4,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 991fe6c..d91ee0e 100644
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -48,5 +48,5 @@
#endif
bl sram_restore
sys_resume:
- bl psci_entrypoint
+ bl bl31_warm_entrypoint
endfunc pmu_cpuson_entrypoint
diff --git a/plat/rockchip/common/rockchip_gicv2.c b/plat/rockchip/common/rockchip_gicv2.c
index afdc6aa..4705042 100644
--- a/plat/rockchip/common/rockchip_gicv2.c
+++ b/plat/rockchip/common/rockchip_gicv2.c
@@ -6,6 +6,7 @@
#include <bl_common.h>
#include <gicv2.h>
+#include <interrupt_props.h>
#include <platform_def.h>
#include <utils.h>
@@ -23,8 +24,8 @@
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
*****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
- PLAT_RK_G1S_IRQS,
+static const interrupt_prop_t g0_interrupt_props[] = {
+ PLAT_RK_GICV2_G1S_IRQS
};
/*
@@ -35,8 +36,8 @@
gicv2_driver_data_t rockchip_gic_data = {
.gicd_base = PLAT_RK_GICD_BASE,
.gicc_base = PLAT_RK_GICC_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
};
/******************************************************************************
diff --git a/plat/rockchip/common/rockchip_gicv3.c b/plat/rockchip/common/rockchip_gicv3.c
index 0500da6..efbf1d1 100644
--- a/plat/rockchip/common/rockchip_gicv3.c
+++ b/plat/rockchip/common/rockchip_gicv3.c
@@ -6,6 +6,7 @@
#include <bl_common.h>
#include <gicv3.h>
+#include <interrupt_props.h>
#include <platform.h>
#include <platform_def.h>
#include <utils.h>
@@ -23,16 +24,11 @@
/* The GICv3 driver only needs to be initialized in EL3 */
uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
-/* Array of Group1 secure interrupts to be configured by the gic driver */
-const unsigned int g1s_interrupt_array[] = {
- PLAT_RK_G1S_IRQS
+static const interrupt_prop_t g01s_interrupt_props[] = {
+ PLAT_RK_GICV3_G0_IRQS,
+ PLAT_RK_GICV3_G1S_IRQS
};
-/* Array of Group0 interrupts to be configured by the gic driver */
-const unsigned int g0_interrupt_array[] = {
- PLAT_RK_G0_IRQS
-};
-
static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
{
return (unsigned int)plat_core_pos_by_mpidr(mpidr);
@@ -41,10 +37,8 @@
const gicv3_driver_data_t rockchip_gic_data = {
.gicd_base = PLAT_RK_GICD_BASE,
.gicr_base = PLAT_RK_GICR_BASE,
- .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
- .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
- .g0_interrupt_array = g0_interrupt_array,
- .g1s_interrupt_array = g1s_interrupt_array,
+ .interrupt_props = g01s_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos,
diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h
index 56d51ee..9b20b41 100644
--- a/plat/rockchip/rk3328/include/platform_def.h
+++ b/plat/rockchip/rk3328/include/platform_def.h
@@ -11,8 +11,6 @@
#include <common_def.h>
#include <rk3328_def.h>
-#define DEBUG_XLAT_TABLE 0
-
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
@@ -24,9 +22,7 @@
******************************************************************************/
/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
@@ -85,7 +81,8 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define MAX_XLAT_TABLES 9
#define MAX_MMAP_REGIONS 33
@@ -107,13 +104,6 @@
#define PLAT_RK_GICD_BASE RK3328_GICD_BASE
#define PLAT_RK_GICC_BASE RK3328_GICC_BASE
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_RK_G1S_IRQS RK_G1S_IRQS
-
#define PLAT_RK_UART_BASE RK3328_UART2_BASE
#define PLAT_RK_UART_CLOCK RK3328_UART_CLOCK
#define PLAT_RK_UART_BAUDRATE RK3328_BAUDRATE
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index f0fd36f..560ccca 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -27,13 +27,14 @@
plat/common/plat_gicv2.c \
${RK_PLAT}/common/rockchip_gicv2.c
-PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
- plat/common/aarch64/plat_psci_common.c
+PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
+ plat/common/plat_psci_common.c
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
- drivers/console/console.S \
- drivers/ti/uart/16550_console.S \
+ drivers/console/aarch64/console.S \
+ drivers/ti/uart/aarch64/16550_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/aem_generic.S \
@@ -48,7 +49,6 @@
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
-ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
include lib/coreboot/coreboot.mk
diff --git a/plat/rockchip/rk3328/rk3328_def.h b/plat/rockchip/rk3328/rk3328_def.h
index 062c9cc..035fcb6 100644
--- a/plat/rockchip/rk3328/rk3328_def.h
+++ b/plat/rockchip/rk3328/rk3328_def.h
@@ -135,7 +135,11 @@
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
-#define RK_G1S_IRQS RK_IRQ_SEC_PHY_TIMER, RK_IRQ_SEC_SGI_6
+#define PLAT_RK_GICV2_G1S_IRQS \
+ INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
#define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/
#define SHARE_MEM_PAGE_NUM 15
diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h
index d9a80a7..4083938 100644
--- a/plat/rockchip/rk3368/include/platform_def.h
+++ b/plat/rockchip/rk3368/include/platform_def.h
@@ -12,8 +12,6 @@
#include <rk3368_def.h>
#include <utils_def.h>
-#define DEBUG_XLAT_TABLE 0
-
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
@@ -25,9 +23,7 @@
******************************************************************************/
/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
@@ -86,7 +82,8 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define MAX_XLAT_TABLES 8
#define MAX_MMAP_REGIONS 16
@@ -108,13 +105,6 @@
#define PLAT_RK_GICD_BASE RK3368_GICD_BASE
#define PLAT_RK_GICC_BASE RK3368_GICC_BASE
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_RK_G1S_IRQS RK_G1S_IRQS
-
#define PLAT_RK_UART_BASE RK3368_UART2_BASE
#define PLAT_RK_UART_CLOCK RK3368_UART_CLOCK
#define PLAT_RK_UART_BAUDRATE RK3368_BAUDRATE
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index 7ecb21a..050a2c4 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -48,7 +48,6 @@
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c \
-ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
include lib/coreboot/coreboot.mk
diff --git a/plat/rockchip/rk3368/rk3368_def.h b/plat/rockchip/rk3368/rk3368_def.h
index 7cb82da..9ebe3be 100644
--- a/plat/rockchip/rk3368/rk3368_def.h
+++ b/plat/rockchip/rk3368/rk3368_def.h
@@ -100,6 +100,8 @@
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
-#define RK_G1S_IRQS (RK_IRQ_SEC_PHY_TIMER)
+#define PLAT_RK_GICV2_G1S_IRQS \
+ INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ GICV2_INTR_GROUP1, GIC_INTR_CFG_LEVEL)
#endif /* __PLAT_DEF_H__ */
diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h
index 26204a1..cb798fb 100644
--- a/plat/rockchip/rk3399/include/platform_def.h
+++ b/plat/rockchip/rk3399/include/platform_def.h
@@ -13,8 +13,6 @@
#include <rk3399_def.h>
#include <utils_def.h>
-#define DEBUG_XLAT_TABLE 0
-
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
@@ -26,9 +24,7 @@
******************************************************************************/
/* Size of cacheable stacks */
-#if DEBUG_XLAT_TABLE
-#define PLATFORM_STACK_SIZE 0x800
-#elif defined(IMAGE_BL1)
+#if defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
@@ -69,7 +65,8 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
-#define ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define MAX_XLAT_TABLES 20
#define MAX_MMAP_REGIONS 25
@@ -92,14 +89,6 @@
#define PLAT_RK_GICR_BASE BASE_GICR_BASE
#define PLAT_RK_GICC_BASE 0
-/*
- * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS
-#define PLAT_RK_G0_IRQS RK3399_G0_IRQS
-
#define PLAT_RK_UART_BASE UART2_BASE
#define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK
#define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index fc386f0..9120419 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -65,7 +65,6 @@
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c \
${RK_PLAT_SOC}/drivers/dram/suspend.c
-ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
include lib/coreboot/coreboot.mk
diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h
index 9fc0809..32e439e 100644
--- a/plat/rockchip/rk3399/rk3399_def.h
+++ b/plat/rockchip/rk3399/rk3399_def.h
@@ -54,7 +54,12 @@
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
-#define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER
-#define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6
+#define PLAT_RK_GICV3_G1S_IRQS \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ INTR_GROUP1S, GIC_INTR_CFG_LEVEL)
+
+#define PLAT_RK_GICV3_G0_IRQS \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ INTR_GROUP0, GIC_INTR_CFG_LEVEL)
#endif /* __PLAT_DEF_H__ */
diff --git a/plat/rpi3/platform.mk b/plat/rpi3/platform.mk
index d6d0d56..a7b0991 100644
--- a/plat/rpi3/platform.mk
+++ b/plat/rpi3/platform.mk
@@ -85,9 +85,6 @@
WORKAROUND_CVE_2017_5715 := 0
-# Disable the PSCI platform compatibility layer by default
-ENABLE_PLAT_COMPAT := 0
-
# Disable stack protector by default
ENABLE_STACK_PROTECTOR := 0
@@ -100,9 +97,6 @@
# Use Coherent memory
USE_COHERENT_MEM := 1
-# Enable new version of image loading
-LOAD_IMAGE_V2 := 1
-
# Use multi console API
MULTI_CONSOLE_API := 1
@@ -142,10 +136,6 @@
endif
endif
-ifneq (${LOAD_IMAGE_V2}, 1)
- $(error Error: rpi3 needs LOAD_IMAGE_V2=1)
-endif
-
ifneq (${MULTI_CONSOLE_API}, 1)
$(error Error: rpi3 needs MULTI_CONSOLE_API=1)
endif
@@ -182,8 +172,6 @@
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
- USE_TBBR_DEFS := 1
-
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 96427a1..1bee20a 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -5,7 +5,6 @@
#
override RESET_TO_BL31 := 1
-override ENABLE_PLAT_COMPAT := 0
override MULTI_CONSOLE_API := 1
override PROGRAMMABLE_RESET_ADDRESS := 1
override USE_COHERENT_MEM := 1
@@ -28,7 +27,7 @@
-I$(PLAT_PATH)/drivers/mhu
PLAT_BL_COMMON_SOURCES += $(PLAT_PATH)/sq_helpers.S \
- drivers/arm/pl011/pl011_console.S \
+ drivers/arm/pl011/aarch64/pl011_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${XLAT_TABLES_LIB_SRCS}
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index 26b8ff1..07c1f89 100644
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -55,8 +55,8 @@
return spsr;
}
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
/* Initialize the console to provide early debug support */
(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
@@ -67,8 +67,8 @@
CONSOLE_FLAG_RUNTIME);
/* There are no parameters from BL2 if BL31 is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
+ assert(arg0 == 0U);
+ assert(arg1 == 0U);
/* Initialize power controller before setting up topology */
plat_sq_pwrc_setup();
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 6de5164..e7a1bfe 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -6,11 +6,8 @@
override BL2_AT_EL3 := 1
override COLD_BOOT_SINGLE_CPU := 1
-override ENABLE_PLAT_COMPAT := 0
-override LOAD_IMAGE_V2 := 1
override PROGRAMMABLE_RESET_ADDRESS := 1
override USE_COHERENT_MEM := 1
-override USE_TBBR_DEFS := 1
override ENABLE_SVE_FOR_NS := 0
# Cortex-A53 revision r0p4-51rel0
diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c
index 9e28eec..c5acdbd 100644
--- a/plat/socionext/uniphier/uniphier_bl31_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl31_setup.c
@@ -28,8 +28,13 @@
return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
}
-void bl31_early_platform_setup(void *from_bl2, void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
+ void *from_bl2;
+
+ from_bl2 = (void *) arg0;
+
bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
uniphier_console_setup();
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 3f938d9..30b2932 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -6,9 +6,7 @@
ARM_CORTEX_A7 := yes
ARM_WITH_NEON := yes
-LOAD_IMAGE_V2 := 1
BL2_AT_EL3 := 1
-ENABLE_PLAT_COMPAT := 0
USE_COHERENT_MEM := 0
STM32_TF_VERSION ?= 0
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index 1329bdb..56598c8 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
-#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index 2d4d1c2..f84b9d4 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -57,12 +57,12 @@
* Perform any BL3-1 early platform setup, such as console init and deciding on
* memory layout.
******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
/* There are no parameters from BL2 if BL31 is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
+ assert(arg0 == 0U);
+ assert(arg1 == 0U);
bl31_console_setup();
@@ -95,12 +95,6 @@
#endif
}
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- bl31_early_platform_setup((void *)arg0, (void *)arg1);
-}
-
void bl31_plat_arch_setup(void)
{
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 446d8af..3148178 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -15,9 +15,6 @@
WARMBOOT_ENABLE_DCACHE_EARLY:= 1
USE_COHERENT_MEM := 0
-ERROR_DEPRECATED := 1
-ENABLE_PLAT_COMPAT := 0
-
# A53 erratum for SoC. (enable them all)
ERRATA_A53_826319 := 1
ERRATA_A53_835769 := 1
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index abfb8c6..02f1811 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -54,8 +54,8 @@
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables.
*/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
- void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
/* Initialize the console to provide early debug support */
console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(),
@@ -65,8 +65,8 @@
zynqmp_config_setup();
/* There are no parameters from BL2 if BL31 is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
+ assert(arg0 == 0U);
+ assert(arg1 == 0U);
/*
* Do initial security configuration to allow DRAM/device access. On
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index f806d46..53d93c3 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -4,7 +4,6 @@
# SPDX-License-Identifier: BSD-3-Clause
override ERRATA_A53_855873 := 1
-override ENABLE_PLAT_COMPAT := 0
override PROGRAMMABLE_RESET_ADDRESS := 1
PSCI_EXTENDED_STATE_ID := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
diff --git a/readme.rst b/readme.rst
index 26e1fde..f2a7a00 100644
--- a/readme.rst
+++ b/readme.rst
@@ -1,4 +1,4 @@
-Trusted Firmware-A - version 1.5
+Trusted Firmware-A - version 2.0
================================
Trusted Firmware-A (TF-A) provides a reference implementation of secure world
@@ -136,6 +136,11 @@
- Support for the GCC, LLVM and Arm Compiler 6 toolchains.
+- Support combining several libraries into a self-called "romlib" image, that
+ may be shared across images to reduce memory footprint. The romlib image
+ is stored in ROM but is accessed through a jump-table that may be stored
+ in read-write memory, allowing for the library code to be patched.
+
For a full description of functionality and implementation details, please
see the `Firmware Design`_ and supporting documentation. The `Change Log`_
provides details of changes made since the last release.
@@ -147,34 +152,35 @@
r0, r1 and r2 of the `Juno Arm Development Platform`_.
Various AArch64 builds of this release have been tested on the following Arm
-Fixed Virtual Platforms (`FVP`_) without shifted affinities, and that do not
+Fixed Virtual Platforms (`FVP`_) without shifted affinities that do not
support threaded CPU cores (64-bit host machine only):
-NOTE: Unless otherwise stated, the FVP Version is 11.2 Build 11.2.33.
+NOTE: Unless otherwise stated, the model version is Version 11.4 Build 37.
-- ``Foundation_Platform``
-- ``FVP_Base_AEMv8A-AEMv8A`` (and also Version 9.0, Build 0.8.9005)
+- ``FVP_Base_Aresx4``
+- ``FVP_Base_AEMv8A-AEMv8A``
+- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
+- ``FVP_Base_AEMv8A-AEMv8A``
+- ``FVP_Base_RevC-2xAEMv8A``
+- ``FVP_Base_Cortex-A32x4``
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
+- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
+- ``FVP_Base_Cortex-A55x4``
- ``FVP_Base_Cortex-A57x4-A53x4``
- ``FVP_Base_Cortex-A57x4``
- ``FVP_Base_Cortex-A72x4-A53x4``
- ``FVP_Base_Cortex-A72x4``
- ``FVP_Base_Cortex-A73x4-A53x4``
- ``FVP_Base_Cortex-A73x4``
-
-Additionally, various AArch64 builds were tested on the following Arm `FVP`_ s
-with shifted affinities, supporting threaded CPU cores (64-bit host machine
-only).
-
-- ``FVP_Base_Cortex-A55x4-A75x4`` (Version 0.0, build 0.0.4395)
-- ``FVP_Base_Cortex-A55x4`` (Version 0.0, build 0.0.4395)
-- ``FVP_Base_Cortex-A75x4`` (Version 0.0, build 0.0.4395)
-- ``FVP_Base_RevC-2xAEMv8A``
+- ``FVP_Base_Cortex-A75x4``
+- ``FVP_Base_Cortex-A76x4``
+- ``FVP_CSS_SGI-575`` (Version 11.3 build 40)
+- ``Foundation_Platform``
-Various AArch32 builds of this release has been tested on the following Arm
-`FVP`_\ s without shifted affinities, and that do not support threaded CPU cores
-(64-bit host machine only):
+The latest version of the AArch32 build of TF-A has been tested on the following
+Arm FVPs without shifted affinities that do not support threaded CPU cores
+(64-bit host machine only).
- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_Cortex-A32x4``
@@ -182,17 +188,22 @@
The Foundation FVP can be downloaded free of charge. The Base FVPs can be
licensed from Arm. See the `Arm FVP website`_.
-All the above platforms have been tested with `Linaro Release 17.10`_.
+All the above platforms have been tested with `Linaro Release 18.04`_.
This release also contains the following platform support:
+- Allwinner sun50i_64 and sun50i_h6
+- ARM SGI-575 and SGM-775
- HiKey, HiKey960 and Poplar boards
+- Marvell Armada 8K
- MediaTek MT6795 and MT8173 SoCs
- NVidia T132, T186 and T210 SoCs
+- NXP QorIQ LS1043A, i.MX8QX, i.MX8QM and i.MX7Solo WaRP7
- QEMU emulator
- Raspberry Pi 3 board
- RockChip RK3328, RK3368 and RK3399 SoCs
- Socionext UniPhier SoC family and SynQuacer SC2A11 SoCs
+- STMicroelectronics STM32MP1
- Texas Instruments K3 SoCs
- Xilinx Zynq UltraScale + MPSoC
@@ -201,7 +212,7 @@
- More platform support.
-- Improved dynamic configuration support.
+- Position independent executable (PIE) support.
- Ongoing support for new architectural features, CPUs and System IP.
@@ -262,7 +273,7 @@
.. _Juno Arm Development Platform: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php
.. _Arm FVP website: FVP_
.. _FVP: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 17.10: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease17.10
+.. _Linaro Release 18.04: https://community.arm.com/dev-platforms/b/documents/posts/linaro-release-notes-deprecated#LinaroRelease18.04
.. _OP-TEE Secure OS: https://github.com/OP-TEE/optee_os
.. _NVidia Trusted Little Kernel: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary
.. _Trusty Secure OS: https://source.android.com/security/trusty
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index cc808e2..3335836 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -322,7 +322,7 @@
fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE)));
cm_set_next_eret_context(NON_SECURE);
- return 0;
+ return 1;
}
static void trusty_cpu_suspend(uint32_t off)
diff --git a/services/spd/tspd/tspd.mk b/services/spd/tspd/tspd.mk
index 0747e15..1457360 100644
--- a/services/spd/tspd/tspd.mk
+++ b/services/spd/tspd/tspd.mk
@@ -33,16 +33,6 @@
# generated while the code is executing in S-EL1/0.
TSP_NS_INTR_ASYNC_PREEMPT := 0
-# If TSPD_ROUTE_IRQ_TO_EL3 build flag is defined, use it to define value for
-# TSP_NS_INTR_ASYNC_PREEMPT for backward compatibility.
-ifdef TSPD_ROUTE_IRQ_TO_EL3
-ifeq (${ERROR_DEPRECATED},1)
-$(error "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
-endif
-$(warning "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT")
-TSP_NS_INTR_ASYNC_PREEMPT := ${TSPD_ROUTE_IRQ_TO_EL3}
-endif
-
ifeq ($(EL3_EXCEPTION_HANDLING),1)
ifeq ($(TSP_NS_INTR_ASYNC_PREEMPT),0)
$(error When EL3_EXCEPTION_HANDLING=1, TSP_NS_INTR_ASYNC_PREEMPT must also be 1)
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index e0e3923..9bdafe0 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -33,7 +33,7 @@
.PHONY: all clean distclean
-all: ${PROJECT} fip_create
+all: ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
@echo " LD $@"
@@ -42,13 +42,9 @@
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
-fip_create: fip_create.sh
- ${Q}mkdir -p ../fip_create
- ${Q}install -m 755 fip_create.sh ../fip_create/fip_create
-
%.o: %.c %.h Makefile
@echo " CC $<"
${Q}${HOSTCC} -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@
clean:
- $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS} fip_create)
+ $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS})
diff --git a/tools/fiptool/fip_create.sh b/tools/fiptool/fip_create.sh
deleted file mode 100644
index 0e80199..0000000
--- a/tools/fiptool/fip_create.sh
+++ /dev/null
@@ -1,127 +0,0 @@
-#!/bin/sh
-#
-# This script implements the old fip_create tool on top of
-# the new fiptool.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-usage() {
- cat << EOF
-This tool is used to create a Firmware Image Package.
-
-Usage:
- fip_create [options] FIP_FILENAME
-
-Options:
- -h,--help: Print this help message and exit
- -d,--dump: Print contents of FIP after update
- -u,--unpack: Unpack images from an existing FIP
- -f,--force: Overwrite existing files when unpacking images
-
-Components that can be added/updated:
- --scp-fwu-cfg FILENAME SCP Firmware Updater Configuration FWU SCP_BL2U
- --ap-fwu-cfg FILENAME AP Firmware Updater Configuration BL2U
- --fwu FILENAME Firmware Updater NS_BL2U
- --fwu-cert FILENAME Non-Trusted Firmware Updater certificate
- --tb-fw FILENAME Trusted Boot Firmware BL2
- --scp-fw FILENAME SCP Firmware SCP_BL2
- --soc-fw FILENAME EL3 Runtime Firmware BL31
- --tos-fw FILENAME Secure Payload BL32 (Trusted OS)
- --tos-fw-extra1 FILENAME Secure Payload BL32 Extra1 (Trusted OS Extra1)
- --tos-fw-extra2 FILENAME Secure Payload BL32 Extra2 (Trusted OS Extra2)
- --nt-fw FILENAME Non-Trusted Firmware BL33
- --rot-cert FILENAME Root Of Trust key certificate
- --trusted-key-cert FILENAME Trusted key certificate
- --scp-fw-key-cert FILENAME SCP Firmware key certificate
- --soc-fw-key-cert FILENAME SoC Firmware key certificate
- --tos-fw-key-cert FILENAME Trusted OS Firmware key certificate
- --nt-fw-key-cert FILENAME Non-Trusted Firmware key certificate
- --tb-fw-cert FILENAME Trusted Boot Firmware BL2 certificate
- --scp-fw-cert FILENAME SCP Firmware content certificate
- --soc-fw-cert FILENAME SoC Firmware content certificate
- --tos-fw-cert FILENAME Trusted OS Firmware content certificate
- --nt-fw-cert FILENAME Non-Trusted Firmware content certificate
-EOF
- exit
-}
-
-echo "!! The fip_create tool is deprecated. Use the new fiptool. !!"
-basedir="$(dirname $0)/../fiptool"
-fiptool_args=
-while :; do
- case "$1" in
- -h | --help )
- usage
- break ;;
- -d | --dump )
- fiptool_args="info $fiptool_args"
- shift ;;
- -u | --unpack )
- fiptool_args="unpack $fiptool_args"
- shift ;;
- -f | --force )
- fiptool_args="$fiptool_args --force"
- shift ;;
- --scp-fwu-cfg | \
- --ap-fwu-cfg | \
- --fwu | \
- --fwu-cert | \
- --tb-fw | \
- --scp-fw | \
- --soc-fw | \
- --tos-fw | \
- --tos-fw-extra1 | \
- --tos-fw-extra2 | \
- --nt-fw | \
- --rot-cert | \
- --trusted-key-cert | \
- --scp-fw-key-cert | \
- --soc-fw-key-cert | \
- --tos-fw-key-cert | \
- --nt-fw-key-cert | \
- --tb-fw-cert | \
- --scp-fw-cert | \
- --soc-fw-cert | \
- --tos-fw-cert | \
- --nt-fw-cert )
- fiptool_args="$fiptool_args $1"
- shift
- if test -z $1; then
- usage
- fi
- fiptool_args="$fiptool_args $1"
- shift ;;
- * )
- break ;;
- esac
-done
-
-# expect a FIP filename
-if test -z $1; then
- usage
-fi
-
-is_pack_cmd=1
-for arg in $fiptool_args; do
- case "$arg" in
- unpack )
- is_pack_cmd=0
- break ;;
- info )
- is_pack_cmd=0
- break ;;
- * )
- esac
-done
-
-# if --unpack and --dump were not specified
-# the default action is to pack
-if test "$is_pack_cmd" -eq 1; then
- fiptool_args="update $fiptool_args"
-fi
-
-# append FIP filename
-fiptool_args="$fiptool_args $1"
-echo "Invoking fiptool with args: $fiptool_args"
-"$basedir/fiptool" $fiptool_args