commit a7f549423e8e9d9716dff4f506326a0c8236f840
author Jit Loon Lim <jit.loon.lim@intel.com> Wed May 17 12:26:11 2023 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> Wed Jul 05 10:11:11 2023 +0800
tree 546d2f87ce15572f317285407ead54412bf33bf5
parent 55bf238b06bfc71e20a14282c367b6b2cd80525c

feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA

This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
	1. Added SDMMC/NAND/COMBO-PHY support.
	2. Updated product name -> Agilex5
	3. Updated QSPI base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6

plat/intel/soc/common/socfpga_storage.c

diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index ac7a9da..e80f074 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -22,6 +22,7 @@
 #include <lib/mmio.h>
 #include <tools_share/firmware_image_package.h>
 
+#include "drivers/sdmmc/sdmmc.h"
 #include "socfpga_private.h"
 
 
@@ -144,8 +145,8 @@
 		register_io_dev = &register_io_dev_block;
 		boot_dev_spec.buffer.offset	= PLAT_MMC_DATA_BASE;
 		boot_dev_spec.buffer.length	= SOCFPGA_MMC_BLOCK_SIZE;
-		boot_dev_spec.ops.read		= mmc_read_blocks;
-		boot_dev_spec.ops.write		= mmc_write_blocks;
+		boot_dev_spec.ops.read		= SDMMC_READ_BLOCKS;
+		boot_dev_spec.ops.write		= SDMMC_WRITE_BLOCKS;
 		boot_dev_spec.block_size	= MMC_BLOCK_SIZE;
 		break;