Merge "fix(qemu): allocate space for GPT bitlock" into integration
diff --git a/Makefile b/Makefile
index d73fc87..bbde1a7 100644
--- a/Makefile
+++ b/Makefile
@@ -24,6 +24,7 @@
MAKE_HELPERS_DIRECTORY := make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
################################################################################
# Default values for build configurations, and their dependencies
@@ -93,23 +94,10 @@
# Process build options
################################################################################
-# Verbose flag
-ifeq (${V},0)
- Q:=@
- ECHO:=@echo
+ifeq ($(verbose),)
CHECKCODE_ARGS += --no-summary --terse
-else
- Q:=
- ECHO:=$(ECHO_QUIET)
-endif
-
-ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),)
- Q:=@
- ECHO:=$(ECHO_QUIET)
endif
-export Q ECHO
-
################################################################################
# Auxiliary tools (fiptool, cert_create, etc)
################################################################################
@@ -1477,7 +1465,7 @@
all: msg_start
msg_start:
- @echo "Building ${PLAT}"
+ $(s)echo "Building ${PLAT}"
ifeq (${ERROR_DEPRECATED},0)
# Check if deprecated declarations and cpp warnings should be treated as error or not.
@@ -1573,11 +1561,11 @@
# Add Secure Partition packages
ifeq (${NEED_SP_PKG},yes)
$(BUILD_PLAT)/sp_gen.mk: ${SP_MK_GEN} ${SP_LAYOUT_FILE} | ${BUILD_PLAT}
- @${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} ${SP_DTS_LIST_FRAGMENT}
+ $(q)${PYTHON} "$<" "$@" $(filter-out $<,$^) $(BUILD_PLAT) ${COT} ${SP_DTS_LIST_FRAGMENT}
sp: $(DTBS) $(BUILD_PLAT)/sp_gen.mk $(SP_PKGS)
- @${ECHO_BLANK_LINE}
- @echo "Built SP Images successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo
+ $(s)echo "Built SP Images successfully"
+ $(s)echo
endif #(NEED_SP_PKG)
locate-checkpatch:
@@ -1590,37 +1578,37 @@
endif #(CHECKPATCH)
clean:
- @echo " CLEAN"
+ $(s)echo " CLEAN"
$(call SHELL_REMOVE_DIR,${BUILD_PLAT})
ifdef UNIX_MK
- ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+ $(q)${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) clean
+ $(q)set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) clean
endif #(UNIX_MK)
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
- ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
+ $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+ $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
+ $(q)${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
realclean distclean:
- @echo " REALCLEAN"
+ $(s)echo " REALCLEAN"
$(call SHELL_REMOVE_DIR,${BUILD_BASE})
$(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*)
ifdef UNIX_MK
- ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+ $(q)${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean
+ $(q)set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean
endif #(UNIX_MK)
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean
- ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
+ $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean
+ $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean
+ $(q)${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
checkcodebase: locate-checkpatch
- @echo " CHECKING STYLE"
- @if test -d .git ; then \
+ $(s)echo " CHECKING STYLE"
+ $(q)if test -d .git ; then \
git ls-files | grep -E -v 'libfdt|libc|docs|\.rst' | \
while read GIT_FILE ; \
do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; \
@@ -1636,11 +1624,11 @@
fi
checkpatch: locate-checkpatch
- @echo " CHECKING STYLE"
- @if test -n "${CHECKPATCH_OPTS}"; then \
+ $(s)echo " CHECKING STYLE"
+ $(q)if test -n "${CHECKPATCH_OPTS}"; then \
echo " with ${CHECKPATCH_OPTS} option(s)"; \
fi
- ${Q}COMMON_COMMIT=$$(git merge-base HEAD ${BASE_COMMIT}); \
+ $(q)COMMON_COMMIT=$$(git merge-base HEAD ${BASE_COMMIT}); \
for commit in `git rev-list --no-merges $$COMMON_COMMIT..HEAD`; \
do \
printf "\n[*] Checking style of '$$commit'\n\n"; \
@@ -1655,44 +1643,44 @@
certtool: ${CRTTOOL}
${CRTTOOL}: FORCE
- ${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} CRTTOOL=${CRTTOOL} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${CRTTOOLPATH} all
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(q)${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} OPENSSL_DIR=${OPENSSL_DIR} CRTTOOL=${CRTTOOL} DEBUG=${DEBUG} --no-print-directory -C ${CRTTOOLPATH} all
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
ifneq (${GENERATE_COT},0)
certificates: ${CRT_DEPS} ${CRTTOOL}
- ${Q}${CRTTOOL} ${CRT_ARGS}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @echo "Certificates can be found in ${BUILD_PLAT}"
- @${ECHO_BLANK_LINE}
+ $(q)${CRTTOOL} ${CRT_ARGS}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo "Certificates can be found in ${BUILD_PLAT}"
+ $(s)echo
endif #(GENERATE_COT)
${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL}
$(eval ${CHECK_FIP_CMD})
- ${Q}${FIPTOOL} create ${FIP_ARGS} $@
- ${Q}${FIPTOOL} info $@
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(q)${FIPTOOL} create ${FIP_ARGS} $@
+ $(q)${FIPTOOL} info $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
ifneq (${GENERATE_COT},0)
fwu_certificates: ${FWU_CRT_DEPS} ${CRTTOOL}
- ${Q}${CRTTOOL} ${FWU_CRT_ARGS}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @echo "FWU certificates can be found in ${BUILD_PLAT}"
- @${ECHO_BLANK_LINE}
+ $(q)${CRTTOOL} ${FWU_CRT_ARGS}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo "FWU certificates can be found in ${BUILD_PLAT}"
+ $(s)echo
endif #(GENERATE_COT)
${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL}
$(eval ${CHECK_FWU_FIP_CMD})
- ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@
- ${Q}${FIPTOOL} info $@
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(q)${FIPTOOL} create ${FWU_FIP_ARGS} $@
+ $(q)${FIPTOOL} info $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
fiptool: ${FIPTOOL}
fip: ${BUILD_PLAT}/${FIP_NAME}
@@ -1700,85 +1688,85 @@
${FIPTOOL}: FORCE
ifdef UNIX_MK
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${FIPTOOLPATH} all
+ $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} --no-print-directory -C ${FIPTOOLPATH} all
else
# Clear the MAKEFLAGS as we do not want
# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
+ $(q)set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
endif #(UNIX_MK)
romlib.bin: libraries FORCE
- ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
+ $(q)${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES=$(call escape-shell,$(INCLUDES)) DEFINES=$(call escape-shell,$(DEFINES)) --no-print-directory -C ${ROMLIBPATH} all
memmap: all
ifdef UNIX_MK
- ${Q}PYTHONPATH=${CURDIR}/tools/memory \
+ $(q)PYTHONPATH=${CURDIR}/tools/memory \
${PYTHON} -m memory.memmap -sr ${BUILD_PLAT}
else
- ${Q}set PYTHONPATH=${CURDIR}/tools/memory && \
+ $(q)set PYTHONPATH=${CURDIR}/tools/memory && \
${PYTHON} -m memory.memmap -sr ${BUILD_PLAT}
endif
doc:
- @echo " BUILD DOCUMENTATION"
- ${Q}${MAKE} --no-print-directory -C ${DOCS_PATH} html
+ $(s)echo " BUILD DOCUMENTATION"
+ $(q)${MAKE} --no-print-directory -C ${DOCS_PATH} html
enctool: ${ENCTOOL}
${ENCTOOL}: FORCE
- ${Q}${MAKE} PLAT=${PLAT} BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} ENCTOOL=${ENCTOOL} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${ENCTOOLPATH} all
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(q)${MAKE} PLAT=${PLAT} BUILD_INFO=0 OPENSSL_DIR=${OPENSSL_DIR} ENCTOOL=${ENCTOOL} DEBUG=${DEBUG} --no-print-directory -C ${ENCTOOLPATH} all
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
cscope:
- @echo " CSCOPE"
- ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
- ${Q}cscope -b -q -k
+ $(s)echo " CSCOPE"
+ $(q)find ${CURDIR} -name "*.[chsS]" > cscope.files
+ $(q)cscope -b -q -k
help:
- @echo "usage: ${MAKE} [PLAT=<platform>] [OPTIONS] [TARGET]"
- @echo ""
- @echo "PLAT is used to specify which platform you wish to build."
- @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
- @echo ""
- @echo "platform = ${PLATFORM_LIST}"
- @echo ""
- @echo "Please refer to the User Guide for a list of all supported options."
- @echo "Note that the build system doesn't track dependencies for build "
- @echo "options. Therefore, if any of the build options are changed "
- @echo "from a previous build, a clean build must be performed."
- @echo ""
- @echo "Supported Targets:"
- @echo " all Build all individual bootloader binaries"
- @echo " bl1 Build the BL1 binary"
- @echo " bl2 Build the BL2 binary"
- @echo " bl2u Build the BL2U binary"
- @echo " bl31 Build the BL31 binary"
- @echo " bl32 Build the BL32 binary. If ARCH=aarch32, then "
- @echo " this builds secure payload specified by AARCH32_SP"
- @echo " certificates Build the certificates (requires 'GENERATE_COT=1')"
- @echo " fip Build the Firmware Image Package (FIP)"
- @echo " fwu_fip Build the FWU Firmware Image Package (FIP)"
- @echo " checkcodebase Check the coding style of the entire source tree"
- @echo " checkpatch Check the coding style on changes in the current"
- @echo " branch against BASE_COMMIT (default origin/master)"
- @echo " clean Clean the build for the selected platform"
- @echo " cscope Generate cscope index"
- @echo " distclean Remove all build artifacts for all platforms"
- @echo " certtool Build the Certificate generation tool"
- @echo " enctool Build the Firmware encryption tool"
- @echo " fiptool Build the Firmware Image Package (FIP) creation tool"
- @echo " sp Build the Secure Partition Packages"
- @echo " sptool Build the Secure Partition Package creation tool"
- @echo " dtbs Build the Device Tree Blobs (if required for the platform)"
- @echo " memmap Print the memory map of the built binaries"
- @echo " doc Build html based documentation using Sphinx tool"
- @echo ""
- @echo "Note: most build targets require PLAT to be set to a specific platform."
- @echo ""
- @echo "example: build all targets for the FVP platform:"
- @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
+ $(s)echo "usage: ${MAKE} [PLAT=<platform>] [OPTIONS] [TARGET]"
+ $(s)echo ""
+ $(s)echo "PLAT is used to specify which platform you wish to build."
+ $(s)echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ $(s)echo ""
+ $(s)echo "platform = ${PLATFORM_LIST}"
+ $(s)echo ""
+ $(s)echo "Please refer to the User Guide for a list of all supported options."
+ $(s)echo "Note that the build system doesn't track dependencies for build "
+ $(s)echo "options. Therefore, if any of the build options are changed "
+ $(s)echo "from a previous build, a clean build must be performed."
+ $(s)echo ""
+ $(s)echo "Supported Targets:"
+ $(s)echo " all Build all individual bootloader binaries"
+ $(s)echo " bl1 Build the BL1 binary"
+ $(s)echo " bl2 Build the BL2 binary"
+ $(s)echo " bl2u Build the BL2U binary"
+ $(s)echo " bl31 Build the BL31 binary"
+ $(s)echo " bl32 Build the BL32 binary. If ARCH=aarch32, then "
+ $(s)echo " this builds secure payload specified by AARCH32_SP"
+ $(s)echo " certificates Build the certificates (requires 'GENERATE_COT=1')"
+ $(s)echo " fip Build the Firmware Image Package (FIP)"
+ $(s)echo " fwu_fip Build the FWU Firmware Image Package (FIP)"
+ $(s)echo " checkcodebase Check the coding style of the entire source tree"
+ $(s)echo " checkpatch Check the coding style on changes in the current"
+ $(s)echo " branch against BASE_COMMIT (default origin/master)"
+ $(s)echo " clean Clean the build for the selected platform"
+ $(s)echo " cscope Generate cscope index"
+ $(s)echo " distclean Remove all build artifacts for all platforms"
+ $(s)echo " certtool Build the Certificate generation tool"
+ $(s)echo " enctool Build the Firmware encryption tool"
+ $(s)echo " fiptool Build the Firmware Image Package (FIP) creation tool"
+ $(s)echo " sp Build the Secure Partition Packages"
+ $(s)echo " sptool Build the Secure Partition Package creation tool"
+ $(s)echo " dtbs Build the Device Tree Blobs (if required for the platform)"
+ $(s)echo " memmap Print the memory map of the built binaries"
+ $(s)echo " doc Build html based documentation using Sphinx tool"
+ $(s)echo ""
+ $(s)echo "Note: most build targets require PLAT to be set to a specific platform."
+ $(s)echo ""
+ $(s)echo "example: build all targets for the FVP platform:"
+ $(s)echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
.PHONY: FORCE
FORCE:;
diff --git a/changelog.yaml b/changelog.yaml
index 7d8760e..6a235cd 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -677,6 +677,13 @@
- plat/zynqmp
- plat/xilinx/zynqmp
+ - title: AMD
+ scope: amd
+
+ subsections:
+ - title: Versal Gen 2
+ scope: versal2
+
- title: Nuvoton
scope: nuvoton
@@ -1139,6 +1146,9 @@
- title: TRDC
scope: imx-trdc
+ - title: Clock
+ scope: nxp-clk
+
- title: Renesas
scope: renesas-drivers
@@ -1406,6 +1416,9 @@
- title: Certificate Creation Tool
scope: cert-create
+ - title: Firmware Encryption Tool
+ scope: encrypt-fw
+
- title: Memory Mapping Tool
scope: memmap
diff --git a/common/bl_common.c b/common/bl_common.c
index fe4de0a..2a9f32f 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -211,18 +211,18 @@
{
int err;
-/*
- * All firmware banks should be part of the same non-volatile storage as per
- * PSA FWU specification, hence don't check for any alternate boot source
- * when PSA FWU is enabled.
- */
-#if PSA_FWU_SUPPORT
- err = load_auth_image_internal(image_id, image_data);
-#else
- do {
+ if ((plat_try_img_ops == NULL) || (plat_try_img_ops->next_instance == NULL)) {
err = load_auth_image_internal(image_id, image_data);
- } while ((err != 0) && (plat_try_next_boot_source() != 0));
-#endif /* PSA_FWU_SUPPORT */
+ } else {
+ do {
+ err = load_auth_image_internal(image_id, image_data);
+ if (err != 0) {
+ if (plat_try_img_ops->next_instance(image_id) != 0) {
+ return err;
+ }
+ }
+ } while (err != 0);
+ }
if (err == 0) {
/*
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 09088c9..8e3e3dd 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -289,7 +289,7 @@
* revisions so that we catch them as they come along
*/
check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
- "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P7);
+ "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P8);
/* v8.1 features */
check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), "PAN", 1, 3);
diff --git a/docs/Makefile b/docs/Makefile
index 5bc24db..9fd7d76 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -1,11 +1,13 @@
#
-# Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+# Copyright (c) 2019-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Minimal makefile for Sphinx documentation
#
+include ../make_helpers/common.mk
+
# You can set these variables from the command line.
SPHINXOPTS = -W
SPHINXBUILD = sphinx-build
@@ -13,20 +15,13 @@
SOURCEDIR = .
BUILDDIR = build
-V ?= 0
-ifeq ($(V),0)
- Q := @
-else
- Q :=
-endif
-
# Put it first so that "make" without argument is like "make help".
help:
- ${Q}$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+ $(q)$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
.PHONY: help Makefile
# Catch-all target: route all unknown targets to Sphinx using the new
# "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS).
-%: Makefile
- ${Q}$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+.DEFAULT: Makefile
+ $(q)$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 85cc612..cbed72f 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -767,6 +767,7 @@
:|M|: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
:|G|: `gprocopciucnxp`_
:|F|: docs/plat/s32g274a.rst
+:|F|: drivers/nxp/clk/s32cc
:|F|: drivers/nxp/console/linflex_console.S
:|F|: include/drivers/nxp/console/linflex.h
:|F|: plat/nxp/s32
diff --git a/docs/plat/amd-versal2.rst b/docs/plat/amd-versal2.rst
new file mode 100644
index 0000000..876ab3c
--- /dev/null
+++ b/docs/plat/amd-versal2.rst
@@ -0,0 +1,87 @@
+AMD Versal Gen 2
+================
+
+Trusted Firmware-A implements the EL3 firmware layer for AMD Versal Gen 2.
+The platform only uses the runtime part of TF-A as AMD Versal Gen 2 already
+has a BootROM (BL1) and PMC FW (BL2).
+
+BL31 is TF-A.
+BL32 is an optional Secure Payload.
+BL33 is the non-secure world software (U-Boot, Linux etc).
+
+To build:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal2 bl31
+```
+
+To build TF-A for JTAG DCC console:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal2 CONSOLE=dcc bl31
+```
+
+To build TF-A with Errata management interface
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal2 bl31 ERRATA_ABI_SUPPORT=1
+```
+
+To build TF-A with IPI CRC check:
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal2 bl31 IPI_CRC_CHECK=1
+```
+
+AMD Versal Gen 2 platform specific build options
+-------------------------------------------------
+
+* `MEM_BASE`: Specifies the base address of the bl31 binary.
+* `MEM_SIZE`: Specifies the size of the memory region of the bl31 binary.
+* `BL32_MEM_BASE`: Specifies the base address of the bl32 binary.
+* `BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary.
+
+* `CONSOLE`: Select the console driver. Options:
+ - `pl011`, `pl011_0`: ARM pl011 UART 0 (default)
+ - `pl011_1` : ARM pl011 UART 1
+ - `dcc` : JTAG Debug Communication Channel(DCC)
+
+
+Reference DEN0028E SMC calling convention
+------------------------------------------
+
+Allocated subranges of Function Identifier to SIP services
+------------------------------------------------------------
+
++-----------------------+-------------------------------------------------------+
+| SMC Function | Identifier Service type |
++-----------------------+-------------------------------------------------------+
+| 0xC2000000-0xC200FFFF | Fast SMC64 SiP Service Calls as per SMCCC Section 6.1 |
++-----------------------+-------------------------------------------------------+
+
+IPI SMC call ranges
+-------------------
+
++---------------------------+-----------------------------------------------------------+
+| SMC Function Identifier | Service type |
++---------------------------+-----------------------------------------------------------+
+| 0xc2001000-0xc2001FFF | Fast SMC64 SiP Service call range used for AMD-Xilinx IPI |
++---------------------------+-----------------------------------------------------------+
+
+PM SMC call ranges
+------------------
+
++---------------------------+---------------------------------------------------------------------------+
+| SMC Function Identifier | Service type |
++---------------------------+---------------------------------------------------------------------------+
+| 0xc2000000-0xc2000FFF | Fast SMC64 SiP Service call range used for AMD-Xilinx Platform Management |
++---------------------------+---------------------------------------------------------------------------+
+
+SMC function IDs for SiP Service queries
+----------------------------------------
+
++--------------+--------------+--------------+
+| Service | Call UID | Revision |
++--------------+--------------+--------------+
+| SiP Service | 0x8200_FF01 | 0x8200_FF03 |
++--------------+--------------+--------------+
+
+Call UID Query – Returns a unique identifier of the service provider.
+
+Revision Query – Returns revision details of the service implementor.
diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index c805c78..5292d68 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -9,25 +9,21 @@
(64-bit host machine only).
.. note::
- The FVP models used are Version 11.22 Build 14, unless otherwise stated.
+ The FVP models used are Version 11.26 Build 11, unless otherwise stated.
-- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
-- ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMvA-AEMvA``
- ``FVP_Base_Cortex-A32x4``
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
- ``FVP_Base_Cortex-A55``
-- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
-- ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
- ``FVP_Base_Cortex-A57x1-A53x1``
- ``FVP_Base_Cortex-A57x2-A53x4``
- ``FVP_Base_Cortex-A57x4``
- ``FVP_Base_Cortex-A57x4-A53x4``
-- ``FVP_Base_Cortex-A65``
-- ``FVP_Base_Cortex-A65AE``
-- ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
+- ``FVP_Base_Cortex-A65`` (Version 11.24/24)
+- ``FVP_Base_Cortex-A65AE`` (Version 11.24/24)
+- ``FVP_Base_Cortex-A710``
- ``FVP_Base_Cortex-A72x4``
- ``FVP_Base_Cortex-A72x4-A53x4``
- ``FVP_Base_Cortex-A73x4``
@@ -39,15 +35,15 @@
- ``FVP_Base_Cortex-A78``
- ``FVP_Base_Cortex-A78AE``
- ``FVP_Base_Cortex-A78C``
-- ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
-- ``FVP_Base_Neoverse-E1``
+- ``FVP_Base_Cortex-X2``
+- ``FVP_Base_Neoverse-E1`` (Version 11.24/24)
- ``FVP_Base_Neoverse-N1``
+- ``FVP_Base_Neoverse-N2``
- ``FVP_Base_Neoverse-V1``
- ``FVP_Base_RevC-2xAEMv8A``
- ``FVP_BaseR_AEMv8R``
- ``FVP_Morello`` (Version 0.11/33)
- ``FVP_RD_V1``
-- ``FVP_TC1``
- ``FVP_TC2`` (Version 11.23/17)
The latest version of the AArch32 build of TF-A has been tested on the
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 5c1ded0..85c97e5 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -7,6 +7,7 @@
:hidden:
allwinner
+ amd-versal2
arm/index
ast2700
meson-axg
diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst
index a7600ec..5643ea1 100644
--- a/docs/porting-guide.rst
+++ b/docs/porting-guide.rst
@@ -1518,6 +1518,40 @@
- The function must not clobber x1, x2 and x3. It's also not safe to rely on
stack. Otherwise obey AAPCS.
+Struct: plat_try_images_ops [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This optional structure holds platform hooks for alternative images load.
+It has to be defined in platform code and registered by calling
+plat_setup_try_img_ops() function, passing it the address of the
+plat_try_images_ops struct.
+
+Function : plat_setup_try_img_ops [optional]
+............................................
+
+::
+
+ Argument : const struct plat_try_images_ops *
+ Return : void
+
+This optional function is called to register platform try images ops, given
+as argument.
+
+Function : plat_try_images_ops.next_instance [optional]
+.......................................................
+
+::
+
+ Argument : unsigned int image_id
+ Return : int
+
+This optional function tries to load images from alternative places.
+In case PSA FWU is not used, it can be any instance or media. If PSA FWU is
+used, it is mandatory that the backup image is on the same media.
+This is required for MTD devices like NAND.
+The argument is the ID of the image for which we are looking for an alternative
+place. It returns 0 in case of success and a negative errno value otherwise.
+
Modifications specific to a Boot Loader stage
---------------------------------------------
@@ -1607,9 +1641,6 @@
for performing any remaining platform-specific setup that can occur after the
MMU and data cache have been enabled.
-if support for multiple boot sources is required, it initializes the boot
-sequence used by plat_try_next_boot_source().
-
In Arm standard platforms, this function initializes the storage abstraction
layer used to load the next bootloader image.
@@ -1892,25 +1923,7 @@
This optional function performs any BL2 platform initialization
required before image loading, that is not done later in
-bl2_platform_setup(). Specifically, if support for multiple
-boot sources is required, it initializes the boot sequence used by
-plat_try_next_boot_source().
-
-Function : plat_try_next_boot_source() [optional]
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-::
-
- Argument : void
- Return : int
-
-This optional function passes to the next boot source in the redundancy
-sequence.
-
-This function moves the current boot redundancy source to the next
-element in the boot sequence. If there are no more boot sources then it
-must return 0, otherwise it must return 1. The default implementation
-of this always returns 0.
+bl2_platform_setup().
Boot Loader Stage 2 (BL2) at EL3
--------------------------------
diff --git a/drivers/arm/mhu/mhu_wrapper_v3_x.c b/drivers/arm/mhu/mhu_wrapper_v3_x.c
index b3d51e3..3efd701 100644
--- a/drivers/arm/mhu/mhu_wrapper_v3_x.c
+++ b/drivers/arm/mhu/mhu_wrapper_v3_x.c
@@ -445,7 +445,7 @@
size_t mhu_get_max_message_size(void)
{
- enum mhu_v3_x_error_t err;
+ enum mhu_v3_x_error_t err __maybe_unused;
uint8_t num_channels;
err = mhu_v3_x_get_num_channel_implemented(&mhu_seh_dev,
diff --git a/drivers/auth/mbedtls/mbedtls_psa_crypto.c b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
index 99242e3..2da97dc 100644
--- a/drivers/auth/mbedtls/mbedtls_psa_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_psa_crypto.c
@@ -446,7 +446,9 @@
*/
if (pk_alg == MBEDTLS_PK_RSASSA_PSS) {
rc = pk_bytes_from_subpubkey((unsigned char **) &pk_ptr, &pk_len);
- goto end2;
+ if (rc != 0) {
+ goto end2;
+ }
}
/* Get the key_id using import API */
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 4cbc0f7..3e87efc 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -34,6 +34,20 @@
return ops->get_rate(id);
}
+int clk_set_rate(unsigned long id, unsigned long rate, unsigned long *orate)
+{
+ unsigned long lrate;
+
+ assert((ops != NULL) && (ops->set_rate != NULL));
+
+ if (orate != NULL) {
+ return ops->set_rate(id, rate, orate);
+ }
+
+ /* In case the caller is not interested in the output rate */
+ return ops->set_rate(id, rate, &lrate);
+}
+
int clk_get_parent(unsigned long id)
{
assert((ops != NULL) && (ops->get_parent != NULL));
@@ -41,6 +55,13 @@
return ops->get_parent(id);
}
+int clk_set_parent(unsigned long id, unsigned long parent_id)
+{
+ assert((ops != NULL) && (ops->set_parent != NULL));
+
+ return ops->set_parent(id, parent_id);
+}
+
bool clk_is_enabled(unsigned long id)
{
assert((ops != NULL) && (ops->is_enabled != NULL));
diff --git a/drivers/measured_boot/rse/dice_prot_env.c b/drivers/measured_boot/rse/dice_prot_env.c
index 8e9185a..da98afe 100644
--- a/drivers/measured_boot/rse/dice_prot_env.c
+++ b/drivers/measured_boot/rse/dice_prot_env.c
@@ -131,7 +131,8 @@
*/
VERBOSE("Share new_context_handle with child: 0x%x\n",
new_context_handle);
- plat_dpe_share_context_handle(&new_context_handle);
+ plat_dpe_share_context_handle(&new_context_handle,
+ &new_parent_context_handle);
}
} else {
ERROR("dpe_derive_context failed: %d\n", ret);
diff --git a/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk b/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk
index 1af51f8..12e22e9 100644
--- a/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk
+++ b/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk
@@ -26,8 +26,8 @@
# CST_BL31
define CST_BL31_RULE
$(1): $(2)
- @echo " Generating CSF Header for $$@ $$<"
- $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ $(s)echo " Generating CSF Header for $$@ $$<"
+ $(q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
--app $(2) ${BL31_INPUT_FILE}
endef
@@ -36,8 +36,8 @@
# CST_BL32
define CST_BL32_RULE
$(1): $(2)
- @echo " Generating CSF Header for $$@ $$<"
- $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ $(s)echo " Generating CSF Header for $$@ $$<"
+ $(q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
--app $(2) ${BL32_INPUT_FILE}
endef
@@ -46,8 +46,8 @@
# CST_BL33
define CST_BL33_RULE
$(1): $(2)
- @echo " Generating CSF Header for $$@ $$<"
- $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ $(s)echo " Generating CSF Header for $$@ $$<"
+ $(q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
--app $(2) ${BL33_INPUT_FILE}
endef
@@ -56,8 +56,8 @@
# CST_SCP_BL2
define CST_SCP_BL2_RULE
$(1): $(2)
- @echo " Generating CSF Header for $$@ $$<"
- $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ $(s)echo " Generating CSF Header for $$@ $$<"
+ $(q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
--app $(2) ${FUSE_INPUT_FILE}
endef
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk.mk b/drivers/nxp/clk/s32cc/s32cc_clk.mk
new file mode 100644
index 0000000..d1f940a
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/s32cc_clk.mk
@@ -0,0 +1,12 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+CLK_SOURCES := \
+ ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk_drv.c \
+
+ifeq (${BL_COMM_CLK_NEEDED},yes)
+BL2_SOURCES += ${CLK_SOURCES}
+endif
diff --git a/drivers/nxp/clk/s32cc/s32cc_clk_drv.c b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
new file mode 100644
index 0000000..8453000
--- /dev/null
+++ b/drivers/nxp/clk/s32cc/s32cc_clk_drv.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <errno.h>
+
+#include <drivers/clk.h>
+
+static int s32cc_clk_enable(unsigned long id)
+{
+ return -ENOTSUP;
+}
+
+static void s32cc_clk_disable(unsigned long id)
+{
+}
+
+static bool s32cc_clk_is_enabled(unsigned long id)
+{
+ return false;
+}
+
+static unsigned long s32cc_clk_get_rate(unsigned long id)
+{
+ return 0;
+}
+
+static int s32cc_clk_set_rate(unsigned long id, unsigned long rate,
+ unsigned long *orate)
+{
+ return -ENOTSUP;
+}
+
+static int s32cc_clk_get_parent(unsigned long id)
+{
+ return -ENOTSUP;
+}
+
+static int s32cc_clk_set_parent(unsigned long id, unsigned long parent_id)
+{
+ return -ENOTSUP;
+}
+
+void s32cc_clk_register_drv(void)
+{
+ static const struct clk_ops s32cc_clk_ops = {
+ .enable = s32cc_clk_enable,
+ .disable = s32cc_clk_disable,
+ .is_enabled = s32cc_clk_is_enabled,
+ .get_rate = s32cc_clk_get_rate,
+ .set_rate = s32cc_clk_set_rate,
+ .get_parent = s32cc_clk_get_parent,
+ .set_parent = s32cc_clk_set_parent,
+ };
+
+ clk_register(&s32cc_clk_ops);
+}
+
diff --git a/drivers/nxp/ddr/phy-gen2/ddrphy.mk b/drivers/nxp/ddr/phy-gen2/ddrphy.mk
index ba5c774..a09a278 100644
--- a/drivers/nxp/ddr/phy-gen2/ddrphy.mk
+++ b/drivers/nxp/ddr/phy-gen2/ddrphy.mk
@@ -12,9 +12,9 @@
DDR_PHY_H =
$(DDR_PHY_C): $(DDR_PHY_H) $(COMMON_HDRS) src
- @cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
+ $(q)cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
$(DDR_PHY_H): src
- @cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
+ $(q)cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
#------------------------------------------------
diff --git a/drivers/nxp/drivers.mk b/drivers/nxp/drivers.mk
index d77e985..761571d 100644
--- a/drivers/nxp/drivers.mk
+++ b/drivers/nxp/drivers.mk
@@ -97,3 +97,7 @@
ifeq (${IFC_NAND_NEEDED},yes)
include ${PLAT_DRIVERS_PATH}/ifc/nand/ifc_nand.mk
endif
+
+ifeq (${CLK_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/clk/s32cc/s32cc_clk.mk
+endif
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index a4a64ca..44d7c09 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2016-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -282,6 +282,7 @@
clk_disable(clock);
+#if STM32MP13 || STM32MP15
if (status == DT_SECURE) {
stm32mp_register_secure_gpio(bank, pin);
#if !IMAGE_BL2
@@ -294,6 +295,9 @@
set_gpio_secure_cfg(bank, pin, false);
#endif
}
+#else /* !STM32MP13 && !STM32MP15 */
+ set_gpio_secure_cfg(bank, pin, true);
+#endif /* STM32MP13 || STM32MP15 */
}
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
@@ -321,3 +325,74 @@
GPIO_ALTERNATE_(0), DT_DISABLED);
set_gpio_secure_cfg(bank, pin, stm32_gpio_is_secure_at_reset(bank));
}
+
+void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level)
+{
+ uintptr_t base = stm32_get_gpio_bank_base(bank);
+ unsigned long clock = stm32_get_gpio_bank_clock(bank);
+
+ assert(pin <= GPIO_PIN_MAX);
+
+ clk_enable(clock);
+
+ if (level == GPIO_LEVEL_HIGH) {
+ mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin));
+ } else {
+ mmio_write_32(base + GPIO_BSRR_OFFSET, BIT(pin + 16U));
+ }
+
+ VERBOSE("GPIO %u level set to 0x%x\n", bank,
+ mmio_read_32(base + GPIO_IDR_OFFSET));
+
+ clk_disable(clock);
+}
+
+enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin)
+{
+ uintptr_t base = stm32_get_gpio_bank_base(bank);
+ unsigned long clock = stm32_get_gpio_bank_clock(bank);
+ enum gpio_level level = GPIO_LEVEL_LOW;
+
+ assert(pin <= GPIO_PIN_MAX);
+
+ clk_enable(clock);
+
+ if (mmio_read_32(base + GPIO_IDR_OFFSET) & BIT(pin)) {
+ level = GPIO_LEVEL_HIGH;
+ }
+
+ VERBOSE("GPIO %u get level 0x%x\n", bank,
+ mmio_read_32(base + GPIO_IDR_OFFSET));
+
+ clk_disable(clock);
+
+ return level;
+}
+
+void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status)
+{
+ uint32_t mode = GPIO_MODE_OUTPUT;
+ uint32_t od = 0U;
+ uint32_t pull = GPIO_NO_PULL;
+
+ VERBOSE("GPIO %u:%u set config to 0x%x\n", bank, pin, config);
+
+ if (config & GPIOF_DIR_IN) {
+ mode = GPIO_MODE_INPUT;
+ }
+
+ if (config & GPIOF_OUT_INIT_HIGH) {
+ od = 1U;
+ }
+
+ if (config & GPIOF_PULL_UP) {
+ pull |= GPIO_PULL_UP;
+ }
+
+ if (config & GPIOF_PULL_DOWN) {
+ pull |= GPIO_PULL_DOWN;
+ }
+
+ set_gpio(bank, pin, mode, GPIO_TYPE_PUSH_PULL, GPIO_SPEED_LOW,
+ pull, od, GPIO_ALTERNATE_(0), status);
+}
diff --git a/fdts/tc-base.dtsi b/fdts/tc-base.dtsi
index 494c825..2e03be2 100644
--- a/fdts/tc-base.dtsi
+++ b/fdts/tc-base.dtsi
@@ -482,9 +482,6 @@
scmi-perf-domain = <3>;
#endif /* TC_SCMI_PD_CTRL_EN */
-#if TC_IOMMU_EN
- iommus = <&smmu_700 0x200>;
-#endif /* TC_IOMMU_EN */
pbha {
int-id-override = <0 0x22>, <2 0x23>, <4 0x23>, <7 0x22>,
<8 0x22>, <9 0x22>, <10 0x22>, <11 0x22>,
@@ -507,7 +504,18 @@
thermal-zone = "";
};
-#if TC_IOMMU_EN
+ smmu_600: smmu@2ce00000 {
+ compatible = "arm,smmu-v3";
+ reg = <0 0x2ce00000 0 0x20000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
+ #iommu-cells = <1>;
+ status = "disabled";
+ };
+
smmu_700: iommu@3f000000 {
#iommu-cells = <1>;
compatible = "arm,smmu-v3";
@@ -517,8 +525,20 @@
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
dma-coherent;
+ status = "disabled";
+ };
+
+ smmu_700_dpu: iommu@4002a00000 {
+ #iommu-cells = <1>;
+ compatible = "arm,smmu-v3";
+ reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>;
+ interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 482 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 483 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eventq", "cmdq-sync", "gerror";
+ dma-coherent;
+ status = "disabled";
};
-#endif /* TC_IOMMU_EN */
dp0: display@DPU_ADDR {
#address-cells = <1>;
@@ -528,9 +548,6 @@
interrupts = <GIC_SPI DPU_IRQ IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DPU";
DPU_CLK_ATTR1;
-#if TC_IOMMU_EN
- iommus = <&smmu_700 0x100>;
-#endif /* TC_IOMMU_EN */
pl0: pipeline@0 {
reg = <0>;
diff --git a/fdts/tc2.dts b/fdts/tc2.dts
index 69c6886..4946aca 100644
--- a/fdts/tc2.dts
+++ b/fdts/tc2.dts
@@ -237,9 +237,18 @@
};
};
+ smmu_700: iommu@3f000000 {
+ status = "okay";
+ };
+
dp0: display@DPU_ADDR {
#if TC_SCMI_PD_CTRL_EN
power-domains = <&scmi_devpd (PLAT_MAX_CPUS_PER_CLUSTER + 2)>;
#endif
+ iommus = <&smmu_700 0x100>;
+ };
+
+ gpu: gpu@2d000000 {
+ iommus = <&smmu_700 0x200>;
};
};
diff --git a/fdts/tc3.dts b/fdts/tc3.dts
index f900eaf..c741be0 100644
--- a/fdts/tc3.dts
+++ b/fdts/tc3.dts
@@ -105,4 +105,35 @@
shmem = <&cpu_scp_scmi_a2p &cpu_scp_scmi_p2a>;
};
};
+
+#if TARGET_FLAVOUR_FVP
+ smmu_700: iommu@3f000000 {
+ status = "okay";
+ };
+
+ smmu_700_dpu: iommu@4002a00000 {
+ status = "okay";
+ };
+#else
+ smmu_600: smmu@2ce00000 {
+ status = "okay";
+ };
+#endif
+
+ dp0: display@DPU_ADDR {
+#if TARGET_FLAVOUR_FVP
+ iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
+ <&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
+#else /* TARGET_FLAVOUR_FPGA */
+ iommus = <&smmu_600 0>, <&smmu_600 1>, <&smmu_600 2>, <&smmu_600 3>,
+ <&smmu_600 4>, <&smmu_600 5>, <&smmu_600 6>, <&smmu_600 7>,
+ <&smmu_600 8>, <&smmu_600 9>;
+#endif
+ };
+
+ gpu: gpu@2d000000 {
+#if TARGET_FLAVOUR_FVP
+ iommus = <&smmu_700 0x200>;
+#endif
+ };
};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 4eb54ed..df0dcc3 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -238,7 +238,7 @@
#define ID_AA64DFR0_PMUVER_SHIFT U(8)
#define ID_AA64DFR0_PMUVER_MASK U(0xf)
#define ID_AA64DFR0_PMUVER_PMUV3 U(1)
-#define ID_AA64DFR0_PMUVER_PMUV3P7 U(7)
+#define ID_AA64DFR0_PMUVER_PMUV3P8 U(8)
#define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf)
/* ID_AA64DFR0_EL1.SEBEP definitions */
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index 1a3e9b6..b4c5c1b 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -88,21 +88,8 @@
* MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
* Debug exceptions, other than Breakpoint Instruction exceptions, are
* disabled from all ELs in Secure state.
- *
- * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
- * privileged debug from S-EL1.
- *
- * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
- * access to the powerdown debug registers do not trap to EL3.
- *
- * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
- * debug registers, other than those registers that are controlled by
- * MDCR_EL3.TDOSA.
*/
- mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
- MDCR_SPD32(MDCR_SPD32_DISABLE)) & \
- ~(MDCR_TDOSA_BIT | MDCR_TDA_BIT))
-
+ mov_imm x0, (MDCR_EL3_RESET_VAL | MDCR_SDD_BIT)
msr mdcr_el3, x0
/* ---------------------------------------------------------------------
diff --git a/include/drivers/arm/fvp/fvp_cpu_pwr.h b/include/drivers/arm/fvp/fvp_cpu_pwr.h
new file mode 100644
index 0000000..488be18
--- /dev/null
+++ b/include/drivers/arm/fvp/fvp_cpu_pwr.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FVP_CPU_PWR_H
+#define FVP_CPU_PWR_H
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+#include <stdint.h>
+
+#if __aarch64__
+bool check_cpupwrctrl_el1_is_available(void);
+#endif /* __aarch64__ */
+#endif /* __ASSEMBLER__ */
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* FVP_CPU_PWR_H */
diff --git a/include/drivers/cadence/cdns_sdmmc.h b/include/drivers/cadence/cdns_sdmmc.h
index 6452725..8bf3b78 100644
--- a/include/drivers/cadence/cdns_sdmmc.h
+++ b/include/drivers/cadence/cdns_sdmmc.h
@@ -280,9 +280,6 @@
#define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \
(SDMMC_CDN_##_reg))
-/* Refer to atf/tools/cert_create/include/debug.h */
-#define BIT_32(nr) (U(1) << (nr))
-
/* MMC Peripheral Definition */
#define SOCFPGA_MMC_BLOCK_SIZE U(8192)
#define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1))
diff --git a/include/drivers/clk.h b/include/drivers/clk.h
index a18f41f..4db20f8 100644
--- a/include/drivers/clk.h
+++ b/include/drivers/clk.h
@@ -13,15 +13,20 @@
int (*enable)(unsigned long id);
void (*disable)(unsigned long id);
unsigned long (*get_rate)(unsigned long id);
+ int (*set_rate)(unsigned long id, unsigned long rate,
+ unsigned long *orate);
int (*get_parent)(unsigned long id);
+ int (*set_parent)(unsigned long id, unsigned long parent_id);
bool (*is_enabled)(unsigned long id);
};
int clk_enable(unsigned long id);
void clk_disable(unsigned long id);
unsigned long clk_get_rate(unsigned long id);
+int clk_set_rate(unsigned long id, unsigned long rate, unsigned long *orate);
bool clk_is_enabled(unsigned long id);
int clk_get_parent(unsigned long id);
+int clk_set_parent(unsigned long id, unsigned long parent_id);
void clk_register(const struct clk_ops *ops);
diff --git a/include/drivers/measured_boot/rse/dice_prot_env.h b/include/drivers/measured_boot/rse/dice_prot_env.h
index 6f754f5..e453198 100644
--- a/include/drivers/measured_boot/rse/dice_prot_env.h
+++ b/include/drivers/measured_boot/rse/dice_prot_env.h
@@ -43,7 +43,7 @@
/* Child components inherit their first valid context handle from their parents.
* How to share context handle is platform specific.
*/
-void plat_dpe_share_context_handle(int *ctx_handle);
+void plat_dpe_share_context_handle(int *ctx_handle, int *parent_ctx_handle);
void plat_dpe_get_context_handle(int *ctx_handle);
#endif /* DICE_PROT_ENV_H */
diff --git a/include/drivers/st/stm32_gpio.h b/include/drivers/st/stm32_gpio.h
index eeef9da..ef4eb04 100644
--- a/include/drivers/st/stm32_gpio.h
+++ b/include/drivers/st/stm32_gpio.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2015-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#define GPIO_TYPE_OFFSET U(0x04)
#define GPIO_SPEED_OFFSET U(0x08)
#define GPIO_PUPD_OFFSET U(0x0C)
+#define GPIO_IDR_OFFSET U(0x10)
#define GPIO_OD_OFFSET U(0x14)
#define GPIO_BSRR_OFFSET U(0x18)
#define GPIO_AFRL_OFFSET U(0x20)
@@ -58,6 +59,16 @@
int dt_set_pinctrl_config(int node);
void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
void set_gpio_reset_cfg(uint32_t bank, uint32_t pin);
+
+enum gpio_level {
+ GPIO_LEVEL_LOW,
+ GPIO_LEVEL_HIGH
+};
+
+void set_gpio_level(uint32_t bank, uint32_t pin, enum gpio_level level);
+enum gpio_level get_gpio_level(uint32_t bank, uint32_t pin);
+
+void set_gpio_config(uint32_t bank, uint32_t pin, uint32_t config, uint8_t status);
#endif /*__ASSEMBLER__*/
#endif /* STM32_GPIO_H */
diff --git a/include/dt-bindings/gpio/stm32-gpio.h b/include/dt-bindings/gpio/stm32-gpio.h
new file mode 100644
index 0000000..2c7a0f1
--- /dev/null
+++ b/include/dt-bindings/gpio/stm32-gpio.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
+/*
+ * Copyright (C) 2024 STMicroelectronics - All Rights Reserved
+ * Author: Paillet Pascal <p.paillet@foss.st.com> for STMicroelectronics.
+ */
+
+#ifndef DT_BINDINGS_STM32_GPIO_H
+#define DT_BINDINGS_STM32_GPIO_H
+
+/* Bank IDs used in GPIO driver API */
+#define GPIO_BANK_A 0U
+#define GPIO_BANK_B 1U
+#define GPIO_BANK_C 2U
+#define GPIO_BANK_D 3U
+#define GPIO_BANK_E 4U
+#define GPIO_BANK_F 5U
+#define GPIO_BANK_G 6U
+#define GPIO_BANK_H 7U
+#define GPIO_BANK_I 8U
+#define GPIO_BANK_J 9U
+#define GPIO_BANK_K 10U
+#define GPIO_BANK_Z 25U
+
+/* Bit 0 is used to set GPIO in input mode */
+#define GPIOF_DIR_OUT 0x0
+#define GPIOF_DIR_IN 0x1
+
+/* Bit 1 is used to set GPIO high level during init */
+#define GPIOF_INIT_LOW 0x0
+#define GPIOF_INIT_HIGH 0x2
+
+#define GPIOF_IN (GPIOF_DIR_IN)
+#define GPIOF_OUT_INIT_LOW (GPIOF_DIR_OUT | GPIOF_INIT_LOW)
+#define GPIOF_OUT_INIT_HIGH (GPIOF_DIR_OUT | GPIOF_INIT_HIGH)
+
+/* Bit 2 is used to set GPIO pull up */
+#define GPIOF_PULL_UP 0x4
+/* Bit 3 is used to set GPIO pull down */
+#define GPIOF_PULL_DOWN 0x8
+
+#endif /* DT_BINDINGS_STM32_GPIO_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 6f97bed..acf111b 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -63,19 +63,20 @@
#define CTX_ELR_EL3 U(0x20)
#define CTX_PMCR_EL0 U(0x28)
#define CTX_IS_IN_EL3 U(0x30)
+#define CTX_MDCR_EL3 U(0x38)
/* Constants required in supporting nested exception in EL3 */
-#define CTX_SAVED_ELR_EL3 U(0x38)
+#define CTX_SAVED_ELR_EL3 U(0x40)
/*
* General purpose flag, to save various EL3 states
* FFH mode : Used to identify if handling nested exception
* KFH mode : Used as counter value
*/
-#define CTX_NESTED_EA_FLAG U(0x40)
+#define CTX_NESTED_EA_FLAG U(0x48)
#if FFH_SUPPORT
- #define CTX_SAVED_ESR_EL3 U(0x48)
- #define CTX_SAVED_SPSR_EL3 U(0x50)
- #define CTX_SAVED_GPREG_LR U(0x58)
- #define CTX_EL3STATE_END U(0x60) /* Align to the next 16 byte boundary */
+ #define CTX_SAVED_ESR_EL3 U(0x50)
+ #define CTX_SAVED_SPSR_EL3 U(0x58)
+ #define CTX_SAVED_GPREG_LR U(0x60)
+ #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */
#else
#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
#endif /* FFH_SUPPORT */
diff --git a/include/lib/extensions/brbe.h b/include/lib/extensions/brbe.h
index 194efba..425a037 100644
--- a/include/lib/extensions/brbe.h
+++ b/include/lib/extensions/brbe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,12 @@
#ifndef BRBE_H
#define BRBE_H
+#include <context.h>
+
#if ENABLE_BRBE_FOR_NS
-void brbe_init_el3(void);
+void brbe_enable(cpu_context_t *ctx);
#else
-static inline void brbe_init_el3(void)
+static inline void brbe_enable(cpu_context_t *ctx)
{
}
#endif /* ENABLE_BRBE_FOR_NS */
diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h
index 7b39037..c6e44f9 100644
--- a/include/lib/extensions/spe.h
+++ b/include/lib/extensions/spe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,13 +8,14 @@
#define SPE_H
#include <stdbool.h>
+#include <context.h>
#if ENABLE_SPE_FOR_NS
-void spe_init_el3(void);
+void spe_enable(cpu_context_t *ctx);
void spe_init_el2_unused(void);
void spe_disable(void);
#else
-static inline void spe_init_el3(void)
+static inline void spe_enable(cpu_context_t *ctx)
{
}
static inline void spe_init_el2_unused(void)
diff --git a/include/lib/extensions/trbe.h b/include/lib/extensions/trbe.h
index 0bed433..5db3316 100644
--- a/include/lib/extensions/trbe.h
+++ b/include/lib/extensions/trbe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,11 +7,13 @@
#ifndef TRBE_H
#define TRBE_H
+#include <context.h>
+
#if ENABLE_TRBE_FOR_NS
-void trbe_init_el3(void);
+void trbe_enable(cpu_context_t *ctx);
void trbe_init_el2_unused(void);
#else
-static inline void trbe_init_el3(void)
+static inline void trbe_enable(cpu_context_t *ctx)
{
}
static inline void trbe_init_el2_unused(void)
diff --git a/include/lib/extensions/trf.h b/include/lib/extensions/trf.h
index 1ac7cda..f0a946b 100644
--- a/include/lib/extensions/trf.h
+++ b/include/lib/extensions/trf.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,16 +7,32 @@
#ifndef TRF_H
#define TRF_H
+#include <context.h>
+
#if ENABLE_TRF_FOR_NS
-void trf_init_el3(void);
+
+#if __aarch64__
+void trf_enable(cpu_context_t *ctx);
void trf_init_el2_unused(void);
-#else
-static inline void trf_init_el3(void)
+#else /* !__aarch64 */
+void trf_init_el3(void);
+#endif /* __aarch64__ */
+
+#else /* ENABLE_TRF_FOR_NS=0 */
+
+#if __aarch64__
+static inline void trf_enable(cpu_context_t *ctx)
{
}
static inline void trf_init_el2_unused(void)
{
}
+#else /* !__aarch64 */
+static inline void trf_init_el3(void)
+{
+}
+#endif /* __aarch64__*/
+
#endif /* ENABLE_TRF_FOR_NS */
#endif /* TRF_H */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 8a03c7d..c3f767e 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -19,8 +19,13 @@
#define SIZE_FROM_LOG2_WORDS(n) (U(4) << (n))
+#if defined(__LINKER__) || defined(__ASSEMBLER__)
#define BIT_32(nr) (U(1) << (nr))
#define BIT_64(nr) (ULL(1) << (nr))
+#else
+#define BIT_32(nr) (((uint32_t)(1U)) << (nr))
+#define BIT_64(nr) (((uint64_t)(1ULL)) << (nr))
+#endif
#ifdef __aarch64__
#define BIT BIT_64
@@ -29,22 +34,22 @@
#endif
/*
- * Create a contiguous bitmask starting at bit position @l and ending at
- * position @h. For example
+ * Create a contiguous bitmask starting at bit position @low and ending at
+ * position @high. For example
* GENMASK_64(39, 21) gives us the 64bit vector 0x000000ffffe00000.
*/
#if defined(__LINKER__) || defined(__ASSEMBLER__)
-#define GENMASK_32(h, l) \
- (((0xFFFFFFFF) << (l)) & (0xFFFFFFFF >> (32 - 1 - (h))))
+#define GENMASK_32(high, low) \
+ (((0xFFFFFFFF) << (low)) & (0xFFFFFFFF >> (32 - 1 - (high))))
-#define GENMASK_64(h, l) \
- ((~0 << (l)) & (~0 >> (64 - 1 - (h))))
+#define GENMASK_64(high, low) \
+ ((~0 << (low)) & (~0 >> (64 - 1 - (high))))
#else
-#define GENMASK_32(h, l) \
- (((~UINT32_C(0)) << (l)) & (~UINT32_C(0) >> (32 - 1 - (h))))
+#define GENMASK_32(high, low) \
+ ((~UINT32_C(0) >> (32U - 1U - (high))) ^ ((BIT_32(low) - 1U)))
-#define GENMASK_64(h, l) \
- (((~UINT64_C(0)) << (l)) & (~UINT64_C(0) >> (64 - 1 - (h))))
+#define GENMASK_64(high, low) \
+ ((~UINT64_C(0) >> (64U - 1U - (high))) ^ ((BIT_64(low) - 1U)))
#endif
#ifdef __aarch64__
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index ce5e8e0..1015fca 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -41,6 +41,16 @@
enum fw_enc_status_t;
/*******************************************************************************
+ * Structure populated by platform specific code to export routines which
+ * perform load images functions, and associated pointer to platform ops
+ ******************************************************************************/
+struct plat_try_images_ops {
+ int (*next_instance)(unsigned int image_id);
+};
+
+extern const struct plat_try_images_ops *plat_try_img_ops;
+
+/*******************************************************************************
* plat_get_rotpk_info() flags
******************************************************************************/
#define ROTPK_IS_HASH (1 << 0)
@@ -154,7 +164,7 @@
void plat_system_reset(void) __dead2;
const char *plat_log_get_prefix(unsigned int log_level);
void bl2_plat_preload_setup(void);
-int plat_try_next_boot_source(void);
+void plat_setup_try_img_ops(const struct plat_try_images_ops *plat_try_ops);
#if MEASURED_BOOT
int plat_mboot_measure_image(unsigned int image_id, image_info_t *image_data);
diff --git a/include/tools_share/cca_oid.h b/include/tools_share/cca_oid.h
index 8c53ef9..6f89c16 100644
--- a/include/tools_share/cca_oid.h
+++ b/include/tools_share/cca_oid.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,15 +30,17 @@
/*
* First undef previous definitions from tbbr_oid.h.
- * CCA ROTPK authenticates BL31 and its configuration image in
+ * CCA ROTPK authenticates BL31, SCP_BL2 and its configuration image in
* CCA CoT.
**/
#undef BL31_IMAGE_KEY_OID
#undef SOC_FW_CONFIG_KEY_OID
#undef HW_CONFIG_KEY_OID
+#undef SCP_BL2_IMAGE_KEY_OID
#define BL31_IMAGE_KEY_OID ZERO_OID
#define SOC_FW_CONFIG_KEY_OID ZERO_OID
#define HW_CONFIG_KEY_OID ZERO_OID
+#define SCP_BL2_IMAGE_KEY_OID ZERO_OID
#define RMM_IMAGE_KEY_OID ZERO_OID
#endif /* CCA_OID_H */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 76aebf9..1fce1bf 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -454,15 +454,17 @@
synchronize_errors
#endif /* IMAGE_BL31 */
- /* ----------------------------------------------------------
- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
- * ----------------------------------------------------------
+ /* --------------------------------------------------------------
+ * Restore MDCR_EL3, SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
+ * --------------------------------------------------------------
*/
- ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
- msr scr_el3, x18
+ ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
+ ldr x19, [sp, #CTX_EL3STATE_OFFSET + CTX_MDCR_EL3]
msr spsr_el3, x16
msr elr_el3, x17
+ msr scr_el3, x18
+ msr mdcr_el3, x19
restore_ptw_el1_sys_regs
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 1937c30..981fddc 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -42,6 +42,7 @@
per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
static bool has_secure_perworld_init;
+static void manage_extensions_common(cpu_context_t *ctx);
static void manage_extensions_nonsecure(cpu_context_t *ctx);
static void manage_extensions_secure(cpu_context_t *ctx);
static void manage_extensions_secure_per_world(void);
@@ -261,13 +262,9 @@
#if CTX_INCLUDE_EL2_REGS
/*
- * Initialize SCTLR_EL2 context register using Endianness value
- * taken from the entrypoint attribute.
+ * Initialize SCTLR_EL2 context register with reset value.
*/
- u_register_t sctlr_el2_val = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
- sctlr_el2_val |= SCTLR_EL2_RES1;
- write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, sctlr_el2_val);
-
+ write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1);
if (is_feat_hcx_supported()) {
/*
@@ -312,6 +309,7 @@
static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
{
u_register_t scr_el3;
+ u_register_t mdcr_el3;
el3_state_t *state;
gp_regs_t *gp_regs;
@@ -484,6 +482,37 @@
write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
+ /* Start with a clean MDCR_EL3 copy as all relevant values are set */
+ mdcr_el3 = MDCR_EL3_RESET_VAL;
+
+ /* ---------------------------------------------------------------------
+ * Initialise MDCR_EL3, setting all fields rather than relying on hw.
+ * Some fields are architecturally UNKNOWN on reset.
+ *
+ * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
+ * Debug exceptions, other than Breakpoint Instruction exceptions, are
+ * disabled from all ELs in Secure state.
+ *
+ * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
+ * privileged debug from S-EL1.
+ *
+ * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
+ * access to the powerdown debug registers do not trap to EL3.
+ *
+ * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
+ * debug registers, other than those registers that are controlled by
+ * MDCR_EL3.TDOSA.
+ */
+ mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
+ & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ;
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3);
+
+ /*
+ * Configure MDCR_EL3 register as applicable for each world
+ * (NS/Secure/Realm) context.
+ */
+ manage_extensions_common(ctx);
+
/*
* Store the X0-X7 value from the entrypoint into the context
* Use memcpy as we are in control of the layout of the structures
@@ -560,10 +589,6 @@
#if IMAGE_BL31
void cm_manage_extensions_el3(void)
{
- if (is_feat_spe_supported()) {
- spe_init_el3();
- }
-
if (is_feat_amu_supported()) {
amu_init_el3();
}
@@ -572,18 +597,6 @@
sme_init_el3();
}
- if (is_feat_trbe_supported()) {
- trbe_init_el3();
- }
-
- if (is_feat_brbe_supported()) {
- brbe_init_el3();
- }
-
- if (is_feat_trf_supported()) {
- trf_init_el3();
- }
-
pmuv3_init_el3();
}
#endif /* IMAGE_BL31 */
@@ -704,6 +717,48 @@
}
/*******************************************************************************
+ * Enable architecture extensions on first entry to Non-secure world only
+ * and disable for secure world.
+ *
+ * NOTE: Arch features which have been provided with the capability of getting
+ * enabled only for non-secure world and being disabled for secure world are
+ * grouped here, as the MDCR_EL3 context value remains same across the worlds.
+ ******************************************************************************/
+static void manage_extensions_common(cpu_context_t *ctx)
+{
+#if IMAGE_BL31
+ if (is_feat_spe_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ */
+ spe_enable(ctx);
+ }
+
+ if (is_feat_trbe_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure and
+ * Realm state.
+ */
+ trbe_enable(ctx);
+ }
+
+ if (is_feat_trf_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ */
+ trf_enable(ctx);
+ }
+
+ if (is_feat_brbe_supported()) {
+ /*
+ * Enable FEAT_SPE for Non-Secure and prohibit for Secure state.
+ */
+ brbe_enable(ctx);
+ }
+#endif /* IMAGE_BL31 */
+}
+
+/*******************************************************************************
* Enable architecture extensions on first entry to Non-secure world.
******************************************************************************/
static void manage_extensions_nonsecure(cpu_context_t *ctx)
@@ -952,7 +1007,7 @@
******************************************************************************/
void cm_prepare_el3_exit(uint32_t security_state)
{
- u_register_t sctlr_elx, scr_el3;
+ u_register_t sctlr_el2, scr_el3;
cpu_context_t *ctx = cm_get_context(security_state);
assert(ctx != NULL);
@@ -993,20 +1048,17 @@
/* Condition to ensure EL2 is being used. */
if ((scr_el3 & SCR_HCE_BIT) != 0U) {
- /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
- sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx),
- CTX_SCTLR_EL1);
- sctlr_elx &= SCTLR_EE_BIT;
- sctlr_elx |= SCTLR_EL2_RES1;
+ /* Initialize SCTLR_EL2 register with reset value. */
+ sctlr_el2 = SCTLR_EL2_RES1;
#if ERRATA_A75_764081
/*
* If workaround of errata 764081 for Cortex-A75
* is used then set SCTLR_EL2.IESB to enable
* Implicit Error Synchronization Barrier.
*/
- sctlr_elx |= SCTLR_IESB_BIT;
-#endif /* ERRATA_A75_764081 */
- write_sctlr_el2(sctlr_elx);
+ sctlr_el2 |= SCTLR_IESB_BIT;
+#endif
+ write_sctlr_el2(sctlr_el2);
} else {
/*
* (scr_el3 & SCR_HCE_BIT==0)
diff --git a/lib/extensions/brbe/brbe.c b/lib/extensions/brbe/brbe.c
index 37bd834..dde0266 100644
--- a/lib/extensions/brbe/brbe.c
+++ b/lib/extensions/brbe/brbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,9 +9,10 @@
#include <arch_helpers.h>
#include <lib/extensions/brbe.h>
-void brbe_init_el3(void)
+void brbe_enable(cpu_context_t *ctx)
{
- uint64_t val;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.SBRBE = 0b01
@@ -19,8 +20,7 @@
* Allows BRBE usage in non-secure world and prohibited in
* secure world.
*/
- val = read_mdcr_el3();
- val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
- val |= (0x1UL << MDCR_SBRBE_SHIFT);
- write_mdcr_el3(val);
+ mdcr_el3_val &= ~(MDCR_SBRBE_MASK << MDCR_SBRBE_SHIFT);
+ mdcr_el3_val |= (0x1UL << MDCR_SBRBE_SHIFT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c
index d1fb182..c6076fe 100644
--- a/lib/extensions/spe/spe.c
+++ b/lib/extensions/spe/spe.c
@@ -29,9 +29,10 @@
__asm__ volatile("hint #17");
}
-void spe_init_el3(void)
+void spe_enable(cpu_context_t *ctx)
{
- uint64_t v;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.NSPB (ARM v8.2): SPE enabled in Non-secure state
@@ -46,10 +47,9 @@
* Setting this bit to 1 doesn't have any effect on it when
* FEAT_SPEv1p2 not implemented.
*/
- v = read_mdcr_el3();
- v |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
- v &= ~(MDCR_NSPBE_BIT);
- write_mdcr_el3(v);
+ mdcr_el3_val |= MDCR_NSPB(MDCR_NSPB_EL1) | MDCR_EnPMSN_BIT;
+ mdcr_el3_val &= ~(MDCR_NSPBE_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void spe_init_el2_unused(void)
diff --git a/lib/extensions/trbe/trbe.c b/lib/extensions/trbe/trbe.c
index d4fbdfb..9157734 100644
--- a/lib/extensions/trbe/trbe.c
+++ b/lib/extensions/trbe/trbe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,9 +19,10 @@
__asm__ volatile("hint #18");
}
-void trbe_init_el3(void)
+void trbe_enable(cpu_context_t *ctx)
{
- u_register_t val;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.NSTBE = 0b0
@@ -33,10 +34,9 @@
* NS-EL2, tracing is prohibited in Secure and Realm state (if
* implemented).
*/
- val = read_mdcr_el3();
- val |= MDCR_NSTB(MDCR_NSTB_EL1);
- val &= ~(MDCR_NSTBE_BIT);
- write_mdcr_el3(val);
+ mdcr_el3_val |= MDCR_NSTB(MDCR_NSTB_EL1);
+ mdcr_el3_val &= ~(MDCR_NSTBE_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void trbe_init_el2_unused(void)
diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c
index 83fbf85..d36853a 100644
--- a/lib/extensions/trf/aarch64/trf.c
+++ b/lib/extensions/trf/aarch64/trf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,9 +9,10 @@
#include <arch_helpers.h>
#include <lib/extensions/trf.h>
-void trf_init_el3(void)
+void trf_enable(cpu_context_t *ctx)
{
- u_register_t val;
+ el3_state_t *state = get_el3state_ctx(ctx);
+ u_register_t mdcr_el3_val = read_ctx_reg(state, CTX_MDCR_EL3);
/*
* MDCR_EL3.STE = b0
@@ -22,9 +23,8 @@
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
*/
- val = read_mdcr_el3();
- val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
- write_mdcr_el3(val);
+ mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
+ write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
void trf_init_el2_unused(void)
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index ee502de..d028fce 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -847,7 +847,7 @@
assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
#if (RME_GPT_MAX_BLOCK != 0)
- while (first < last) {
+ while (first <= last) {
/* Region length */
size_t length = last - first + GPT_PGS_ACTUAL_SIZE(gpt_config.p);
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index da3d3d5..9ade331 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -10,6 +10,7 @@
toolchains := aarch64
endif
+include ../../make_helpers/common.mk
include ../../make_helpers/toolchain.mk
ROMLIB_GEN = ./romlib_generator.py
@@ -29,13 +30,6 @@
WRAPPER_OBJS = $(WRAPPER_SOURCES:.s=.o)
endif
-V ?= 0
-ifeq ($(V),0)
- Q := @
-else
- Q :=
-endif
-
LDFLAGS := -Wl,--gc-sections -nostdlib
ifeq ($(DEBUG),1)
@@ -53,49 +47,49 @@
all: $(BUILD_DIR)/romlib.bin $(LIB_DIR)/libwrappers.a
%.o: %.s
- @echo " AS $@"
- $(Q)$(aarch64-as) -c $(ASFLAGS) -o $@ $<
+ $(s)echo " AS $@"
+ $(q)$(aarch64-as) -c $(ASFLAGS) -o $@ $<
$(BUILD_DIR)/%.o: %.s
- @echo " AS $@"
- $(Q)$(aarch64-as) -c $(ASFLAGS) -o $@ $<
+ $(s)echo " AS $@"
+ $(q)$(aarch64-as) -c $(ASFLAGS) -o $@ $<
$(BUILD_DIR)/romlib.ld: romlib.ld.S
- @echo " PP $@"
- $(Q)$(aarch64-cpp) -E $(PPFLAGS) -o $@ romlib.ld.S
+ $(s)echo " PP $@"
+ $(q)$(aarch64-cpp) -E $(PPFLAGS) -o $@ romlib.ld.S
$(BUILD_DIR)/romlib.elf: $(OBJS) $(BUILD_DIR)/romlib.ld
- @echo " LD $@"
- $(Q)$(aarch64-ld) -T $(BUILD_DIR)/romlib.ld -L$(LIB_DIR) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
+ $(s)echo " LD $@"
+ $(q)$(aarch64-ld) -T $(BUILD_DIR)/romlib.ld -L$(LIB_DIR) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
$(BUILD_DIR)/romlib.bin: $(BUILD_DIR)/romlib.elf
- @echo " BIN $@"
- $(Q)$(aarch64-oc) -O binary $(BUILD_DIR)/romlib.elf $@
+ $(s)echo " BIN $@"
+ $(q)$(aarch64-oc) -O binary $(BUILD_DIR)/romlib.elf $@
$(WRAPPER_DIR)/jmpvar.s: $(BUILD_DIR)/romlib.elf
- @echo " VAR $@"
- $(Q)$(ROMLIB_GEN) genvar --output $@ $<
+ $(s)echo " VAR $@"
+ $(q)$(ROMLIB_GEN) genvar --output $@ $<
$(LIB_DIR)/libwrappers.a: $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
- @echo " AR $@"
- $(Q)$(aarch64-ar) -rc $@ $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
+ $(s)echo " AR $@"
+ $(q)$(aarch64-ar) -rc $@ $(WRAPPER_DIR)/jmpvar.o $(WRAPPER_OBJS)
$(BUILD_DIR)/jmptbl.i: ../../$(PLAT_DIR)/jmptbl.i
- @echo " PRE $@"
- $(Q)$(ROMLIB_GEN) pre --output $@ --deps $(BUILD_DIR)/jmptbl.d $<
+ $(s)echo " PRE $@"
+ $(q)$(ROMLIB_GEN) pre --output $@ --deps $(BUILD_DIR)/jmptbl.d $<
$(WRAPPER_SOURCES) &: $(BUILD_DIR)/jmptbl.i
- @echo " WRP $<"
- $(Q)$(ROMLIB_GEN) genwrappers --bti=$(ENABLE_BTI) -b $(WRAPPER_DIR) $<
+ $(s)echo " WRP $<"
+ $(q)$(ROMLIB_GEN) genwrappers --bti=$(ENABLE_BTI) -b $(WRAPPER_DIR) $<
$(WRAPPER_OBJS): $(WRAPPER_DIR)/%.o: $(WRAPPER_DIR)/%.s
$(BUILD_DIR)/jmptbl.s: $(BUILD_DIR)/jmptbl.i
- @echo " TBL $@"
- $(Q)$(ROMLIB_GEN) gentbl --output $@ --bti=$(ENABLE_BTI) $<
+ $(s)echo " TBL $@"
+ $(q)$(ROMLIB_GEN) gentbl --output $@ --bti=$(ENABLE_BTI) $<
clean:
- @rm -f $(BUILD_DIR)/*
+ $(q)rm -f $(BUILD_DIR)/*
-include $(BUILD_DIR)/romlib.d
-include $(BUILD_DIR)/jmptbl.d
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index fabd74e..d27408c 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -17,22 +17,6 @@
$(strip $(foreach d,$(wildcard ${1}*),$(call rwildcard,${d}/,${2}) $(filter $(subst *,%,%${2}),${d})))
endef
-# This table is used in converting lower case to upper case.
-uppercase_table:=a,A b,B c,C d,D e,E f,F g,G h,H i,I j,J k,K l,L m,M n,N o,O p,P q,Q r,R s,S t,T u,U v,V w,W x,X y,Y z,Z
-
-# Internal macro used for converting lower case to upper case.
-# $(1) = upper case table
-# $(2) = String to convert
-define uppercase_internal
-$(if $(1),$$(subst $(firstword $(1)),$(call uppercase_internal,$(wordlist 2,$(words $(1)),$(1)),$(2))),$(2))
-endef
-
-# A macro for converting a string to upper case
-# $(1) = String to convert
-define uppercase
-$(eval uppercase_result:=$(call uppercase_internal,$(uppercase_table),$(1)))$(uppercase_result)
-endef
-
# Convenience function for setting a variable to 0 if not previously set
# $(eval $(call default_zero,FOO))
define default_zero
@@ -164,8 +148,8 @@
# $(2) = output encrypted firmware binary
define ENCRYPT_FW
$(2): $(1) enctool
- $$(ECHO) " ENC $$<"
- $$(Q)$$(ENCTOOL) $$(ENC_ARGS) -i $$< -o $$@
+ $$(s)echo " ENC $$<"
+ $$(q)$$(ENCTOOL) $$(ENC_ARGS) -i $$< -o $$@
endef
# TOOL_ADD_PAYLOAD appends the command line arguments required by fiptool to
@@ -283,8 +267,8 @@
# GZIP
define GZIP_RULE
$(1): $(2)
- $(ECHO) " GZIP $$@"
- $(Q)gzip -n -f -9 $$< --stdout > $$@
+ $(s)echo " GZIP $$@"
+ $(q)gzip -n -f -9 $$< --stdout > $$@
endef
GZIP_SUFFIX := .gz
@@ -306,8 +290,8 @@
$(eval LIB := $(call uppercase, $(notdir $(1))))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs
- $$(ECHO) " CC $$<"
- $$(Q)$($(ARCH)-cc) $$($(LIB)_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(MAKE_DEP) -c $$< -o $$@
+ $$(s)echo " CC $$<"
+ $$(q)$($(ARCH)-cc) $$($(LIB)_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -322,8 +306,8 @@
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | lib$(3)_dirs
- $$(ECHO) " AS $$<"
- $$(Q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
+ $$(s)echo " AS $$<"
+ $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -345,8 +329,8 @@
$(eval BL_CFLAGS := $($(call uppercase,$(3))_CFLAGS) $(PLAT_BL_COMMON_CFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
- $$(ECHO) " CC $$<"
- $$(Q)$($(ARCH)-cc) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CPPFLAGS) $(BL_CFLAGS) $(MAKE_DEP) -c $$< -o $$@
+ $$(s)echo " CC $$<"
+ $$(q)$($(ARCH)-cc) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CPPFLAGS) $(BL_CFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -368,8 +352,8 @@
$(eval BL_ASFLAGS := $($(call uppercase,$(3))_ASFLAGS) $(PLAT_BL_COMMON_ASFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
- $$(ECHO) " AS $$<"
- $$(Q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(BL_CPPFLAGS) $(BL_ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
+ $$(s)echo " AS $$<"
+ $$(q)$($(ARCH)-as) -x assembler-with-cpp $$(TF_CFLAGS_$(ARCH)) $$(ASFLAGS) $(BL_CPPFLAGS) $(BL_ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -389,8 +373,8 @@
$(eval BL_CPPFLAGS := $($(call uppercase,$(3))_CPPFLAGS) $(addprefix -D,$(BL_DEFINES)) $(addprefix -I,$(BL_INCLUDE_DIRS)) $(PLAT_BL_COMMON_CPPFLAGS))
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | $(3)_dirs
- $$(ECHO) " PP $$<"
- $$(Q)$($(ARCH)-cpp) -E $$(CPPFLAGS) $(BL_CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -o $$@ $$<
+ $$(s)echo " PP $$<"
+ $$(q)$($(ARCH)-cpp) -E $$(CPPFLAGS) $(BL_CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -o $$@ $$<
-include $(DEP)
@@ -482,8 +466,8 @@
all: ${LIB_DIR}/lib$(1).a
${LIB_DIR}/lib$(1).a: $(OBJS)
- $$(ECHO) " AR $$@"
- $$(Q)$($(ARCH)-ar) cr $$@ $$?
+ $$(s)echo " AR $$@"
+ $$(q)$($(ARCH)-ar) cr $$@ $$?
endef
# Generate the path to one or more preprocessed linker scripts given the paths
@@ -556,38 +540,38 @@
$(eval OBJS += $(MODULE_OBJS))
$(ELF): $(OBJS) $(DEFAULT_LINKER_SCRIPT) $(LINKER_SCRIPTS) | $(1)_dirs libraries $(BL_LIBS)
- $$(ECHO) " LD $$@"
+ $$(s)echo " LD $$@"
ifeq ($($(ARCH)-ld-id),arm-link)
- $$(Q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=${1}_entrypoint \
+ $$(q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) --entry=${1}_entrypoint \
--predefine=$(call escape-shell,-D__LINKER__=$(__LINKER__)) \
--predefine=$(call escape-shell,-DTF_CFLAGS=$(TF_CFLAGS)) \
--map --list="$(MAPFILE)" --scatter=${PLAT_DIR}/scat/${1}.scat \
$(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS) $(OBJS)
else ifeq ($($(ARCH)-ld-id),gnu-gcc)
- $$(Q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Wl,-Map=$(MAPFILE) \
+ $$(q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Wl,-Map=$(MAPFILE) \
$(addprefix -Wl$(comma)--script$(comma),$(LINKER_SCRIPTS)) -Wl,--script,$(DEFAULT_LINKER_SCRIPT) \
$(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS)
else
- $$(Q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Map=$(MAPFILE) \
+ $$(q)$($(ARCH)-ld) -o $$@ $$(TF_LDFLAGS) $$(LDFLAGS) $(BL_LDFLAGS) -Map=$(MAPFILE) \
$(addprefix -T ,$(LINKER_SCRIPTS)) --script $(DEFAULT_LINKER_SCRIPT) \
$(OBJS) $(LDPATHS) $(LIBWRAPPER) $(LDLIBS) $(BL_LIBS)
endif
ifeq ($(DISABLE_BIN_GENERATION),1)
- @${ECHO_BLANK_LINE}
- @echo "Built $$@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo
+ $(s)echo "Built $$@ successfully"
+ $(s)echo
endif
$(DUMP): $(ELF)
- $${ECHO} " OD $$@"
- $${Q}$($(ARCH)-od) -dx $$< > $$@
+ $$(s)echo " OD $$@"
+ $$(q)$($(ARCH)-od) -dx $$< > $$@
$(BIN): $(ELF)
- $${ECHO} " BIN $$@"
- $$(Q)$($(ARCH)-oc) -O binary $$< $$@
- @${ECHO_BLANK_LINE}
- @echo "Built $$@ successfully"
- @${ECHO_BLANK_LINE}
+ $$(s)echo " BIN $$@"
+ $$(q)$($(ARCH)-oc) -O binary $$< $$@
+ $(s)echo
+ $(s)echo "Built $$@ successfully"
+ $(s)echo
.PHONY: $(1)
ifeq ($(DISABLE_BIN_GENERATION),1)
@@ -645,13 +629,13 @@
$(eval DTBDEP := $(patsubst %.dtb,%.d,$(DOBJ)))
$(DPRE): $(2) | fdt_dirs
- $${ECHO} " CPP $$<"
+ $$(s)echo " CPP $$<"
$(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2))))
- $$(Q)$($(ARCH)-cpp) -E $$(TF_CFLAGS_$(ARCH)) $$(DTC_CPPFLAGS) -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$<
+ $$(q)$($(ARCH)-cpp) -E $$(TF_CFLAGS_$(ARCH)) $$(DTC_CPPFLAGS) -MT $(DTBS) -MMD -MF $(DTSDEP) -o $(DPRE) $$<
$(DOBJ): $(DPRE) $(filter-out %.d,$(MAKEFILE_LIST)) | fdt_dirs
- $${ECHO} " DTC $$<"
- $$(Q)$($(ARCH)-dtc) $$(DTC_FLAGS) -d $(DTBDEP) -o $$@ $$<
+ $$(s)echo " DTC $$<"
+ $$(q)$($(ARCH)-dtc) $$(DTC_FLAGS) -d $(DTBDEP) -o $$@ $$<
-include $(DTBDEP)
-include $(DTSDEP)
diff --git a/make_helpers/common.mk b/make_helpers/common.mk
new file mode 100644
index 0000000..75d9f71
--- /dev/null
+++ b/make_helpers/common.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifndef common-mk
+ common-mk := $(lastword $(MAKEFILE_LIST))
+
+ include $(dir $(common-mk))utilities.mk
+
+ silent = $(call bool,$(findstring s,$(firstword ~$(MAKEFLAGS))))
+ verbose = $(if $(silent),,$(call bool,$(V)))
+
+ s = @$(if $(or $(verbose),$(silent)),: )
+ q = $(if $(verbose),,@)
+endif
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index a5c78ae..368d26d 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -294,9 +294,6 @@
# Use tbbr_oid.h instead of platform_oid.h
USE_TBBR_DEFS := 1
-# Build verbosity
-V := 0
-
# Whether to enable D-Cache early during warm boot. This is usually
# applicable for platforms wherein interconnect programming is not
# required to enable cache coherency after warm reset (eg: single cluster
diff --git a/make_helpers/unix.mk b/make_helpers/unix.mk
index 93e1fcc..4fd819a 100644
--- a/make_helpers/unix.mk
+++ b/make_helpers/unix.mk
@@ -9,9 +9,6 @@
ifndef UNIX_MK
UNIX_MK := $(lastword $(MAKEFILE_LIST))
- ECHO_BLANK_LINE := echo
- ECHO_QUIET := @\#
-
DIR_DELIM := /
PATH_SEP := :
@@ -21,24 +18,24 @@
# ${1} is the file to be copied.
# ${2} is the destination file name.
define SHELL_COPY
- ${Q}cp -f "${1}" "${2}"
+ $(q)cp -f "${1}" "${2}"
endef
# ${1} is the directory to be copied.
# ${2} is the destination directory path.
define SHELL_COPY_TREE
- ${Q}cp -rf "${1}" "${2}"
+ $(q)cp -rf "${1}" "${2}"
endef
# ${1} is the file to be deleted.
define SHELL_DELETE
- -${Q}rm -f "${1}"
+ -$(q)rm -f "${1}"
endef
# ${1} is a space delimited list of files to be deleted.
# Note that we do not quote ${1}, as multiple parameters may be passed.
define SHELL_DELETE_ALL
- -${Q}rm -rf ${1}
+ -$(q)rm -rf ${1}
endef
# ${1} is the directory to be generated.
@@ -48,13 +45,13 @@
ifneq (${1},${2})
${1} : ${2}
- ${Q}mkdir -p "${1}"
+ $(q)mkdir -p "${1}"
endif
endef
define SHELL_REMOVE_DIR
- -${Q}rm -rf "${1}"
+ -$(q)rm -rf "${1}"
endef
nul := /dev/null
diff --git a/make_helpers/utilities.mk b/make_helpers/utilities.mk
index 62769fb..45ef12e 100644
--- a/make_helpers/utilities.mk
+++ b/make_helpers/utilities.mk
@@ -20,3 +20,83 @@
directory-name = $(call decompat-path,$(dir $(call compat-path,$(1))))
escape-shell = '$(subst ','\'',$(1))'
+
+#
+# Upper-case a string value.
+#
+# Parameters:
+#
+# - $(1): The string to upper-case.
+#
+# Example usage:
+#
+# $(call uppercase,HeLlO wOrLd) # "HELLO WORLD"
+#
+
+uppercase = $(shell echo $(call escape-shell,$(1)) | tr '[:lower:]' '[:upper:]')
+
+#
+# Lower-case a string value.
+#
+# Parameters:
+#
+# - $(1): The string to lower-case.
+#
+# Example usage:
+#
+# $(call lowercase,HeLlO wOrLd) # "hello world"
+#
+
+lowercase = $(shell echo $(call escape-shell,$(1)) | tr '[:upper:]' '[:lower:]')
+
+#
+# Determine the "truthiness" of a value.
+#
+# Parameters:
+#
+# - $(1): The value to determine the truthiness of.
+#
+# A value is considered to be falsy if it is:
+#
+# - empty, or
+# - equal to "0", "N", "NO", "F" or "FALSE" after upper-casing.
+#
+# If the value is truthy then the value is returned as-is, otherwise no value
+# is returned.
+#
+# Example usage:
+#
+# truthy := y
+# truthy-bool := $(call bool,$(truthy)) # "y"
+#
+# falsy := n
+# falsy-bool := $(call bool,$(falsy)) # <empty>
+#
+
+bool = $(filter-out 0 n no f false,$(call lowercase,$(1)))
+
+#
+# Determine the "truthiness" of a value, returning 0 or 1.
+#
+# Parameters:
+#
+# - $(1): The value to determine the truthiness of.
+#
+# A value is considered to be falsy if it is:
+#
+# - empty, or
+# - equal to "0", "N", "NO", "F" or "FALSE" after upper-casing.
+#
+# If the value is truthy then the value is returned as-is, otherwise no value
+# is returned.
+#
+# Example usage:
+#
+# truthy := y
+# truthy-bool := $(call bool,$(truthy)) # "1"
+#
+# falsy := n
+# falsy-bool := $(call bool,$(falsy)) # "0"
+#
+
+bool-01 = $(if $(call bool,$(1)),1,0)
diff --git a/make_helpers/windows.mk b/make_helpers/windows.mk
index de34eaf..2f5d51b 100644
--- a/make_helpers/windows.mk
+++ b/make_helpers/windows.mk
@@ -12,8 +12,6 @@
ifndef WINDOWS_MK
WINDOWS_MK := $(lastword $(MAKEFILE_LIST))
- ECHO_BLANK_LINE := @cmd /c echo.
- ECHO_QUIET := @rem
DIR_DELIM := $(strip \)
BIN_EXT := .exe
PATH_SEP := ;
diff --git a/plat/amd/versal2/aarch64/common.c b/plat/amd/versal2/aarch64/common.c
new file mode 100644
index 0000000..3ab3dca
--- /dev/null
+++ b/plat/amd/versal2/aarch64/common.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+
+#include <def.h>
+#include <plat_common.h>
+#include <plat_ipi.h>
+#include <plat_private.h>
+
+uint32_t platform_id, platform_version;
+
+/*
+ * Table of regions to map using the MMU.
+ * This doesn't include TZRAM as the 'mem_layout' argument passed to
+ * configure_mmu_elx() will give the available subset of that,
+ */
+const mmap_region_t plat_mmap[] = {
+ MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
+#if defined(TRANSFER_LIST)
+ MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_BASE + FW_HANDOFF_SIZE,
+ MT_MEMORY | MT_RW | MT_NS),
+#endif
+ { 0 }
+};
+
+const mmap_region_t *plat_get_mmap(void)
+{
+ return plat_mmap;
+}
+
+/* For saving cpu clock for certain platform */
+uint32_t cpu_clock;
+
+const char *board_name_decode(void)
+{
+ const char *platform;
+
+ switch (platform_id) {
+ case SPP:
+ platform = "IPP";
+ break;
+ case EMU:
+ platform = "EMU";
+ break;
+ case SILICON:
+ platform = "Silicon";
+ break;
+ case QEMU:
+ platform = "QEMU";
+ break;
+ default:
+ platform = "Unknown";
+ }
+
+ return platform;
+}
+
+void board_detection(void)
+{
+ uint32_t version;
+
+ version = mmio_read_32(PMC_TAP_VERSION);
+ platform_id = FIELD_GET(PLATFORM_MASK, version);
+ platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
+
+ if (platform_id == QEMU_COSIM) {
+ platform_id = QEMU;
+ }
+
+ /* Make sure that console is setup to see this message */
+ VERBOSE("Platform id: %d version: %d.%d\n", platform_id,
+ platform_version / 10U, platform_version % 10U);
+}
+
+uint32_t get_uart_clk(void)
+{
+ uint32_t uart_clock = 0;
+
+ switch (platform_id) {
+ case SPP:
+ case SPP_MMD:
+ uart_clock = cpu_clock;
+ break;
+ case EMU:
+ case EMU_MMD:
+ uart_clock = 25000000;
+ break;
+ case QEMU:
+ /* Random values now */
+ uart_clock = 25000000;
+ break;
+ case SILICON:
+ uart_clock = 100000000;
+ break;
+ default:
+ panic();
+ }
+
+ return uart_clock;
+}
+
+void config_setup(void)
+{
+ uint32_t val;
+ uintptr_t crl_base, iou_scntrs_base, psx_base;
+
+ crl_base = CRL;
+ iou_scntrs_base = IOU_SCNTRS;
+ psx_base = PSX_CRF;
+
+ /* Reset for system timestamp generator in FPX */
+ mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0);
+
+ /* Global timer init - Program time stamp reference clk */
+ val = mmio_read_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET);
+ val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+ mmio_write_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET, val);
+
+ /* Clear reset of timestamp reg */
+ mmio_write_32(crl_base + CRL_RST_TIMESTAMP_OFFSET, 0);
+
+ /* Program freq register in System counter and enable system counter. */
+ mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET,
+ cpu_clock);
+ mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
+ IOU_SCNTRS_CONTROL_EN);
+
+ generic_delay_timer_init();
+
+ /* Configure IPI data */
+ soc_ipi_config_table_init();
+}
+
+uint32_t plat_get_syscnt_freq2(void)
+{
+ return cpu_clock;
+}
diff --git a/plat/amd/versal2/aarch64/helpers.S b/plat/amd/versal2/aarch64/helpers.S
new file mode 100644
index 0000000..580bb76
--- /dev/null
+++ b/plat/amd/versal2/aarch64/helpers.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <drivers/arm/gicv3.h>
+
+#include <platform_def.h>
+
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_is_my_cpu_primary
+ .globl platform_mem_init
+ .globl plat_my_core_pos
+
+ /* -----------------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * This function performs any platform specific actions
+ * needed for a secondary cpu after a cold reset e.g
+ * mark the cpu's presence, mechanism to place it in a
+ * holding pen etc.
+ * TODO: Should we read the PSYS register to make sure
+ * that the request has gone through.
+ * -----------------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+ mrs x0, mpidr_el1
+
+ /*
+ * There is no sane reason to come out of this wfi. This
+ * cpu will be powered on and reset by the cpu_on pm api
+ */
+ dsb sy
+ bl plat_panic_handler
+endfunc plat_secondary_cold_boot_setup
+
+func plat_is_my_cpu_primary
+ mov x9, x30
+ bl plat_my_core_pos
+ cmp x0, #PRIMARY_CPU
+ cset x0, eq
+ ret x9
+endfunc plat_is_my_cpu_primary
+
+ /* -----------------------------------------------------
+ * unsigned int plat_my_core_pos(void)
+ * This function uses the plat_core_pos_by_mpidr()
+ * definition to get the index of the calling CPU.
+ * -----------------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ b plat_core_pos_by_mpidr
+endfunc plat_my_core_pos
+
+ /* ---------------------------------------------------------------------
+ * We don't need to carry out any memory initialization on platform
+ * The Secure RAM is accessible straight away.
+ * ---------------------------------------------------------------------
+ */
+func platform_mem_init
+ ret
+endfunc platform_mem_init
diff --git a/plat/amd/versal2/bl31_setup.c b/plat/amd/versal2/bl31_setup.c
new file mode 100644
index 0000000..e878863
--- /dev/null
+++ b/plat/amd/versal2/bl31_setup.c
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+
+#include <bl31/bl31.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/dcc.h>
+#include <drivers/arm/pl011.h>
+#include <drivers/console.h>
+#include <lib/cpus/cpu_ops.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <plat/common/platform.h>
+#include <plat_arm.h>
+#include <scmi.h>
+
+#include <def.h>
+#include <plat_fdt.h>
+#include <plat_private.h>
+#include <plat_startup.h>
+#include <pm_api_sys.h>
+#include <pm_client.h>
+
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+/*
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ */
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ assert(sec_state_is_valid(type));
+
+ if (type == NON_SECURE) {
+ return &bl33_image_ep_info;
+ }
+
+ return &bl32_image_ep_info;
+}
+
+/*
+ * Set the build time defaults,if we can't find any config data.
+ */
+static inline void bl31_set_default_config(void)
+{
+ bl32_image_ep_info.pc = BL32_BASE;
+ bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+#if defined(SPD_opteed)
+ /* NS dtb addr passed to optee_os */
+ bl32_image_ep_info.args.arg3 = XILINX_OF_BOARD_DTB_ADDR;
+#endif
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS);
+}
+
+/*
+ * Perform any BL31 specific platform actions. Here is an opportunity to copy
+ * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
+ * are lost (potentially). This needs to be done before the MMU is initialized
+ * so that the memory layout can be used while creating page tables.
+ */
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ uint32_t uart_clock;
+ int32_t rc;
+
+ board_detection();
+
+ /* FIXME */
+ switch (platform_id) {
+ case SPP:
+ switch (platform_version) {
+ case SPP_PSXC_MMI_V2_0:
+ cpu_clock = 770000;
+ break;
+ case SPP_PSXC_MMI_V3_0:
+ cpu_clock = 908000;
+ break;
+ default:
+ panic();
+ }
+ break;
+ case SPP_MMD:
+ switch (platform_version) {
+ case SPP_PSXC_ISP_AIE_V2_0:
+ case SPP_PSXC_MMD_AIE_FRZ_EA:
+ case SPP_PSXC_MMD_AIE_V3_0:
+ cpu_clock = 760000;
+ break;
+ default:
+ panic();
+ }
+ break;
+ case EMU:
+ case EMU_MMD:
+ cpu_clock = 112203;
+ break;
+ case QEMU:
+ /* Random values now */
+ cpu_clock = 3333333;
+ break;
+ case SILICON:
+ cpu_clock = 100000000;
+ break;
+ default:
+ panic();
+ }
+
+ uart_clock = get_uart_clk();
+
+ if (CONSOLE_IS(pl011_0) || CONSOLE_IS(pl011_1)) {
+ static console_t _runtime_console;
+
+ /* Initialize the console to provide early debug support */
+ rc = console_pl011_register(UART_BASE, uart_clock,
+ UART_BAUDRATE,
+ &_runtime_console);
+ if (rc == 0) {
+ panic();
+ }
+
+ console_set_scope(&_runtime_console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
+ } else if (CONSOLE_IS(dcc)) {
+ /* Initialize the dcc console for debug.
+ * dcc is over jtag and does not configures uart0 or uart1.
+ */
+ rc = console_dcc_register();
+ if (rc == 0) {
+ panic();
+ }
+ } else {
+ /* Making MISRA C 2012 15.7 compliant */
+ }
+
+ NOTICE("TF-A running on %s %d.%d\n", board_name_decode(),
+ platform_version / 10U, platform_version % 10U);
+
+ /* Initialize the platform config for future decision making */
+ config_setup();
+
+ /*
+ * Do initial security configuration to allow DRAM/device access. On
+ * Base only DRAM security is programmable (via TrustZone), but
+ * other platforms might have more programmable security devices
+ * present.
+ */
+
+ /* Populate common information for BL32 and BL33 */
+ SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
+ SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+ SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+ bl31_set_default_config();
+
+ long rev_var = cpu_get_rev_var();
+
+ INFO("CPU Revision = 0x%lx\n", rev_var);
+ INFO("cpu_clock = %dHz, uart_clock = %dHz\n", cpu_clock, uart_clock);
+ NOTICE("BL31: Executing from 0x%x\n", BL31_BASE);
+ NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
+ NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
+
+}
+
+static versal_intr_info_type_el3_t type_el3_interrupt_table[MAX_INTR_EL3];
+
+int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
+{
+ static uint32_t index;
+ uint32_t i;
+
+ /* Validate 'handler' and 'id' parameters */
+ if (handler == NULL || index >= MAX_INTR_EL3) {
+ return -EINVAL;
+ }
+
+ /* Check if a handler has already been registered */
+ for (i = 0; i < index; i++) {
+ if (id == type_el3_interrupt_table[i].id) {
+ return -EALREADY;
+ }
+ }
+
+ type_el3_interrupt_table[index].id = id;
+ type_el3_interrupt_table[index].handler = handler;
+
+ index++;
+
+ return 0;
+}
+
+static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
+ void *handle, void *cookie)
+{
+ uint32_t intr_id;
+ uint32_t i;
+ interrupt_type_handler_t handler = NULL;
+
+ intr_id = plat_ic_get_pending_interrupt_id();
+
+ for (i = 0; i < MAX_INTR_EL3; i++) {
+ if (intr_id == type_el3_interrupt_table[i].id) {
+ handler = type_el3_interrupt_table[i].handler;
+ }
+ }
+
+ if (handler != NULL) {
+ (void)handler(intr_id, flags, handle, cookie);
+ }
+
+ return 0;
+}
+
+void bl31_platform_setup(void)
+{
+ prepare_dtb();
+
+ /* Initialize the gic cpu and distributor interfaces */
+ plat_gic_driver_init();
+ plat_gic_init();
+
+ if (platform_id != EMU) {
+ init_scmi_server();
+ }
+}
+
+void bl31_plat_runtime_setup(void)
+{
+ uint64_t flags = 0;
+ int32_t rc;
+
+ set_interrupt_rm_flag(flags, NON_SECURE);
+ rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+ rdo_el3_interrupt_handler, flags);
+ if (rc != 0) {
+ panic();
+ }
+}
+
+/*
+ * Perform the very early platform specific architectural setup here.
+ */
+void bl31_plat_arch_setup(void)
+{
+ const mmap_region_t bl_regions[] = {
+#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
+ MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
+ MT_MEMORY | MT_RW | MT_NS),
+#endif
+ MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
+ MT_MEMORY | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
+ MT_CODE | MT_SECURE),
+ MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
+ MT_RO_DATA | MT_SECURE),
+ MAP_REGION_FLAT(SMT_BUFFER_BASE, 0x1000,
+ MT_DEVICE | MT_RW | MT_NON_CACHEABLE | MT_EXECUTE_NEVER | MT_NS),
+ {0}
+ };
+
+ setup_page_tables(bl_regions, plat_get_mmap());
+ enable_mmu(0);
+}
diff --git a/plat/amd/versal2/gicv3.c b/plat/amd/versal2/gicv3.c
new file mode 100644
index 0000000..c7b44e1
--- /dev/null
+++ b/plat/amd/versal2/gicv3.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/interrupt_props.h>
+#include <drivers/arm/gicv3.h>
+#include <lib/utils.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include <plat_private.h>
+
+/******************************************************************************
+ * The following functions are defined as weak to allow a platform to override
+ * the way the GICv3 driver is initialised and used.
+ *****************************************************************************/
+#pragma weak plat_gic_driver_init
+#pragma weak plat_gic_init
+#pragma weak plat_gic_cpuif_enable
+#pragma weak plat_gic_cpuif_disable
+#pragma weak plat_gic_pcpu_init
+#pragma weak plat_gic_redistif_on
+#pragma weak plat_gic_redistif_off
+
+/* The GICv3 driver only needs to be initialized in EL3 */
+static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+
+static const interrupt_prop_t _interrupt_props[] = {
+ PLAT_G1S_IRQ_PROPS(INTR_GROUP1S),
+ PLAT_G0_IRQ_PROPS(INTR_GROUP0)
+};
+
+/*
+ * We save and restore the GICv3 context on system suspend. Allocate the
+ * data in the designated EL3 Secure carve-out memory.
+ */
+static gicv3_redist_ctx_t rdist_ctx __section("._el3_tzc_dram");
+static gicv3_dist_ctx_t dist_ctx __section("._el3_tzc_dram");
+
+/*
+ * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
+ * to core position.
+ *
+ * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
+ * values read from GICR_TYPER don't have an MT field. To reuse the same
+ * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
+ * that read from GICR_TYPER.
+ *
+ * Assumptions:
+ *
+ * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
+ * - No CPUs implemented in the system use affinity level 3.
+ */
+static uint32_t _gicv3_mpidr_hash(u_register_t mpidr)
+{
+ mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
+ return plat_core_pos_by_mpidr(mpidr);
+}
+
+static const gicv3_driver_data_t _gic_data __unused = {
+ .gicd_base = PLAT_GICD_BASE_VALUE,
+ .gicr_base = PLAT_GICR_BASE_VALUE,
+ .interrupt_props = _interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(_interrupt_props),
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = rdistif_base_addrs,
+ .mpidr_to_core_pos = _gicv3_mpidr_hash
+};
+
+void __init plat_gic_driver_init(void)
+{
+ /*
+ * The GICv3 driver is initialized in EL3 and does not need
+ * to be initialized again in SEL1. This is because the S-EL1
+ * can use GIC system registers to manage interrupts and does
+ * not need GIC interface base addresses to be configured.
+ */
+#if IMAGE_BL31
+ gicv3_driver_init(&_gic_data);
+#endif
+}
+
+/******************************************************************************
+ * common helper to initialize the GIC. Only invoked by BL31
+ *****************************************************************************/
+void __init plat_gic_init(void)
+{
+ gicv3_distif_init();
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+/******************************************************************************
+ * common helper to enable the GIC CPU interface
+ *****************************************************************************/
+void plat_gic_cpuif_enable(void)
+{
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+/******************************************************************************
+ * common helper to disable the GIC CPU interface
+ *****************************************************************************/
+void plat_gic_cpuif_disable(void)
+{
+ gicv3_cpuif_disable(plat_my_core_pos());
+}
+
+/******************************************************************************
+ * common helper to initialize the per-cpu redistributor interface in GICv3
+ *****************************************************************************/
+void plat_gic_pcpu_init(void)
+{
+ gicv3_rdistif_init(plat_my_core_pos());
+}
+
+/******************************************************************************
+ * common helpers to power GIC redistributor interface
+ *****************************************************************************/
+void plat_gic_redistif_on(void)
+{
+ gicv3_rdistif_on(plat_my_core_pos());
+}
+
+void plat_gic_redistif_off(void)
+{
+ gicv3_rdistif_off(plat_my_core_pos());
+}
+
+/******************************************************************************
+ * common helper to save & restore the GICv3 on resume from system suspend
+ *****************************************************************************/
+void plat_gic_save(void)
+{
+ /*
+ * If an ITS is available, save its context before
+ * the Redistributor using:
+ * gicv3_its_save_disable(gits_base, &its_ctx[i])
+ * Additionnaly, an implementation-defined sequence may
+ * be required to save the whole ITS state.
+ */
+
+ /*
+ * Save the GIC Redistributors and ITS contexts before the
+ * Distributor context. As we only handle SYSTEM SUSPEND API,
+ * we only need to save the context of the CPU that is issuing
+ * the SYSTEM SUSPEND call, i.e. the current CPU.
+ */
+ gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
+
+ /* Save the GIC Distributor context */
+ gicv3_distif_save(&dist_ctx);
+
+ /*
+ * From here, all the components of the GIC can be safely powered down
+ * as long as there is an alternate way to handle wakeup interrupt
+ * sources.
+ */
+}
+
+void plat_gic_resume(void)
+{
+ /* Restore the GIC Distributor context */
+ gicv3_distif_init_restore(&dist_ctx);
+
+ /*
+ * Restore the GIC Redistributor and ITS contexts after the
+ * Distributor context. As we only handle SYSTEM SUSPEND API,
+ * we only need to restore the context of the CPU that issued
+ * the SYSTEM SUSPEND call.
+ */
+ gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
+
+ /*
+ * If an ITS is available, restore its context after
+ * the Redistributor using:
+ * gicv3_its_restore(gits_base, &its_ctx[i])
+ * An implementation-defined sequence may be required to
+ * restore the whole ITS state. The ITS must also be
+ * re-enabled after this sequence has been executed.
+ */
+}
diff --git a/plat/amd/versal2/include/def.h b/plat/amd/versal2/include/def.h
new file mode 100644
index 0000000..a8cbaaf
--- /dev/null
+++ b/plat/amd/versal2/include/def.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEF_H
+#define DEF_H
+
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+
+#define MAX_INTR_EL3 2
+
+/* List all consoles */
+#define CONSOLE_ID_pl011 U(1)
+#define CONSOLE_ID_pl011_0 U(1)
+#define CONSOLE_ID_pl011_1 U(2)
+#define CONSOLE_ID_dcc U(3)
+
+#define CONSOLE_IS(con) (CONSOLE_ID_ ## con == CONSOLE)
+
+/* List all platforms */
+#define SILICON U(0)
+#define SPP U(1)
+#define EMU U(2)
+#define QEMU U(3)
+#define SPP_MMD U(5)
+#define EMU_MMD U(6)
+#define QEMU_COSIM U(7)
+
+/* For platform detection */
+#define PMC_TAP U(0xF11A0000)
+#define PMC_TAP_VERSION (PMC_TAP + 0x4U)
+# define PLATFORM_MASK GENMASK(27U, 24U)
+# define PLATFORM_VERSION_MASK GENMASK(31U, 28U)
+
+/* Global timer reset */
+#define PSX_CRF U(0xEC200000)
+#define ACPU0_CLK_CTRL U(0x10C)
+#define ACPU_CLK_CTRL_CLKACT BIT(25)
+
+#define RST_APU0_OFFSET U(0x300)
+#define RST_APU_COLD_RESET BIT(0)
+#define RST_APU_WARN_RESET BIT(4)
+#define RST_APU_CLUSTER_COLD_RESET BIT(8)
+#define RST_APU_CLUSTER_WARM_RESET BIT(9)
+
+#define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C)
+
+#define APU_PCLI (0xECB10000ULL)
+#define APU_PCLI_CPU_STEP (0x30ULL)
+#define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP)
+#define APU_PCLI_CLUSTER_OFFSET U(0x8000)
+#define APU_PCLI_CLUSTER_STEP U(0x1000)
+#define PCLI_PREQ_OFFSET U(0x4)
+#define PREQ_CHANGE_REQUEST BIT(0)
+#define PCLI_PSTATE_OFFSET U(0x8)
+#define PCLI_PSTATE_VAL_SET U(0x48)
+#define PCLI_PSTATE_VAL_CLEAR U(0x38)
+
+/* Firmware Image Package */
+#define PRIMARY_CPU U(0)
+
+#define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL)
+#define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U)
+#define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL)
+#define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U)
+#define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL)
+#define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U)
+#define CORE_0_ISR_POWER_OFFSET (0x00000010ULL)
+#define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001)
+#define CORE_0_IEN_POWER_OFFSET (0x00000018ULL)
+#define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U)
+#define CORE_0_IDS_POWER_OFFSET (0x0000001CULL)
+#define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \
+ (APU_PCLI_CPU_STEP * (cpu_id))))
+#define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U)
+#define CORE_PWRDN_EN_BIT_MASK (0x1U)
+
+/*******************************************************************************
+ * memory map related constants
+ ******************************************************************************/
+/* IPP 1.2/SPP 0.9 mapping */
+#define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */
+#define DEVICE0_SIZE U(0x08000000)
+#define DEVICE1_BASE U(0xE2000000) /* gic */
+#define DEVICE1_SIZE U(0x00800000)
+#define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */
+#define DEVICE2_SIZE U(0x01000000)
+#define CRF_BASE U(0xFD1A0000)
+#define CRF_SIZE U(0x00600000)
+#define IPI_BASE U(0xEB300000)
+#define IPI_SIZE U(0x00100000)
+
+/* CRL */
+#define CRL U(0xEB5E0000)
+#define CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C)
+#define CRL_RST_TIMESTAMP_OFFSET U(0x348)
+
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
+
+/* IOU SCNTRS */
+#define IOU_SCNTRS U(0xEC920000)
+#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
+#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
+
+#define IOU_SCNTRS_CONTROL_EN U(1)
+
+#define APU_CLUSTER0 U(0xECC00000)
+#define APU_RVBAR_L_0 U(0x40)
+#define APU_RVBAR_H_0 U(0x44)
+#define APU_CLUSTER_STEP U(0x100000)
+
+#define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504)
+
+/*******************************************************************************
+ * IRQ constants
+ ******************************************************************************/
+#define IRQ_SEC_PHY_TIMER U(29)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE U(0xF1920000)
+#define UART1_BASE U(0xF1930000)
+
+#define UART_BAUDRATE 115200
+
+#if CONSOLE_IS(pl011_1)
+#define UART_BASE UART1_BASE
+#else
+/* Default console is UART0 */
+#define UART_BASE UART0_BASE
+#endif
+
+#endif /* DEF_H */
diff --git a/plat/amd/versal2/include/plat_ipi.h b/plat/amd/versal2/include/plat_ipi.h
new file mode 100644
index 0000000..503ec1f
--- /dev/null
+++ b/plat/amd/versal2/include/plat_ipi.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Versal Gen 2 IPI management enums and defines */
+
+#ifndef PLAT_IPI_H
+#define PLAT_IPI_H
+
+#include <stdint.h>
+
+#include <ipi.h>
+
+/*********************************************************************
+ * IPI agent IDs macros
+ ********************************************************************/
+#define IPI_ID_PMC 1U
+#define IPI_ID_APU 2U
+#define IPI_ID_RPU0 3U
+#define IPI_ID_RPU1 4U
+#define IPI_ID_3 5U
+#define IPI_ID_4 6U
+#define IPI_ID_5 7U
+#define IPI_ID_MAX 8U
+
+/*********************************************************************
+ * IPI message buffers
+ ********************************************************************/
+#define IPI_BUFFER_BASEADDR (0xEB3F0000U)
+
+#define IPI_LOCAL_ID IPI_ID_APU
+#define IPI_REMOTE_ID IPI_ID_PMC
+
+#define IPI_BUFFER_LOCAL_BASE (IPI_BUFFER_BASEADDR + (IPI_LOCAL_ID * 0x200U))
+#define IPI_BUFFER_REMOTE_BASE (IPI_BUFFER_BASEADDR + (IPI_REMOTE_ID * 0x200U))
+
+#define IPI_BUFFER_TARGET_LOCAL_OFFSET (IPI_LOCAL_ID * 0x40U)
+#define IPI_BUFFER_TARGET_REMOTE_OFFSET (IPI_REMOTE_ID * 0x40U)
+
+#define IPI_BUFFER_MAX_WORDS 8
+
+#define IPI_BUFFER_REQ_OFFSET 0x0U
+#define IPI_BUFFER_RESP_OFFSET 0x20U
+
+/*********************************************************************
+ * Platform specific IPI API declarations
+ ********************************************************************/
+
+/* Configure IPI table */
+extern void soc_ipi_config_table_init(void);
+
+/*******************************************************************************
+ * IPI registers and bitfields
+ ******************************************************************************/
+#define IPI0_REG_BASE (0xEB330000U)
+#define IPI0_TRIG_BIT (1 << 2)
+#define PMC_IPI_TRIG_BIT (1 << 1)
+#define IPI1_REG_BASE (0xEB340000U)
+#define IPI1_TRIG_BIT (1 << 3)
+#define IPI2_REG_BASE (0xEB350000U)
+#define IPI2_TRIG_BIT (1 << 4)
+#define IPI3_REG_BASE (0xEB360000U)
+#define IPI3_TRIG_BIT (1 << 5)
+#define IPI4_REG_BASE (0xEB370000U)
+#define IPI4_TRIG_BIT (1 << 6)
+#define IPI5_REG_BASE (0xEB380000U)
+#define IPI5_TRIG_BIT (1 << 7)
+
+#endif /* PLAT_IPI_H */
diff --git a/plat/amd/versal2/include/plat_macros.S b/plat/amd/versal2/include/plat_macros.S
new file mode 100644
index 0000000..d20f693
--- /dev/null
+++ b/plat/amd/versal2/include/plat_macros.S
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/arm/gicv3.h>
+
+#include "../include/platform_def.h"
+
+.section .rodata.gic_reg_name, "aS"
+/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
+gicc_regs:
+ .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+
+/* Applicable only to GICv3 with SRE enabled */
+icc_regs:
+ .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
+
+/* Registers common to both GICv2 and GICv3 */
+gicd_pend_reg:
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
+newline:
+ .asciz "\n"
+spacer:
+ .asciz ":\t\t0x"
+
+ /* ---------------------------------------------
+ * The below utility macro prints out relevant GIC
+ * registers whenever an unhandled exception is
+ * taken in BL31 on platform.
+ * Expects: GICD base in x16, GICC base in x17
+ * Clobbers: x0 - x10, sp
+ * ---------------------------------------------
+ */
+ .macro _print_gic_regs
+ /* Check for GICv3 system register access */
+ mrs x7, id_aa64pfr0_el1
+ ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
+ cmp x7, #1
+ b.ne print_gicv2
+
+ /* Check for SRE enable */
+ mrs x8, ICC_SRE_EL3
+ tst x8, #ICC_SRE_SRE_BIT
+ b.eq print_gicv2
+
+ /* Load the icc reg list to x6 */
+ adr x6, icc_regs
+ /* Load the icc regs to gp regs used by str_in_crash_buf_print */
+ mrs x8, ICC_HPPIR0_EL1
+ mrs x9, ICC_HPPIR1_EL1
+ mrs x10, ICC_CTLR_EL3
+ /* Store to the crash buf and print to console */
+ bl str_in_crash_buf_print
+ b print_gic_common
+
+print_gicv2:
+ /* Load the gicc reg list to x6 */
+ adr x6, gicc_regs
+ /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
+ ldr w8, [x17, #GICC_HPPIR]
+ ldr w9, [x17, #GICC_AHPPIR]
+ ldr w10, [x17, #GICC_CTLR]
+ /* Store to the crash buf and print to console */
+ bl str_in_crash_buf_print
+
+print_gic_common:
+ /* Print the GICD_ISPENDR regs */
+ add x7, x16, #GICD_ISPENDR
+ adr x4, gicd_pend_reg
+ bl asm_print_str
+gicd_ispendr_loop:
+ sub x4, x7, x16
+ cmp x4, #0x280
+ b.eq exit_print_gic_regs
+ bl asm_print_hex
+
+ adr x4, spacer
+ bl asm_print_str
+
+ ldr x4, [x7], #8
+ bl asm_print_hex
+
+ adr x4, newline
+ bl asm_print_str
+ b gicd_ispendr_loop
+exit_print_gic_regs:
+ .endm
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant GIC and CCI registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * Clobbers: x0 - x10, x16, x17, sp
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ /*
+ * Empty for now to handle more platforms variant.
+ * Uncomment it when versions are stable
+ */
+ /*
+ mov_imm x17, PLAT_GICD_BASE_VALUE
+ mov_imm x16, PLAT_GICR_BASE_VALUE
+ _print_gic_regs
+ */
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/amd/versal2/include/plat_pm_common.h b/plat/amd/versal2/include/plat_pm_common.h
new file mode 100644
index 0000000..5e68472
--- /dev/null
+++ b/plat/amd/versal2/include/plat_pm_common.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Contains platform specific definitions of commonly used macros data types
+ * for PU Power Management. This file should be common for all PU's.
+ */
+
+#ifndef PLAT_PM_COMMON_H
+#define PLAT_PM_COMMON_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+#include "pm_defs.h"
+
+#define NON_SECURE_FLAG 1U
+#define SECURE_FLAG 0U
+
+#endif /* PLAT_PM_COMMON_H */
diff --git a/plat/amd/versal2/include/plat_private.h b/plat/amd/versal2/include/plat_private.h
new file mode 100644
index 0000000..5a2e5bd
--- /dev/null
+++ b/plat/amd/versal2/include/plat_private.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+#include <bl31/interrupt_mgmt.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#define SPP_PSXC_MMI_V2_0 U(6)
+#define SPP_PSXC_MMI_V3_0 U(8)
+
+/* MMD */
+#define SPP_PSXC_ISP_AIE_V2_0 U(3)
+#define SPP_PSXC_MMD_AIE_FRZ_EA U(4)
+#define SPP_PSXC_MMD_AIE_V3_0 U(5)
+
+typedef struct versal_intr_info_type_el3 {
+ uint32_t id;
+ interrupt_type_handler_t handler;
+} versal_intr_info_type_el3_t;
+
+void config_setup(void);
+uint32_t get_uart_clk(void);
+
+const mmap_region_t *plat_get_mmap(void);
+
+void plat_gic_driver_init(void);
+void plat_gic_init(void);
+void plat_gic_cpuif_enable(void);
+void plat_gic_cpuif_disable(void);
+void plat_gic_pcpu_init(void);
+void plat_gic_save(void);
+void plat_gic_resume(void);
+void plat_gic_redistif_on(void);
+void plat_gic_redistif_off(void);
+
+extern uint32_t cpu_clock, platform_id, platform_version;
+void board_detection(void);
+const char *board_name_decode(void);
+uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
+ uint64_t x4, void *cookie, void *handle, uint64_t flags);
+int32_t sip_svc_setup_init(void);
+/*
+ * Register handler to specific GIC entrance
+ * for INTR_TYPE_EL3 type of interrupt
+ */
+int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/amd/versal2/include/platform_def.h b/plat/amd/versal2/include/platform_def.h
new file mode 100644
index 0000000..090fe46
--- /dev/null
+++ b/plat/amd/versal2/include/platform_def.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include "def.h"
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stacks */
+#define PLATFORM_STACK_SIZE U(0x440)
+
+#define PLATFORM_CLUSTER_COUNT U(4)
+#define PLATFORM_CORE_COUNT_PER_CLUSTER U(2) /* 2 CPUs per cluster */
+
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * PLATFORM_CORE_COUNT_PER_CLUSTER)
+
+#define PLAT_MAX_PWR_LVL U(2)
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(2)
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL31 debug size plus a
+ * little space for growth.
+ */
+#ifndef MEM_BASE
+# define BL31_BASE U(0xBBF00000)
+# define BL31_LIMIT U(0xBC000000)
+#else
+# define BL31_BASE U(MEM_BASE)
+# define BL31_LIMIT U(MEM_BASE + MEM_SIZE)
+# ifdef MEM_PROGBITS_SIZE
+# define BL31_PROGBITS_LIMIT U(MEM_BASE + \
+ MEM_PROGBITS_SIZE)
+# endif
+#endif
+
+/*******************************************************************************
+ * BL32 specific defines.
+ ******************************************************************************/
+#ifndef BL32_MEM_BASE
+# define BL32_BASE U(0x60000000)
+# define BL32_LIMIT U(0x80000000)
+#else
+# define BL32_BASE U(BL32_MEM_BASE)
+# define BL32_LIMIT U(BL32_MEM_BASE + BL32_MEM_SIZE)
+#endif
+
+/*******************************************************************************
+ * BL33 specific defines.
+ ******************************************************************************/
+#ifndef PRELOADED_BL33_BASE
+# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
+#else
+# define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE)
+#endif
+
+/*******************************************************************************
+ * TSP specific defines.
+ ******************************************************************************/
+#define TSP_SEC_MEM_BASE BL32_BASE
+#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE)
+
+/* ID of the secure physical generic timer interrupt used by the TSP */
+#define ARM_IRQ_SEC_PHY_TIMER U(29)
+#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_DDR_LOWMEM_MAX U(0x80000000)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32U)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32U)
+
+#define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000)
+
+#define PLAT_OCM_BASE U(0xBBF00000)
+#define PLAT_OCM_LIMIT U(0xBC000000)
+
+#if defined(TRANSFER_LIST)
+/*
+ * FIXME: This address should come from firmware before TF-A
+ * Having this to make sure the transfer list functionality works
+ */
+#define FW_HANDOFF_BASE U(0x70000000)
+#define FW_HANDOFF_SIZE U(0x10000)
+#endif
+
+#define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT))
+
+#ifndef MAX_MMAP_REGIONS
+#if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE))
+#define MAX_MMAP_REGIONS 11
+#else
+#define MAX_MMAP_REGIONS 10
+#endif
+#endif
+
+#ifndef MAX_XLAT_TABLES
+#define MAX_XLAT_TABLES U(12)
+#endif
+
+#define CACHE_WRITEBACK_SHIFT U(6)
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+#define PLAT_GICD_BASE_VALUE U(0xE2000000)
+#define PLAT_GICR_BASE_VALUE U(0xE2060000)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_IPI_IRQ 89
+#define PLAT_VERSAL_IPI_IRQ PLAT_IPI_IRQ
+
+#define PLAT_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+#define PLAT_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+
+#define IRQ_MAX 200U
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/amd/versal2/include/scmi.h b/plat/amd/versal2/include/scmi.h
new file mode 100644
index 0000000..0ab8b34
--- /dev/null
+++ b/plat/amd/versal2/include/scmi.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SCMI_H
+#define SCMI_H
+
+#include "versal2-scmi.h"
+
+#define SIP_SCMI (0xC200ffffU)
+#define SMT_BUFFER_BASE 0x7fffe000
+
+void init_scmi_server(void);
+
+#define SCMI_VENDOR "AMD"
+#define SCMI_PRODUCT "Versal Gen 2"
+
+#endif /* DEF_H */
diff --git a/plat/amd/versal2/include/versal2-scmi.h b/plat/amd/versal2/include/versal2-scmi.h
new file mode 100644
index 0000000..4d581e4
--- /dev/null
+++ b/plat/amd/versal2/include/versal2-scmi.h
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
+/*
+ * Macros IDs for AMD Versal Gen 2
+ *
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#ifndef _VERSAL2_SCMI_H
+#define _VERSAL2_SCMI_H
+
+#define CLK_GEM0_0 0
+#define CLK_GEM0_1 1
+#define CLK_GEM0_2 2
+#define CLK_GEM0_3 3
+#define CLK_GEM0_4 4
+#define CLK_GEM1_0 5
+#define CLK_GEM1_1 6
+#define CLK_GEM1_2 7
+#define CLK_GEM1_3 8
+#define CLK_GEM1_4 9
+#define CLK_SERIAL0_0 10
+#define CLK_SERIAL0_1 11
+#define CLK_SERIAL1_0 12
+#define CLK_SERIAL1_1 13
+#define CLK_UFS0_0 14
+#define CLK_UFS0_1 15
+#define CLK_UFS0_2 16
+#define CLK_USB0_0 17
+#define CLK_USB0_1 18
+#define CLK_USB0_2 19
+#define CLK_USB1_0 20
+#define CLK_USB1_1 21
+#define CLK_USB1_2 22
+#define CLK_MMC0_0 23
+#define CLK_MMC0_1 24
+#define CLK_MMC0_2 25
+#define CLK_MMC1_0 26
+#define CLK_MMC1_1 27
+#define CLK_MMC1_2 28
+#define CLK_TTC0_0 29
+#define CLK_TTC1_0 30
+#define CLK_TTC2_0 31
+#define CLK_TTC3_0 32
+#define CLK_TTC4_0 33
+#define CLK_TTC5_0 34
+#define CLK_TTC6_0 35
+#define CLK_TTC7_0 36
+#define CLK_I2C0_0 37
+#define CLK_I2C1_0 38
+#define CLK_I2C2_0 39
+#define CLK_I2C3_0 40
+#define CLK_I2C4_0 41
+#define CLK_I2C5_0 42
+#define CLK_I2C6_0 43
+#define CLK_I2C7_0 44
+#define CLK_OSPI0_0 45
+#define CLK_QSPI0_0 46
+#define CLK_QSPI0_1 47
+#define CLK_WWDT0_0 48
+#define CLK_WWDT1_0 49
+#define CLK_WWDT2_0 50
+#define CLK_WWDT3_0 51
+#define CLK_ADMA0_0 52
+#define CLK_ADMA0_1 53
+#define CLK_ADMA1_0 54
+#define CLK_ADMA1_1 55
+#define CLK_ADMA2_0 56
+#define CLK_ADMA2_1 57
+#define CLK_ADMA3_0 58
+#define CLK_ADMA3_1 59
+#define CLK_ADMA4_0 60
+#define CLK_ADMA4_1 61
+#define CLK_ADMA5_0 62
+#define CLK_ADMA5_1 63
+#define CLK_ADMA6_0 64
+#define CLK_ADMA6_1 65
+#define CLK_ADMA7_0 66
+#define CLK_ADMA7_1 67
+#define CLK_CAN0_0 68
+#define CLK_CAN0_1 69
+#define CLK_CAN1_0 70
+#define CLK_CAN1_1 71
+#define CLK_CAN2_0 72
+#define CLK_CAN2_1 73
+#define CLK_CAN3_0 74
+#define CLK_CAN3_1 75
+#define CLK_PS_GPIO_0 76
+#define CLK_PMC_GPIO_0 77
+#define CLK_SPI0_0 78
+#define CLK_SPI0_1 79
+#define CLK_SPI1_0 80
+#define CLK_SPI1_1 81
+#define CLK_I3C0_0 82
+#define CLK_I3C1_0 83
+#define CLK_I3C2_0 84
+#define CLK_I3C3_0 85
+#define CLK_I3C4_0 86
+#define CLK_I3C5_0 87
+#define CLK_I3C6_0 88
+#define CLK_I3C7_0 89
+
+#define RESET_GEM0_0 0
+#define RESET_GEM1_0 1
+#define RESET_SERIAL0_0 2
+#define RESET_SERIAL1_0 3
+#define RESET_UFS0_0 4
+#define RESET_I2C0_0 5
+#define RESET_I2C1_0 6
+#define RESET_I2C2_0 7
+#define RESET_I2C3_0 8
+#define RESET_I2C4_0 9
+#define RESET_I2C5_0 10
+#define RESET_I2C6_0 11
+#define RESET_I2C7_0 12
+#define RESET_I2C8_0 13
+#define RESET_OSPI0_0 14
+#define RESET_USB0_0 15
+#define RESET_USB0_1 16
+#define RESET_USB0_2 17
+#define RESET_USB1_0 18
+#define RESET_USB1_1 19
+#define RESET_USB1_2 20
+#define RESET_MMC0_0 21
+#define RESET_MMC1_0 22
+#define RESET_SPI0_0 23
+#define RESET_SPI1_0 24
+#define RESET_QSPI0_0 25
+#define RESET_I3C0_0 26
+#define RESET_I3C1_0 27
+#define RESET_I3C2_0 28
+#define RESET_I3C3_0 29
+#define RESET_I3C4_0 30
+#define RESET_I3C5_0 31
+#define RESET_I3C6_0 32
+#define RESET_I3C7_0 33
+#define RESET_I3C8_0 34
+
+#endif /* _VERSAL2_SCMI_H */
diff --git a/plat/amd/versal2/plat_psci.c b/plat/amd/versal2/plat_psci.c
new file mode 100644
index 0000000..4faa434
--- /dev/null
+++ b/plat/amd/versal2/plat_psci.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <plat_arm.h>
+
+#include <plat_private.h>
+#include <pm_defs.h>
+
+#define PM_RET_ERROR_NOFEATURE U(19)
+#define ALWAYSTRUE true
+
+static uintptr_t _sec_entry;
+
+static void zynqmp_cpu_standby(plat_local_state_t cpu_state)
+{
+ dsb();
+ wfi();
+}
+
+#define MPIDR_MT_BIT (24)
+
+static int32_t zynqmp_nopmu_pwr_domain_on(u_register_t mpidr)
+{
+ uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr) & ~BIT(MPIDR_MT_BIT);
+ uint32_t cpu = cpu_id % PLATFORM_CORE_COUNT_PER_CLUSTER;
+ uint32_t cluster = cpu_id / PLATFORM_CORE_COUNT_PER_CLUSTER;
+ uintptr_t apu_cluster_base = 0, apu_pcli_base, apu_pcli_cluster = 0;
+ uintptr_t rst_apu_cluster = PSX_CRF + RST_APU0_OFFSET + ((uint64_t)cluster * 0x4U);
+
+ VERBOSE("%s: mpidr: 0x%lx, cpuid: %x, cpu: %x, cluster: %x\n",
+ __func__, mpidr, cpu_id, cpu, cluster);
+
+ if (cpu_id == -1) {
+ return PSCI_E_INTERN_FAIL;
+ }
+
+ if (cluster > 3) {
+ panic();
+ }
+
+ apu_pcli_cluster = APU_PCLI + APU_PCLI_CLUSTER_OFFSET + ((uint64_t)cluster * APU_PCLI_CLUSTER_STEP);
+ apu_cluster_base = APU_CLUSTER0 + ((uint64_t)cluster * APU_CLUSTER_STEP);
+
+ /* Enable clock */
+ mmio_setbits_32(PSX_CRF + ACPU0_CLK_CTRL + ((uint64_t)cluster * 0x4U), ACPU_CLK_CTRL_CLKACT);
+
+ /* Enable cluster states */
+ mmio_setbits_32(apu_pcli_cluster + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_SET);
+ mmio_setbits_32(apu_pcli_cluster + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST);
+
+ /* assert core reset */
+ mmio_setbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu));
+
+ /* program RVBAR */
+ mmio_write_32(apu_cluster_base + APU_RVBAR_L_0 + (cpu << 3),
+ (uint32_t)_sec_entry);
+ mmio_write_32(apu_cluster_base + APU_RVBAR_H_0 + (cpu << 3),
+ _sec_entry >> 32);
+
+ /* de-assert core reset */
+ mmio_clrbits_32(rst_apu_cluster, ((RST_APU_COLD_RESET|RST_APU_WARN_RESET) << cpu));
+
+ /* clear cluster resets */
+ mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_WARM_RESET);
+ mmio_clrbits_32(rst_apu_cluster, RST_APU_CLUSTER_COLD_RESET);
+
+ apu_pcli_base = APU_PCLI + (APU_PCLI_CPU_STEP * cpu) +
+ (APU_PCLI_CLUSTER_CPU_STEP * cluster);
+
+ mmio_write_32(apu_pcli_base + PCLI_PSTATE_OFFSET, PCLI_PSTATE_VAL_CLEAR);
+ mmio_write_32(apu_pcli_base + PCLI_PREQ_OFFSET, PREQ_CHANGE_REQUEST);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ plat_gic_cpuif_disable();
+}
+
+static void __dead2 zynqmp_nopmu_system_reset(void)
+{
+ while (ALWAYSTRUE) {
+ wfi();
+ }
+}
+
+static int32_t zynqmp_validate_ns_entrypoint(uint64_t ns_entrypoint)
+{
+ VERBOSE("Validate ns_entry point %lx\n", ns_entrypoint);
+
+ if ((ns_entrypoint) != 0U) {
+ return PSCI_E_SUCCESS;
+ } else {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+}
+
+static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ plat_gic_pcpu_init();
+ plat_gic_cpuif_enable();
+}
+
+static void __dead2 zynqmp_system_off(void)
+{
+ while (ALWAYSTRUE) {
+ wfi();
+ }
+}
+
+static int32_t zynqmp_validate_power_state(uint32_t power_state, psci_power_state_t *req_state)
+{
+ return PSCI_E_SUCCESS;
+}
+
+static const struct plat_psci_ops _nopmc_psci_ops = {
+ .cpu_standby = zynqmp_cpu_standby,
+ .pwr_domain_on = zynqmp_nopmu_pwr_domain_on,
+ .pwr_domain_off = zynqmp_nopmu_pwr_domain_off,
+ .system_reset = zynqmp_nopmu_system_reset,
+ .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint,
+ .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish,
+ .system_off = zynqmp_system_off,
+ .validate_power_state = zynqmp_validate_power_state,
+};
+
+/*******************************************************************************
+ * Export the platform specific power ops.
+ ******************************************************************************/
+int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const struct plat_psci_ops **psci_ops)
+{
+ _sec_entry = sec_entrypoint;
+
+ VERBOSE("Setting up entry point %lx\n", _sec_entry);
+
+ *psci_ops = &_nopmc_psci_ops;
+
+ return 0;
+}
+
+int sip_svc_setup_init(void)
+{
+ return 0;
+}
+
+static int32_t no_pm_ioctl(uint32_t device_id, uint32_t ioctl_id,
+ uint32_t arg1, uint32_t arg2)
+{
+ VERBOSE("%s: ioctl_id: %x, arg1: %x\n", __func__, ioctl_id, arg1);
+ if (ioctl_id == IOCTL_OSPI_MUX_SELECT) {
+ mmio_write_32(SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL, arg1);
+ return 0;
+ }
+ return PM_RET_ERROR_NOFEATURE;
+}
+
+static uint64_t no_pm_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
+ uint64_t x4, void *cookie, void *handle, uint64_t flags)
+{
+ int32_t ret;
+ uint32_t arg[4], api_id;
+
+ arg[0] = (uint32_t)x1;
+ arg[1] = (uint32_t)(x1 >> 32);
+ arg[2] = (uint32_t)x2;
+ arg[3] = (uint32_t)(x2 >> 32);
+
+ api_id = smc_fid & FUNCID_NUM_MASK;
+ VERBOSE("%s: smc_fid: %x, api_id=0x%x\n", __func__, smc_fid, api_id);
+
+ switch (api_id) {
+ case PM_IOCTL:
+ {
+ ret = no_pm_ioctl(arg[0], arg[1], arg[2], arg[3]);
+ SMC_RET1(handle, (uint64_t)ret);
+ }
+ case PM_GET_CHIPID:
+ {
+ uint32_t idcode, version;
+
+ idcode = mmio_read_32(PMC_TAP);
+ version = mmio_read_32(PMC_TAP_VERSION);
+ SMC_RET2(handle, ((uint64_t)idcode << 32), version);
+ }
+ default:
+ WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ }
+}
+
+uint64_t smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+ void *cookie, void *handle, uint64_t flags)
+{
+ return no_pm_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+}
diff --git a/plat/amd/versal2/plat_topology.c b/plat/amd/versal2/plat_topology.c
new file mode 100644
index 0000000..0763139
--- /dev/null
+++ b/plat/amd/versal2/plat_topology.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include <plat_private.h>
+
+static const uint8_t plat_power_domain_tree_desc[] = {
+ /* Number of root nodes */
+ 1,
+ /* Number of clusters */
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the first cluster node */
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+ /* Number of children for the second cluster node */
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+ /* Number of children for the third cluster node */
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+ /* Number of children for the fourth cluster node */
+ PLATFORM_CORE_COUNT_PER_CLUSTER,
+};
+
+const uint8_t *plat_get_power_domain_tree_desc(void)
+{
+ return plat_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ uint32_t cluster_id, cpu_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ cluster_id = MPIDR_AFFLVL2_VAL(mpidr);
+ cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
+
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+ return -3;
+ }
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in
+ * one of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) {
+ return -1;
+ }
+
+ return (cpu_id + (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER));
+}
diff --git a/plat/amd/versal2/platform.mk b/plat/amd/versal2/platform.mk
new file mode 100644
index 0000000..c07fc36
--- /dev/null
+++ b/plat/amd/versal2/platform.mk
@@ -0,0 +1,127 @@
+# Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved.
+# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+PLAT_PATH := plat/amd/versal2
+
+# A78 Erratum for SoC
+ERRATA_A78_AE_1941500 := 1
+ERRATA_A78_AE_1951502 := 1
+ERRATA_A78_AE_2376748 := 1
+ERRATA_A78_AE_2395408 := 1
+ERRATA_ABI_SUPPORT := 1
+
+# Platform Supports Armv8.2 extensions
+ARM_ARCH_MAJOR := 8
+ARM_ARCH_MINOR := 2
+
+override PROGRAMMABLE_RESET_ADDRESS := 1
+PSCI_EXTENDED_STATE_ID := 1
+SEPARATE_CODE_AND_RODATA := 1
+override RESET_TO_BL31 := 1
+PL011_GENERIC_UART := 1
+IPI_CRC_CHECK := 0
+GIC_ENABLE_V4_EXTN := 0
+GICV3_SUPPORT_GIC600 := 1
+
+override CTX_INCLUDE_AARCH32_REGS := 0
+
+ifdef MEM_BASE
+ $(eval $(call add_define,MEM_BASE))
+
+ ifndef MEM_SIZE
+ $(error "ATF_BASE defined without ATF_SIZE")
+ endif
+ $(eval $(call add_define,MEM_SIZE))
+
+ ifdef MEM_PROGBITS_SIZE
+ $(eval $(call add_define,MEM_PROGBITS_SIZE))
+ endif
+endif
+
+ifdef BL32_MEM_BASE
+ $(eval $(call add_define,BL32_MEM_BASE))
+
+ ifndef BL32_MEM_SIZE
+ $(error "BL32_BASE defined without BL32_SIZE")
+ endif
+ $(eval $(call add_define,BL32_MEM_SIZE))
+endif
+
+ifdef IPI_CRC_CHECK
+ $(eval $(call add_define,IPI_CRC_CHECK))
+endif
+
+USE_COHERENT_MEM := 0
+HW_ASSISTED_COHERENCY := 1
+
+CONSOLE ?= pl011
+ifeq (${CONSOLE}, $(filter ${CONSOLE},pl011 pl011_0 pl011_1 dcc))
+else
+ $(error Please define CONSOLE)
+endif
+
+$(eval $(call add_define_val,CONSOLE,CONSOLE_ID_${CONSOLE}))
+
+ifdef XILINX_OF_BOARD_DTB_ADDR
+$(eval $(call add_define,XILINX_OF_BOARD_DTB_ADDR))
+endif
+
+PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
+ -Iplat/xilinx/common/include/ \
+ -Iplat/xilinx/common/ipi_mailbox_service/ \
+ -I${PLAT_PATH}/include/ \
+ -Iplat/xilinx/versal/pm_service/
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+include lib/libfdt/libfdt.mk
+
+PLAT_BL_COMMON_SOURCES := \
+ drivers/arm/dcc/dcc_console.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ ${GICV3_SOURCES} \
+ drivers/arm/pl011/aarch64/pl011_console.S \
+ plat/common/aarch64/crash_console_helpers.S \
+ plat/arm/common/arm_common.c \
+ plat/common/plat_gicv3.c \
+ ${PLAT_PATH}/aarch64/helpers.S \
+ ${PLAT_PATH}/aarch64/common.c \
+ ${PLAT_PATH}/plat_topology.c \
+ ${XLAT_TABLES_LIB_SRCS}
+
+BL31_SOURCES += drivers/arm/cci/cci.c \
+ lib/cpus/aarch64/cortex_a78_ae.S \
+ lib/cpus/aarch64/cortex_a78.S \
+ plat/common/plat_psci_common.c \
+ drivers/scmi-msg/base.c \
+ drivers/scmi-msg/entry.c \
+ drivers/scmi-msg/smt.c \
+ drivers/scmi-msg/clock.c \
+ drivers/scmi-msg/power_domain.c \
+ drivers/scmi-msg/reset_domain.c \
+ ${PLAT_PATH}/scmi.c
+
+BL31_SOURCES += ${PLAT_PATH}/plat_psci.c
+
+BL31_SOURCES += plat/xilinx/common/plat_fdt.c \
+ plat/xilinx/common/plat_startup.c \
+ plat/xilinx/common/ipi.c \
+ plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
+ ${PLAT_PATH}/soc_ipi.c \
+ plat/xilinx/common/versal.c \
+ ${PLAT_PATH}/bl31_setup.c \
+ common/fdt_fixup.c \
+ ${LIBFDT_SRCS} \
+ ${PLAT_PATH}/sip_svc_setup.c \
+ ${PLAT_PATH}/gicv3.c
+
+ifeq (${ERRATA_ABI_SUPPORT}, 1)
+# enable the cpu macros for errata abi interface
+CORTEX_A78_AE_H_INC := 1
+$(eval $(call add_define, CORTEX_A78_AE_H_INC))
+endif
diff --git a/plat/amd/versal2/scmi.c b/plat/amd/versal2/scmi.c
new file mode 100644
index 0000000..c3c517a
--- /dev/null
+++ b/plat/amd/versal2/scmi.c
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <inttypes.h>
+
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
+#include <lib/utils_def.h>
+#include <platform_def.h>
+#include <scmi.h>
+
+#include "plat_private.h"
+
+#define HIGH (1)
+#define LOW (0)
+
+struct scmi_clk {
+ unsigned long clock_id;
+ unsigned long rate;
+ const char *name;
+ bool enabled;
+};
+
+#define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \
+ [_scmi_id] = { \
+ .clock_id = (_id), \
+ .name = (_name), \
+ .enabled = (_init_enabled), \
+ .rate = (_rate), \
+ }
+
+static struct scmi_clk scmi0_clock[] = {
+ CLOCK_CELL(CLK_GEM0_0, CLK_GEM0_0, "gem0_pclk", true, 100000000),
+ CLOCK_CELL(CLK_GEM0_1, CLK_GEM0_1, "gem0_hclk", true, 100000000),
+ CLOCK_CELL(CLK_GEM0_2, CLK_GEM0_2, "gem0_tx_clk", true, 125000000),
+ CLOCK_CELL(CLK_GEM0_3, CLK_GEM0_3, "gem0_rx_clk", true, 100000000),
+ CLOCK_CELL(CLK_GEM0_4, CLK_GEM0_4, "gem0_tsu_clk", true, 100000000),
+ CLOCK_CELL(CLK_GEM1_0, CLK_GEM1_0, "gem1_pclk", true, 100000000),
+ CLOCK_CELL(CLK_GEM1_1, CLK_GEM1_1, "gem1_hclk", true, 100000000),
+ CLOCK_CELL(CLK_GEM1_2, CLK_GEM1_2, "gem1_tx_clk", true, 125000000),
+ CLOCK_CELL(CLK_GEM1_3, CLK_GEM1_3, "gem1_rx_clk", true, 100000000),
+ CLOCK_CELL(CLK_GEM1_4, CLK_GEM1_4, "gem1_tsu_clk", true, 100000000),
+ CLOCK_CELL(CLK_SERIAL0_0, CLK_SERIAL0_0, "uart0_uartclk", true, 100000000),
+ CLOCK_CELL(CLK_SERIAL0_1, CLK_SERIAL0_1, "uart0_apb_pclk", true, 100000000),
+ CLOCK_CELL(CLK_SERIAL1_0, CLK_SERIAL1_0, "uart1_uartclk", true, 100000000),
+ CLOCK_CELL(CLK_SERIAL1_1, CLK_SERIAL1_1, "uart1_apb_pclk", true, 100000000),
+ CLOCK_CELL(CLK_UFS0_0, CLK_UFS0_0, "ufs_core_clk", true, 100000000),
+ CLOCK_CELL(CLK_UFS0_1, CLK_UFS0_1, "ufs_phy_clk", true, 100000000),
+ CLOCK_CELL(CLK_UFS0_2, CLK_UFS0_2, "ufs_ref_pclk", true, 100000000),
+ CLOCK_CELL(CLK_USB0_0, CLK_USB0_0, "usb0_bus_clk", true, 100000000),
+ CLOCK_CELL(CLK_USB0_1, CLK_USB0_1, "usb0_ref_clk", true, 100000000),
+ CLOCK_CELL(CLK_USB0_2, CLK_USB0_2, "usb0_dwc_clk", true, 100000000),
+ CLOCK_CELL(CLK_USB1_0, CLK_USB1_0, "usb1_bus_clk", true, 100000000),
+ CLOCK_CELL(CLK_USB1_1, CLK_USB1_1, "usb1_ref_clk", true, 100000000),
+ CLOCK_CELL(CLK_USB1_2, CLK_USB1_2, "usb1_dwc_clk", true, 100000000),
+ CLOCK_CELL(CLK_MMC0_0, CLK_MMC0_0, "mmc0_xin_clk", true, 100000000),
+ CLOCK_CELL(CLK_MMC0_1, CLK_MMC0_1, "mmc0_ahb_clk", true, 100000000),
+ CLOCK_CELL(CLK_MMC0_2, CLK_MMC0_2, "mmc0_gate_clk", true, 100000000),
+ CLOCK_CELL(CLK_MMC1_0, CLK_MMC1_0, "mmc1_xin_clk", true, 100000000),
+ CLOCK_CELL(CLK_MMC1_1, CLK_MMC1_1, "mmc1_ahb_clk", true, 100000000),
+ CLOCK_CELL(CLK_MMC1_2, CLK_MMC1_2, "mmc1_gate_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC0_0, CLK_TTC0_0, "ttc0_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC1_0, CLK_TTC1_0, "ttc1_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC2_0, CLK_TTC2_0, "ttc2_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC3_0, CLK_TTC3_0, "ttc3_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC4_0, CLK_TTC4_0, "ttc4_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC5_0, CLK_TTC5_0, "ttc5_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC6_0, CLK_TTC6_0, "ttc6_clk", true, 100000000),
+ CLOCK_CELL(CLK_TTC7_0, CLK_TTC7_0, "ttc7_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C0_0, CLK_I2C0_0, "i2c0_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C1_0, CLK_I2C1_0, "i2c1_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C2_0, CLK_I2C2_0, "i2c2_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C3_0, CLK_I2C3_0, "i2c3_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C4_0, CLK_I2C4_0, "i2c4_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C5_0, CLK_I2C5_0, "i2c5_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C6_0, CLK_I2C6_0, "i2c6_clk", true, 100000000),
+ CLOCK_CELL(CLK_I2C7_0, CLK_I2C7_0, "i2c7_clk", true, 100000000),
+ CLOCK_CELL(CLK_OSPI0_0, CLK_OSPI0_0, "ospi0_clk", true, 100000000),
+ CLOCK_CELL(CLK_QSPI0_0, CLK_QSPI0_0, "qpsi0_ref_clk", true, 100000000),
+ CLOCK_CELL(CLK_QSPI0_1, CLK_QSPI0_1, "qspi0_pclk", true, 100000000),
+ CLOCK_CELL(CLK_WWDT0_0, CLK_WWDT0_0, "wwdt0_clk", true, 100000000),
+ CLOCK_CELL(CLK_WWDT1_0, CLK_WWDT1_0, "wwdt1_clk", true, 100000000),
+ CLOCK_CELL(CLK_WWDT2_0, CLK_WWDT2_0, "wwdt2_clk", true, 100000000),
+ CLOCK_CELL(CLK_WWDT3_0, CLK_WWDT3_0, "wwdt3_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA0_0, CLK_ADMA0_0, "adma0_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA0_1, CLK_ADMA0_1, "adma0_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA1_0, CLK_ADMA1_0, "adma1_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA1_1, CLK_ADMA1_1, "adma1_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA2_0, CLK_ADMA2_0, "adma2_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA2_1, CLK_ADMA2_1, "adma2_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA3_0, CLK_ADMA3_0, "adma3_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA3_1, CLK_ADMA3_1, "adma3_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA4_0, CLK_ADMA4_0, "adma4_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA4_1, CLK_ADMA4_1, "adma4_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA5_0, CLK_ADMA5_0, "adma5_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA5_1, CLK_ADMA5_1, "adma5_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA6_0, CLK_ADMA6_0, "adma6_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA6_1, CLK_ADMA6_1, "adma6_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA7_0, CLK_ADMA7_0, "adma7_main_clk", true, 100000000),
+ CLOCK_CELL(CLK_ADMA7_1, CLK_ADMA7_1, "adma7_apb_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN0_0, CLK_CAN0_0, "can0_can_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN0_1, CLK_CAN0_1, "can0_axi_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN1_0, CLK_CAN1_0, "can1_can_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN1_1, CLK_CAN1_1, "can1_axi_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN2_0, CLK_CAN2_0, "can2_can_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN2_1, CLK_CAN2_1, "can2_axi_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN3_0, CLK_CAN3_0, "can3_can_clk", true, 100000000),
+ CLOCK_CELL(CLK_CAN3_1, CLK_CAN3_1, "can3_axi_clk", true, 100000000),
+ CLOCK_CELL(CLK_PS_GPIO_0, CLK_PS_GPIO_0, "ps_gpio_clk", true, 100000000),
+ CLOCK_CELL(CLK_PMC_GPIO_0, CLK_PMC_GPIO_0, "pmc_gpio_clk", true, 100000000),
+ CLOCK_CELL(CLK_SPI0_0, CLK_SPI0_0, "spi0_ref_clk", true, 100000000),
+ CLOCK_CELL(CLK_SPI0_1, CLK_SPI0_1, "spi0_pclk", true, 100000000),
+ CLOCK_CELL(CLK_SPI1_0, CLK_SPI1_0, "spi1_ref_clk", true, 100000000),
+ CLOCK_CELL(CLK_SPI1_1, CLK_SPI1_1, "spi1_pclk", true, 100000000),
+ CLOCK_CELL(CLK_I3C0_0, CLK_I3C0_0, "i3c0_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C1_0, CLK_I3C1_0, "i3c1_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C2_0, CLK_I3C2_0, "i3c2_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C3_0, CLK_I3C3_0, "i3c3_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C4_0, CLK_I3C4_0, "i3c4_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C5_0, CLK_I3C5_0, "i3c5_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C6_0, CLK_I3C6_0, "i3c6_clk", true, 100000000),
+ CLOCK_CELL(CLK_I3C7_0, CLK_I3C7_0, "i3c7_clk", true, 100000000),
+};
+
+/*
+ * struct scmi_reset - Data for the exposed reset controller
+ * @reset_id: Reset identifier in RCC reset driver
+ * @name: Reset string ID exposed to agent
+ */
+struct scmi_reset {
+ unsigned long reset_id;
+ const char *name;
+};
+
+#define RESET_CELL(_scmi_id, _id, _name) \
+ [_scmi_id] = { \
+ .reset_id = (_id), \
+ .name = (_name), \
+ }
+
+static struct scmi_reset scmi0_reset[] = {
+ RESET_CELL(RESET_GEM0_0, RESET_GEM0_0, "gem0"),
+ RESET_CELL(RESET_GEM1_0, RESET_GEM1_0, "gem1"),
+ RESET_CELL(RESET_SERIAL0_0, RESET_SERIAL0_0, "serial0"),
+ RESET_CELL(RESET_SERIAL1_0, RESET_SERIAL1_0, "serial1"),
+ RESET_CELL(RESET_UFS0_0, RESET_UFS0_0, "ufs0"),
+ RESET_CELL(RESET_I2C0_0, RESET_I2C0_0, "i2c0"),
+ RESET_CELL(RESET_I2C1_0, RESET_I2C1_0, "i2c1"),
+ RESET_CELL(RESET_I2C2_0, RESET_I2C2_0, "i2c2"),
+ RESET_CELL(RESET_I2C3_0, RESET_I2C3_0, "i2c3"),
+ RESET_CELL(RESET_I2C4_0, RESET_I2C4_0, "i2c4"),
+ RESET_CELL(RESET_I2C5_0, RESET_I2C5_0, "i2c5"),
+ RESET_CELL(RESET_I2C6_0, RESET_I2C6_0, "i2c6"),
+ RESET_CELL(RESET_I2C7_0, RESET_I2C7_0, "i2c7"),
+ RESET_CELL(RESET_I2C8_0, RESET_I2C8_0, "i2c8"),
+ RESET_CELL(RESET_OSPI0_0, RESET_OSPI0_0, "ospi"),
+ RESET_CELL(RESET_USB0_0, RESET_USB0_0, "usb0_0"),
+ RESET_CELL(RESET_USB0_1, RESET_USB0_1, "usb0_1"),
+ RESET_CELL(RESET_USB0_2, RESET_USB0_2, "usb0_2"),
+ RESET_CELL(RESET_USB1_0, RESET_USB1_0, "usb1_0"),
+ RESET_CELL(RESET_USB1_1, RESET_USB1_1, "usb1_1"),
+ RESET_CELL(RESET_USB1_2, RESET_USB1_2, "usb1_2"),
+ RESET_CELL(RESET_MMC0_0, RESET_MMC0_0, "mmc0"),
+ RESET_CELL(RESET_MMC1_0, RESET_MMC1_0, "mmc1"),
+ RESET_CELL(RESET_SPI0_0, RESET_SPI0_0, "spi0"),
+ RESET_CELL(RESET_SPI1_0, RESET_SPI1_0, "spi1"),
+ RESET_CELL(RESET_QSPI0_0, RESET_QSPI0_0, "qspi"),
+ RESET_CELL(RESET_I3C0_0, RESET_I3C0_0, "i3c0"),
+ RESET_CELL(RESET_I3C1_0, RESET_I3C1_0, "i3c1"),
+ RESET_CELL(RESET_I3C2_0, RESET_I3C2_0, "i3c2"),
+ RESET_CELL(RESET_I3C3_0, RESET_I3C3_0, "i3c3"),
+ RESET_CELL(RESET_I3C4_0, RESET_I3C4_0, "i3c4"),
+ RESET_CELL(RESET_I3C5_0, RESET_I3C5_0, "i3c5"),
+ RESET_CELL(RESET_I3C6_0, RESET_I3C6_0, "i3c6"),
+ RESET_CELL(RESET_I3C7_0, RESET_I3C7_0, "i3c7"),
+ RESET_CELL(RESET_I3C8_0, RESET_I3C8_0, "i3c8"),
+};
+
+struct scmi_resources {
+ struct scmi_clk *clock;
+ size_t clock_count;
+ struct scmi_reset *reset;
+ size_t reset_count;
+
+};
+
+static const struct scmi_resources resources[] = {
+ [0] = {
+ .clock = scmi0_clock,
+ .clock_count = ARRAY_SIZE(scmi0_clock),
+ .reset = scmi0_reset,
+ .reset_count = ARRAY_SIZE(scmi0_reset),
+ },
+};
+
+static const struct scmi_resources *find_resource(unsigned int agent_id)
+{
+ assert(agent_id < ARRAY_SIZE(resources));
+
+ return &resources[agent_id];
+}
+
+static struct scmi_clk *clk_find(unsigned int agent_id, unsigned int scmi_id)
+{
+ const struct scmi_resources *resource = find_resource(agent_id);
+ size_t n = 0U;
+ struct scmi_clk *ret = NULL;
+
+ if (resource != NULL) {
+ for (n = 0U; n < resource->clock_count; n++) {
+ if (n == scmi_id) {
+ ret = &resource->clock[n];
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+size_t plat_scmi_clock_count(unsigned int agent_id)
+{
+ const struct scmi_resources *resource = find_resource(agent_id);
+ size_t ret;
+
+ if (resource == NULL) {
+ ret = 0U;
+ } else {
+ VERBOSE("SCMI: CLK: %d clocks\n", (unsigned int)resource->clock_count);
+
+ ret = resource->clock_count;
+ }
+ return ret;
+}
+
+const char *plat_scmi_clock_get_name(unsigned int agent_id, unsigned int scmi_id)
+{
+ struct scmi_clk *clock = clk_find(agent_id, scmi_id);
+ const char *ret;
+
+ if (clock == NULL) {
+ ret = NULL;
+ } else {
+ VERBOSE("SCMI: CLK: id: %d, get_name: %s\n", scmi_id, clock->name);
+
+ ret = clock->name;
+ }
+ return ret;
+};
+
+/* Called by Linux */
+int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id,
+ unsigned long *array, size_t *nb_elts,
+ uint32_t start_idx)
+{
+ struct scmi_clk *clock = clk_find(agent_id, scmi_id);
+
+ if (clock == NULL) {
+ return SCMI_NOT_FOUND;
+ }
+
+ if (start_idx > 0) {
+ return SCMI_OUT_OF_RANGE;
+ }
+
+ if (array == NULL) {
+ *nb_elts = 1U;
+ } else if (*nb_elts == 1U) {
+ *array = clock->rate;
+ VERBOSE("SCMI: CLK: id: %d, clk_name: %s, get_rate %lu\n",
+ scmi_id, clock->name, *array);
+ } else {
+ return SCMI_GENERIC_ERROR;
+ }
+
+ return SCMI_SUCCESS;
+}
+
+unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, unsigned int scmi_id)
+{
+ struct scmi_clk *clock = clk_find(agent_id, scmi_id);
+ unsigned long ret;
+
+ if ((clock == NULL)) {
+ ret = SCMI_NOT_FOUND;
+ } else {
+ VERBOSE("SCMI: CLK: id: %d, get_rate: %lu\n", scmi_id, clock->rate);
+ ret = clock->rate;
+ }
+ return ret;
+}
+
+int32_t plat_scmi_clock_set_rate(unsigned int agent_id, unsigned int scmi_id,
+ unsigned long rate)
+{
+ struct scmi_clk *clock = clk_find(agent_id, scmi_id);
+ unsigned long ret = UL(SCMI_SUCCESS);
+
+ if ((clock == NULL)) {
+ ret = SCMI_NOT_FOUND;
+ } else {
+ VERBOSE("SCMI: CLK: id: %d, set_rate: %lu\n", scmi_id, rate);
+ clock->rate = rate;
+ }
+ return ret;
+}
+
+int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id)
+{
+ struct scmi_clk *clock = clk_find(agent_id, scmi_id);
+ int32_t ret;
+
+ if ((clock == NULL)) {
+ ret = SCMI_NOT_FOUND;
+ } else {
+ VERBOSE("SCMI: CLK: id: %d, get_state: %d\n", scmi_id, clock->enabled);
+
+ if (clock->enabled) {
+ ret = HIGH;
+ } else {
+ ret = LOW;
+ }
+ }
+ return ret;
+}
+
+int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id,
+ bool enable_not_disable)
+{
+ struct scmi_clk *clock = clk_find(agent_id, scmi_id);
+ int32_t ret;
+
+ if (clock == NULL) {
+ ret = SCMI_NOT_FOUND;
+ } else {
+ if (enable_not_disable) {
+ if (!clock->enabled) {
+ VERBOSE("SCMI: clock: %u enable\n", scmi_id);
+ clock->enabled = true;
+ }
+ } else {
+ if (clock->enabled) {
+ VERBOSE("SCMI: clock: %u disable\n", scmi_id);
+ clock->enabled = false;
+ }
+ }
+
+ VERBOSE("SCMI: CLK: id: %d, set_state: %d\n", scmi_id, clock->enabled);
+
+ ret = SCMI_SUCCESS;
+ }
+
+ return ret;
+}
+
+
+/*
+ * Platform SCMI reset domains
+ */
+static struct scmi_reset *find_reset(unsigned int agent_id,
+ unsigned int scmi_id)
+{
+ const struct scmi_resources *resource = find_resource(agent_id);
+ size_t n;
+
+ if (resource != NULL) {
+ for (n = 0U; n < resource->reset_count; n++) {
+ if (n == scmi_id) {
+ return &resource->reset[n];
+ }
+ }
+ }
+
+ return NULL;
+}
+
+const char *plat_scmi_rstd_get_name(unsigned int agent_id, unsigned int scmi_id)
+{
+ const struct scmi_reset *reset = find_reset(agent_id, scmi_id);
+
+ if (reset == NULL) {
+ return NULL;
+ }
+
+ return reset->name;
+}
+
+size_t plat_scmi_rstd_count(unsigned int agent_id)
+{
+ const struct scmi_resources *resource = find_resource(agent_id);
+
+ if (resource == NULL) {
+ return 0U;
+ }
+
+ return resource->reset_count;
+}
+
+int32_t plat_scmi_rstd_autonomous(unsigned int agent_id, unsigned int scmi_id,
+ uint32_t state)
+{
+ const struct scmi_reset *reset = find_reset(agent_id, scmi_id);
+
+ if (reset == NULL) {
+ return SCMI_NOT_FOUND;
+ }
+
+ /* Supports only reset with context loss */
+ if (state != 0U) {
+ return SCMI_NOT_SUPPORTED;
+ }
+
+ NOTICE("SCMI reset on ID %lu/%s\n",
+ reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id));
+
+ return SCMI_SUCCESS;
+}
+
+int32_t plat_scmi_rstd_set_state(unsigned int agent_id, unsigned int scmi_id,
+ bool assert_not_deassert)
+{
+ const struct scmi_reset *reset = find_reset(agent_id, scmi_id);
+
+ if (reset == NULL) {
+ return SCMI_NOT_FOUND;
+ }
+
+ if (assert_not_deassert) {
+ NOTICE("SCMI reset %lu/%s set\n",
+ reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id));
+ } else {
+ NOTICE("SCMI reset %lu/%s release\n",
+ reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id));
+ }
+
+ return SCMI_SUCCESS;
+}
+
+/* Currently only one channel is supported. Expectation is that channel 0 is used by NS SW */
+static struct scmi_msg_channel scmi_channel[] = {
+ [0] = {
+ .shm_addr = SMT_BUFFER_BASE,
+ .shm_size = SMT_BUF_SLOT_SIZE,
+ },
+};
+
+struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id)
+{
+ assert(agent_id < ARRAY_SIZE(scmi_channel));
+
+ VERBOSE("%d: SCMI asking for channel\n", agent_id);
+
+ /* Just in case that code is reused */
+ return &scmi_channel[agent_id];
+}
+
+/* Base protocol implementations */
+const char *plat_scmi_vendor_name(void)
+{
+ return SCMI_VENDOR;
+}
+
+const char *plat_scmi_sub_vendor_name(void)
+{
+ return SCMI_PRODUCT;
+}
+
+/* Currently supporting Clocks and Reset Domains */
+static const uint8_t plat_protocol_list[] = {
+ SCMI_PROTOCOL_ID_BASE,
+ SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_PROTOCOL_ID_RESET_DOMAIN,
+ /*
+ *SCMI_PROTOCOL_ID_POWER_DOMAIN,
+ *SCMI_PROTOCOL_ID_SENSOR,
+ */
+ 0U /* Null termination */
+};
+
+size_t plat_scmi_protocol_count(void)
+{
+ const size_t count = ARRAY_SIZE(plat_protocol_list) - 1U;
+
+ VERBOSE("SCMI: Protocol count: %d\n", (int32_t)count);
+
+ return count;
+}
+
+const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused)
+{
+ return plat_protocol_list;
+}
+
+void init_scmi_server(void)
+{
+ size_t i;
+ int32_t ret;
+
+ for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++)
+ scmi_smt_init_agent_channel(&scmi_channel[i]);
+
+ INFO("SCMI: Server initialized\n");
+
+ if (platform_id == QEMU) {
+ /* default setting is for QEMU */
+ } else if (platform_id == SPP) {
+ for (i = 0U; i < ARRAY_SIZE(scmi0_clock); i++) {
+
+ /* Keep i2c on 100MHz to calculate rates properly */
+ if (i >= CLK_I2C0_0 && i <= CLK_I2C7_0)
+ continue;
+ /*
+ * SPP supports multiple versions.
+ * The cpu_clock value is set to corresponding SPP
+ * version in early platform setup, resuse the same
+ * value here.
+ */
+ ret = plat_scmi_clock_set_rate(0, i, cpu_clock);
+ if (ret < 0) {
+ NOTICE("Failed to set clock rate for SPP scmi_id=%ld\n", i);
+ }
+ }
+ } else {
+ /* Making MISRA C 2012 15.7 compliant */
+ }
+}
diff --git a/plat/amd/versal2/sip_svc_setup.c b/plat/amd/versal2/sip_svc_setup.c
new file mode 100644
index 0000000..6850030
--- /dev/null
+++ b/plat/amd/versal2/sip_svc_setup.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* Top level SMC handler for SiP calls. Dispatch PM calls to PM SMC handler. */
+
+#include <errno.h>
+#include <inttypes.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <drivers/scmi-msg.h>
+#include <scmi.h>
+#include <tools_share/uuid.h>
+
+#include "ipi_mailbox_svc.h"
+#include "plat_private.h"
+#include "pm_svc_main.h"
+
+/* SMC function IDs for SiP Service queries */
+#define SIP_SVC_UID (0x8200ff01U)
+#define SIP_SVC_VERSION (0x8200ff03U)
+
+/* SiP Service Calls version numbers */
+#define SIP_SVC_VERSION_MAJOR (0U)
+#define SIP_SVC_VERSION_MINOR (1U)
+
+/* These macros are used to identify PM calls from the SMC function ID */
+#define SIP_FID_MASK GENMASK(23, 16)
+#define XLNX_FID_MASK GENMASK(23, 12)
+#define PM_FID_VALUE 0u
+#define IPI_FID_VALUE 0x1000u
+#define is_pm_fid(_fid) (((_fid) & XLNX_FID_MASK) == PM_FID_VALUE)
+#define is_ipi_fid(_fid) (((_fid) & XLNX_FID_MASK) == IPI_FID_VALUE)
+
+/* SiP Service UUID */
+DEFINE_SVC_UUID2(_sip_uuid,
+ 0x0499eb70, 0x5ed0, 0x11ee, 0xb3, 0x0a,
+ 0x87, 0xd1, 0x1d, 0x4f, 0x8a, 0x9b);
+
+/**
+ * sip_svc_setup() - Setup SiP Service
+ *
+ * Return: 0 on success, negative error code on failure.
+ *
+ */
+static int32_t sip_svc_setup(void)
+{
+ return sip_svc_setup_init();
+}
+
+/*
+ * sip_svc_smc_handler() - Top-level SiP Service SMC handler
+ *
+ * Handler for all SiP SMC calls. Handles standard SIP requests
+ * and calls PM SMC handler if the call is for a PM-API function.
+ */
+static uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ VERBOSE("SMCID: 0x%08x, x1: 0x%016" PRIx64 ", x2: 0x%016" PRIx64 ", x3: 0x%016" PRIx64 ", x4: 0x%016" PRIx64 "\n",
+ smc_fid, x1, x2, x3, x4);
+
+ if ((smc_fid & SIP_FID_MASK) != 0) {
+ WARN("SMC out of SiP assinged range: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ }
+
+ /* Let PM SMC handler deal with PM-related requests */
+ if (is_pm_fid(smc_fid)) {
+ return smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+ }
+
+ /* Let IPI SMC handler deal with IPI-related requests if platform */
+ if (is_ipi_fid(smc_fid)) {
+ return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
+ }
+
+ /* Let PM SMC handler deal with PM-related requests */
+ switch (smc_fid) {
+ case SIP_SVC_UID:
+ SMC_UUID_RET(handle, _sip_uuid);
+
+ case SIP_SVC_VERSION:
+ SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR);
+
+ case SIP_SCMI:
+ if (platform_id != EMU) {
+ scmi_smt_fastcall_smc_entry(0);
+ SMC_RET1(handle, 0);
+ }
+ WARN("SCMI is not working on EMU\n");
+ SMC_RET1(handle, SMC_UNK);
+ default:
+ WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+ }
+}
+
+/* Register PM Service Calls as runtime service */
+DECLARE_RT_SVC(
+ sip_svc,
+ OEN_SIP_START,
+ OEN_SIP_END,
+ SMC_TYPE_FAST,
+ sip_svc_setup,
+ sip_svc_smc_handler);
diff --git a/plat/amd/versal2/soc_ipi.c b/plat/amd/versal2/soc_ipi.c
new file mode 100644
index 0000000..85d1bcd
--- /dev/null
+++ b/plat/amd/versal2/soc_ipi.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * SoC IPI agent registers access management
+ */
+
+#include <lib/utils_def.h>
+#include <plat_ipi.h>
+
+/* versal2 ipi configuration table */
+static const struct ipi_config ipi_table[IPI_ID_MAX] = {
+ /* A78 IPI */
+ [IPI_ID_APU] = {
+ .ipi_bit_mask = IPI0_TRIG_BIT,
+ .ipi_reg_base = IPI0_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* PMC IPI */
+ [IPI_ID_PMC] = {
+ .ipi_bit_mask = PMC_IPI_TRIG_BIT,
+ .ipi_reg_base = IPI0_REG_BASE,
+ .secure_only = IPI_SECURE_MASK,
+ },
+
+ /* RPU0 IPI */
+ [IPI_ID_RPU0] = {
+ .ipi_bit_mask = IPI1_TRIG_BIT,
+ .ipi_reg_base = IPI1_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* RPU1 IPI */
+ [IPI_ID_RPU1] = {
+ .ipi_bit_mask = IPI2_TRIG_BIT,
+ .ipi_reg_base = IPI2_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI3 IPI */
+ [IPI_ID_3] = {
+ .ipi_bit_mask = IPI3_TRIG_BIT,
+ .ipi_reg_base = IPI3_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI4 IPI */
+ [IPI_ID_4] = {
+ .ipi_bit_mask = IPI4_TRIG_BIT,
+ .ipi_reg_base = IPI4_REG_BASE,
+ .secure_only = 0,
+ },
+
+ /* IPI5 IPI */
+ [IPI_ID_5] = {
+ .ipi_bit_mask = IPI5_TRIG_BIT,
+ .ipi_reg_base = IPI5_REG_BASE,
+ .secure_only = 0,
+ },
+};
+
+/**
+ * soc_ipi_config_table_init() - Initialize versal2 IPI configuration data.
+ */
+void soc_ipi_config_table_init(void)
+{
+ ipi_config_table_init(ipi_table, ARRAY_SIZE(ipi_table));
+}
diff --git a/plat/amd/versal2/tsp/tsp-versal2.mk b/plat/amd/versal2/tsp/tsp-versal2.mk
new file mode 100644
index 0000000..422ed17
--- /dev/null
+++ b/plat/amd/versal2/tsp/tsp-versal2.mk
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# TSP source files specific to Versal Gen 2 platform
+
+PLAT_XILINX_COMMON := plat/xilinx/common/
+
+include ${PLAT_XILINX_COMMON}/tsp/tsp.mk
diff --git a/plat/amlogic/axg/platform.mk b/plat/amlogic/axg/platform.mk
index 64b35d6..aadecab 100644
--- a/plat/amlogic/axg/platform.mk
+++ b/plat/amlogic/axg/platform.mk
@@ -85,10 +85,10 @@
distclean realclean clean: cleanimage
cleanimage:
- ${Q}${MAKE} -C ${DOIMAGEPATH} clean
+ $(q)${MAKE} -C ${DOIMAGEPATH} clean
${DOIMAGETOOL}:
- ${Q}${MAKE} -C ${DOIMAGEPATH}
+ $(q)${MAKE} -C ${DOIMAGEPATH}
${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL}
${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img
diff --git a/plat/amlogic/g12a/platform.mk b/plat/amlogic/g12a/platform.mk
index 799e106..15658d3 100644
--- a/plat/amlogic/g12a/platform.mk
+++ b/plat/amlogic/g12a/platform.mk
@@ -81,10 +81,10 @@
distclean realclean clean: cleanimage
cleanimage:
- ${Q}${MAKE} -C ${DOIMAGEPATH} clean
+ $(q)${MAKE} -C ${DOIMAGEPATH} clean
${DOIMAGETOOL}:
- ${Q}${MAKE} -C ${DOIMAGEPATH}
+ $(q)${MAKE} -C ${DOIMAGEPATH}
${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL}
${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img
diff --git a/plat/amlogic/gxl/platform.mk b/plat/amlogic/gxl/platform.mk
index 0a88482..31063a9 100644
--- a/plat/amlogic/gxl/platform.mk
+++ b/plat/amlogic/gxl/platform.mk
@@ -81,10 +81,10 @@
distclean realclean clean: cleanimage
cleanimage:
- ${Q}${MAKE} -C ${DOIMAGEPATH} clean
+ $(q)${MAKE} -C ${DOIMAGEPATH} clean
${DOIMAGETOOL}:
- ${Q}${MAKE} -C ${DOIMAGEPATH}
+ $(q)${MAKE} -C ${DOIMAGEPATH}
${BUILD_PLAT}/bl31.img: ${BUILD_PLAT}/bl31.bin ${DOIMAGETOOL}
${DOIMAGETOOL} ${BUILD_PLAT}/bl31.bin ${BUILD_PLAT}/bl31.img
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 520a73a..82401db 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -41,8 +41,12 @@
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
ENABLE_FEAT_HCX := 2
+ENABLE_FEAT_MTE2 := 2
+ENABLE_FEAT_TCR2 := 2
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_TRF_FOR_NS := 2
+ENABLE_SME_FOR_NS := 2
+ENABLE_SME2_FOR_NS := 2
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
@@ -128,13 +132,15 @@
$(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,bl31))
ifeq ($($(ARCH)-ld-id),gnu-gcc)
- PLAT_LDFLAGS += -Wl,--strip-debug
+ AXF_LDFLAGS += -Wl,--build-id=none -mno-fix-cortex-a53-843419
else
- PLAT_LDFLAGS += --strip-debug
+ AXF_LDFLAGS += --build-id=none
endif
+AXF_LDFLAGS += -nostdlib -no-pie
+
bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/kernel_trampoline.o ${BUILD_PLAT}/build_axf.ld
- $(ECHO) " LD $@"
- $(Q)$($(ARCH)-ld) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} $(TF_LDFLAGS) $(PLAT_LDFLAGS) -s -n -o ${BUILD_PLAT}/bl31.axf
+ $(s)echo " LD $@"
+ $(q)$($(ARCH)-ld) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} ${AXF_LDFLAGS} -s -n -o ${BUILD_PLAT}/bl31.axf
all: bl31.axf
diff --git a/plat/arm/board/corstone1000/common/corstone1000_helpers.S b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
index cbe27c3..a4ca9fe 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_helpers.S
+++ b/plat/arm/board/corstone1000/common/corstone1000_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024 Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,8 +21,34 @@
* --------------------------------------------------------------------
*/
func plat_secondary_cold_boot_setup
+#if defined(CORSTONE1000_FVP_MULTICORE)
+
+ /* Calculate the address of our hold entry */
+ bl plat_my_core_pos
+ lsl x0, x0, #CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT
+ mov_imm x2, CORSTONE1000_SECONDARY_CORE_HOLD_BASE
+
+ /* Set the wait state for the secondary core */
+ mov_imm x3, CORSTONE1000_SECONDARY_CORE_STATE_WAIT
+ str x3, [x2, x0]
+ dmb ish
+
+ /* Poll until the primary core signals to go */
+poll_mailbox:
+ ldr x1, [x2, x0]
+ cmp x1, #CORSTONE1000_SECONDARY_CORE_STATE_WAIT
+ beq 1f
+ mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
+ ldr x1, [x0]
+ br x1
+1:
+ wfe
+ b poll_mailbox
+#else
cb_panic:
b cb_panic
+#endif
+
endfunc plat_secondary_cold_boot_setup
/* ---------------------------------------------------------------------
diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c
index 4b0a791..ee07605 100644
--- a/plat/arm/board/corstone1000/common/corstone1000_pm.c
+++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,9 +25,52 @@
}
}
+#if defined(CORSTONE1000_FVP_MULTICORE)
+int corstone1000_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /*
+ * Check if the non secure entrypoint lies within the non
+ * secure DRAM.
+ */
+ if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
+ return PSCI_E_SUCCESS;
+ }
+ return PSCI_E_INVALID_ADDRESS;
+}
+
+int corstone1000_pwr_domain_on(u_register_t mpidr)
+{
+ int core_index = plat_core_pos_by_mpidr(mpidr);
+ uint64_t *secondary_core_hold_base = (uint64_t *)CORSTONE1000_SECONDARY_CORE_HOLD_BASE;
+
+ /* Validate the core index */
+ if (core_index < 0 || core_index > PLATFORM_CORE_COUNT) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+ secondary_core_hold_base[core_index] = CORSTONE1000_SECONDARY_CORE_STATE_GO;
+ dsbish();
+ sev();
+
+ return PSCI_E_SUCCESS;
+}
+
+void corstone1000_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ (void)target_state;
+ plat_arm_gic_init();
+}
+#endif
+
plat_psci_ops_t plat_arm_psci_pm_ops = {
+#if defined(CORSTONE1000_FVP_MULTICORE)
+ .pwr_domain_on = corstone1000_pwr_domain_on,
+ .pwr_domain_on_finish = corstone1000_pwr_domain_on_finish,
+ .validate_ns_entrypoint = corstone1000_validate_ns_entrypoint,
+ .system_reset = corstone1000_system_reset,
+#else
+ .validate_ns_entrypoint = NULL,
.system_reset = corstone1000_system_reset,
- .validate_ns_entrypoint = NULL
+#endif
};
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h
index 6953b89..e3f3268 100644
--- a/plat/arm/board/corstone1000/common/include/platform_def.h
+++ b/plat/arm/board/corstone1000/common/include/platform_def.h
@@ -262,6 +262,19 @@
#define ARM_LOCAL_STATE_OFF U(2)
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
+
+#if defined(CORSTONE1000_FVP_MULTICORE)
+/* The secondary core entrypoint address points to bl31_warm_entrypoint
+ * and the address size is 8 bytes */
+#define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8)
+
+#define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \
+ CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE)
+#define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0)
+#define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1)
+#define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3)
+#endif
+
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk
index fd08803..9d44a14 100644
--- a/plat/arm/board/corstone1000/platform.mk
+++ b/plat/arm/board/corstone1000/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2021-2024 Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -36,6 +36,13 @@
$(eval $(call add_define,CORSTONE1000_WITH_BL32))
endif
+ENABLE_MULTICORE := 0
+ifneq ($(filter ${TARGET_PLATFORM}, fvp),)
+ifeq (${ENABLE_MULTICORE},1)
+$(eval $(call add_define,CORSTONE1000_FVP_MULTICORE))
+endif
+endif
+
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S
index 8efc238..46fb44a 100644
--- a/plat/arm/board/fvp/aarch64/fvp_helpers.S
+++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S
@@ -6,9 +6,10 @@
#include <arch.h>
#include <asm_macros.S>
+#include <drivers/arm/fvp/fvp_cpu_pwr.h>
+#include <drivers/arm/fvp/fvp_pwrc.h>
#include <drivers/arm/gicv2.h>
#include <drivers/arm/gicv3.h>
-#include <drivers/arm/fvp/fvp_pwrc.h>
#include <platform_def.h>
.globl plat_secondary_cold_boot_setup
@@ -29,6 +30,21 @@
*/
func plat_secondary_cold_boot_setup
#ifndef EL3_PAYLOAD_BASE
+
+ /* --------------------------------------------
+ * Check if core supports powering down, if it
+ * supports power down then set core power down
+ * bit before requesting for the cores to be
+ * powered off from base power controller.
+ * ---------------------------------------------
+ */
+ bl check_cpupwrctrl_el1_is_available
+ cbz x0, base_power_off
+
+ mrs x1, CPUPWRCTLR_EL1
+ orr x1, x1, #CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CPUPWRCTLR_EL1, x1
+
/* ---------------------------------------------
* Power down this cpu.
* TODO: Do we need to worry about powering the
@@ -37,6 +53,7 @@
* loader zeroes out the zi section.
* ---------------------------------------------
*/
+base_power_off:
mrs x0, mpidr_el1
mov_imm x1, PWRC_BASE
str w0, [x1, #PPOFFR_OFF]
diff --git a/plat/arm/board/fvp/fvp_cpu_pwr.c b/plat/arm/board/fvp/fvp_cpu_pwr.c
new file mode 100644
index 0000000..f2771c2
--- /dev/null
+++ b/plat/arm/board/fvp/fvp_cpu_pwr.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if __aarch64__
+
+#include <aem_generic.h>
+#include <arch_helpers.h>
+#include <cortex_a35.h>
+#include <cortex_a53.h>
+#include <cortex_a57.h>
+#include <cortex_a72.h>
+#include <cortex_a73.h>
+#include <cortex_a78_ae.h>
+#include <drivers/arm/fvp/fvp_cpu_pwr.h>
+#include <lib/utils_def.h>
+#include <neoverse_e1.h>
+
+bool check_cpupwrctrl_el1_is_available(void)
+{
+ /* Poupulate list of CPU midr that doesn't support CPUPWRCTL_EL1 */
+ const unsigned int midr_no_cpupwrctl[] = {
+ BASE_AEM_MIDR,
+ CORTEX_A35_MIDR,
+ CORTEX_A53_MIDR,
+ CORTEX_A57_MIDR,
+ CORTEX_A72_MIDR,
+ CORTEX_A73_MIDR,
+ CORTEX_A78_AE_MIDR,
+ NEOVERSE_E1_MIDR
+ };
+ unsigned int midr = (unsigned int)read_midr();
+
+ for (unsigned int i = 0U; i < ARRAY_SIZE(midr_no_cpupwrctl); i++) {
+ if (midr_no_cpupwrctl[i] == midr) {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+#endif /* __arch64__ */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 033eb7c..af2b78d 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -222,6 +222,7 @@
lib/semihosting/${ARCH}/semihosting_call.S \
plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
plat/arm/board/fvp/fvp_bl1_setup.c \
+ plat/arm/board/fvp/fvp_cpu_pwr.c \
plat/arm/board/fvp/fvp_err.c \
plat/arm/board/fvp/fvp_io_storage.c \
plat/arm/board/fvp/fvp_topology.c \
@@ -252,7 +253,8 @@
endif
ifeq (${ENABLE_RME},1)
-BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S
+BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \
+ plat/arm/board/fvp/fvp_cpu_pwr.c
BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \
plat/arm/board/fvp/fvp_realm_attest_key.c
@@ -264,6 +266,7 @@
ifeq (${RESET_TO_BL2},1)
BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \
+ plat/arm/board/fvp/fvp_cpu_pwr.c \
plat/arm/board/fvp/fvp_bl2_el3_setup.c \
${FVP_CPU_LIBS} \
${FVP_INTERCONNECT_SOURCES}
@@ -290,6 +293,7 @@
plat/arm/board/fvp/fvp_pm.c \
plat/arm/board/fvp/fvp_topology.c \
plat/arm/board/fvp/aarch64/fvp_helpers.S \
+ plat/arm/board/fvp/fvp_cpu_pwr.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
${FVP_CPU_LIBS} \
${FVP_GIC_SOURCES} \
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index a00bf26..8eca0c5 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -134,7 +134,7 @@
endif
bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin romlib.bin
- @echo "Building combined BL1 and ROMLIB binary for Juno $@"
+ $(s)echo "Building combined BL1 and ROMLIB binary for Juno $@"
./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT)
# Errata workarounds for Cortex-A53:
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index cd5abd0..28b98c2 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -10,8 +10,6 @@
TC_DPU_USE_SCMI_CLK := 1
# SCMI power domain control enable
TC_SCMI_PD_CTRL_EN := 1
-# IOMMU: Enable the use of system or individual MMUs
-TC_IOMMU_EN := 1
# System setup
CSS_USE_SCMI_SDS_DRIVER := 1
@@ -76,7 +74,6 @@
TC_RESOLUTION_$(call uppercase,${TC_RESOLUTION}) \
TC_DPU_USE_SCMI_CLK \
TC_SCMI_PD_CTRL_EN \
- TC_IOMMU_EN \
))
CSS_LOAD_SCP_IMAGES := 1
diff --git a/plat/arm/board/tc/tc_bl1_dpe.c b/plat/arm/board/tc/tc_bl1_dpe.c
index 432a163..a073dc3 100644
--- a/plat/arm/board/tc/tc_bl1_dpe.c
+++ b/plat/arm/board/tc/tc_bl1_dpe.c
@@ -45,7 +45,7 @@
.signer_id_size = SIGNER_ID_MIN_SIZE,
.sw_type = MBOOT_BL2_IMAGE_STRING,
.allow_new_context_to_derive = true,
- .retain_parent_context = false,
+ .retain_parent_context = true, /* To handle restart */
.create_certificate = false,
.pk_oid = ZERO_OID },
{
@@ -58,10 +58,15 @@
/* Context handle is meant to be used by BL2. Sharing it via TB_FW_CONFIG */
static int new_ctx_handle;
+/* Save a valid parent context handle to be able to send commands to DPE service
+ * in case of an AP cold restart.
+ */
+static int new_parent_ctx_handle;
-void plat_dpe_share_context_handle(int *ctx_handle)
+void plat_dpe_share_context_handle(int *ctx_handle, int *parent_ctx_handle)
{
new_ctx_handle = *ctx_handle;
+ new_parent_ctx_handle = *parent_ctx_handle;
}
void plat_dpe_get_context_handle(int *ctx_handle)
@@ -135,4 +140,16 @@
*/
plat_panic_handler();
}
+
+ VERBOSE("Save parent context handle: 0x%x\n", new_parent_ctx_handle);
+ rc = sds_struct_write(SDS_RSE_AP_REGION_ID,
+ TC2_SDS_DPE_CTX_HANDLE_STRUCT_ID,
+ 0,
+ &new_parent_ctx_handle,
+ sizeof(new_parent_ctx_handle),
+ SDS_ACCESS_MODE_NON_CACHED);
+ if (rc != SDS_OK) {
+ ERROR("Unable to save DPE parent context handle to SDS area\n");
+ plat_panic_handler();
+ }
}
diff --git a/plat/arm/board/tc/tc_bl2_dpe.c b/plat/arm/board/tc/tc_bl2_dpe.c
index 50cdbf8..fb70fef 100644
--- a/plat/arm/board/tc/tc_bl2_dpe.c
+++ b/plat/arm/board/tc/tc_bl2_dpe.c
@@ -186,9 +186,12 @@
/* Context handle is meant to be used by BL33. Sharing it via NT_FW_CONFIG */
static int new_ctx_handle;
-void plat_dpe_share_context_handle(int *ctx_handle)
+void plat_dpe_share_context_handle(int *ctx_handle, int *parent_ctx_handle)
{
new_ctx_handle = *ctx_handle;
+
+ /* Irrelevant in BL2 because cold restart resumes CPU in BL1 */
+ (void)parent_ctx_handle;
}
void plat_dpe_get_context_handle(int *ctx_handle)
diff --git a/plat/arm/board/tc/tc_bl2_measured_boot.c b/plat/arm/board/tc/tc_bl2_measured_boot.c
index add871c..3957c90 100644
--- a/plat/arm/board/tc/tc_bl2_measured_boot.c
+++ b/plat/arm/board/tc/tc_bl2_measured_boot.c
@@ -40,6 +40,13 @@
.pk_oid = SOC_FW_CONFIG_KEY_OID,
.lock_measurement = true },
{
+ .id = SCP_BL2_IMAGE_ID,
+ .slot = U(12),
+ .signer_id_size = SIGNER_ID_MIN_SIZE,
+ .sw_type = MBOOT_SCP_BL2_IMAGE_STRING,
+ .pk_oid = SCP_BL2_IMAGE_KEY_OID,
+ .lock_measurement = true },
+ {
.id = RSE_MBOOT_INVALID_ID }
};
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 7377a01..f5919ab 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -26,7 +26,7 @@
else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
else
- $(error "Unsupported ARM_TSP_RAM_LOCATION value")
+ $(error Unsupported ARM_TSP_RAM_LOCATION value)
endif
# Process flags
@@ -83,7 +83,7 @@
# memory. This means we must not run BL31 from TZC-protected DRAM.
ifeq (${ARM_BL31_IN_DRAM},1)
ifeq (${ENABLE_RME},1)
- $(error "BL31 must not run from DRAM on RME-systems. Please set ARM_BL31_IN_DRAM to 0")
+ $(error BL31 must not run from DRAM on RME-systems. Please set ARM_BL31_IN_DRAM to 0)
endif
endif
@@ -105,16 +105,15 @@
ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
ifneq (${ARCH},aarch64)
ifneq (${RESET_TO_SP_MIN},1)
- $(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.")
+ $(error ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.)
endif
endif
ifndef PRELOADED_BL33_BASE
- $(error "PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+ $(error PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.)
endif
ifeq (${RESET_TO_BL31},1)
ifndef ARM_PRELOADED_DTB_BASE
- $(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is
- used with RESET_TO_BL31.")
+ $(error ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used with RESET_TO_BL31.)
endif
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
endif
@@ -456,6 +455,6 @@
ifeq (${RECLAIM_INIT_CODE}, 1)
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
- $(error "To reclaim init code xlat tables v2 must be used")
+ $(error To reclaim init code xlat tables v2 must be used)
endif
endif
diff --git a/plat/aspeed/ast2700/include/platform_def.h b/plat/aspeed/ast2700/include/platform_def.h
index 8be26c3..e668115 100644
--- a/plat/aspeed/ast2700/include/platform_def.h
+++ b/plat/aspeed/ast2700/include/platform_def.h
@@ -21,9 +21,6 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_CORE_COUNT_PER_CLUSTER)
-/* arch timer */
-#define PLAT_SYSCNT_CLKIN_HZ U(1600000000)
-
/* power domain */
#define PLAT_MAX_PWR_LVL U(1)
#define PLAT_NUM_PWR_DOMAINS U(5)
@@ -55,4 +52,12 @@
#define CONSOLE_UART_CLKIN_HZ U(1846153)
#define CONSOLE_UART_BAUDRATE U(115200)
+/* CLK information */
+#define CLKIN_25M UL(25000000)
+
+#define PLAT_CLK_GATE_NUM U(29)
+#define PLAT_CLK_HPLL (PLAT_CLK_GATE_NUM + 5)
+#define PLAT_CLK_DPLL (PLAT_CLK_GATE_NUM + 6)
+#define PLAT_CLK_MPLL (PLAT_CLK_GATE_NUM + 7)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/aspeed/ast2700/include/platform_reg.h b/plat/aspeed/ast2700/include/platform_reg.h
index 7f26865..3c164a4 100644
--- a/plat/aspeed/ast2700/include/platform_reg.h
+++ b/plat/aspeed/ast2700/include/platform_reg.h
@@ -19,6 +19,10 @@
/* CPU-die SCU */
#define SCU_CPU_BASE U(0x12c02000)
+#define SCU_CPU_HW_STRAP1 (SCU_CPU_BASE + 0x010)
+#define SCU_CPU_HPLL (SCU_CPU_BASE + 0x300)
+#define SCU_CPU_DPLL (SCU_CPU_BASE + 0x308)
+#define SCU_CPU_MPLL (SCU_CPU_BASE + 0x310)
#define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780)
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
diff --git a/plat/aspeed/ast2700/plat_bl31_setup.c b/plat/aspeed/ast2700/plat_bl31_setup.c
index 92a48ff..9fec3e8 100644
--- a/plat/aspeed/ast2700/plat_bl31_setup.c
+++ b/plat/aspeed/ast2700/plat_bl31_setup.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <errno.h>
#include <arch.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
@@ -112,3 +113,90 @@
return ep_info;
}
+
+/*
+ * Clock divider/multiplier configuration struct.
+ * For H-PLL and M-PLL the formula is
+ * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1)
+ * M - Numerator
+ * N - Denumerator
+ * P - Post Divider
+ * They have the same layout in their control register.
+ *
+ */
+union plat_pll_reg {
+ uint32_t w;
+ struct {
+ uint16_t m : 13; /* bit[12:0] */
+ uint8_t n : 6; /* bit[18:13] */
+ uint8_t p : 4; /* bit[22:19] */
+ uint8_t off : 1; /* bit[23] */
+ uint8_t bypass : 1; /* bit[24] */
+ uint8_t reset : 1; /* bit[25] */
+ uint8_t reserved : 6; /* bit[31:26] */
+ } b;
+};
+
+static uint32_t plat_get_pll_rate(int pll_idx)
+{
+ union plat_pll_reg pll_reg;
+ uint32_t mul = 1, div = 1;
+ uint32_t rate = 0;
+
+ switch (pll_idx) {
+ case PLAT_CLK_HPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_HPLL);
+ break;
+ case PLAT_CLK_DPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_DPLL);
+ break;
+ case PLAT_CLK_MPLL:
+ pll_reg.w = mmio_read_32(SCU_CPU_MPLL);
+ break;
+ default:
+ ERROR("%s: invalid PSP clock source (%d)\n", __func__, pll_idx);
+ return -EINVAL;
+ }
+
+ if (pll_idx == PLAT_CLK_HPLL && ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) != 0U)) {
+ switch ((mmio_read_32(SCU_CPU_HW_STRAP1) & GENMASK(3, 2)) >> 2) {
+ case 1U:
+ rate = 1900000000;
+ break;
+ case 2U:
+ rate = 1800000000;
+ break;
+ case 3U:
+ rate = 1700000000;
+ break;
+ default:
+ rate = 2000000000;
+ break;
+ }
+ } else {
+ if (pll_reg.b.bypass != 0U) {
+ if (pll_idx == PLAT_CLK_MPLL) {
+ /* F = 25Mhz * [M / (n + 1)] / (p + 1) */
+ mul = (pll_reg.b.m) / ((pll_reg.b.n + 1));
+ div = (pll_reg.b.p + 1);
+ } else {
+ /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */
+ mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2);
+ div = (pll_reg.b.p + 1);
+ }
+ }
+
+ rate = ((CLKIN_25M * mul) / div);
+ }
+
+ return rate;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ if (mmio_read_32(SCU_CPU_HW_STRAP1) & BIT(4)) {
+ return plat_get_pll_rate(PLAT_CLK_HPLL);
+ } else {
+ return plat_get_pll_rate(PLAT_CLK_MPLL);
+ }
+}
diff --git a/plat/aspeed/ast2700/plat_helpers.S b/plat/aspeed/ast2700/plat_helpers.S
index c6d987e..e4a283c 100644
--- a/plat/aspeed/ast2700/plat_helpers.S
+++ b/plat/aspeed/ast2700/plat_helpers.S
@@ -59,12 +59,6 @@
br x0
endfunc plat_secondary_cold_boot_setup
-/* unsigned int plat_get_syscnt_freq2(void); */
-func plat_get_syscnt_freq2
- mov_imm w0, PLAT_SYSCNT_CLKIN_HZ
- ret
-endfunc plat_get_syscnt_freq2
-
/* int plat_crash_console_init(void); */
func plat_crash_console_init
mov_imm x0, CONSOLE_UART_BASE
diff --git a/plat/common/aarch32/plat_common.c b/plat/common/aarch32/plat_common.c
index 2c1a8fa..8979171 100644
--- a/plat/common/aarch32/plat_common.c
+++ b/plat/common/aarch32/plat_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,14 @@
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <plat/common/platform.h>
+/* Pointer and function to register platform function to load alernate images */
+const struct plat_try_images_ops *plat_try_img_ops;
+
+void plat_setup_try_img_ops(const struct plat_try_images_ops *plat_try_ops)
+{
+ plat_try_img_ops = plat_try_ops;
+}
+
/*
* The following platform setup functions are weakly defined. They
* provide typical implementations that may be re-used by multiple
@@ -14,7 +22,6 @@
*/
#pragma weak bl32_plat_enable_mmu
-
void bl32_plat_enable_mmu(uint32_t flags)
{
enable_mmu_svc_mon(flags);
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index 54f2a03..7a228b9 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -17,6 +17,14 @@
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include <plat/common/platform.h>
+/* Pointer and function to register platform function to load alernate images */
+const struct plat_try_images_ops *plat_try_img_ops;
+
+void plat_setup_try_img_ops(const struct plat_try_images_ops *plat_try_ops)
+{
+ plat_try_img_ops = plat_try_ops;
+}
+
/*
* The following platform setup functions are weakly defined. They
* provide typical implementations that may be re-used by multiple
diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c
index 89b77ba..a603f2b 100644
--- a/plat/common/plat_bl_common.c
+++ b/plat/common/plat_bl_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,7 +24,6 @@
#pragma weak bl2_plat_preload_setup
#pragma weak bl2_plat_handle_pre_image_load
#pragma weak bl2_plat_handle_post_image_load
-#pragma weak plat_try_next_boot_source
#pragma weak plat_get_enc_key_info
#pragma weak plat_is_smccc_feature_available
#pragma weak plat_get_soc_version
@@ -69,11 +68,6 @@
return 0;
}
-int plat_try_next_boot_source(void)
-{
- return 0;
-}
-
/*
* Weak implementation to provide dummy decryption key only for test purposes,
* platforms must override this API for any real world firmware encryption
diff --git a/plat/hisilicon/hikey/platform.mk b/plat/hisilicon/hikey/platform.mk
index 807a915..63eca37 100644
--- a/plat/hisilicon/hikey/platform.mk
+++ b/plat/hisilicon/hikey/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -153,12 +153,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/hisilicon/hikey960/platform.mk b/plat/hisilicon/hikey960/platform.mk
index fd11a4d..c2c3122 100644
--- a/plat/hisilicon/hikey960/platform.mk
+++ b/plat/hisilicon/hikey960/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -146,12 +146,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/imx/imx7/common/imx7.mk b/plat/imx/imx7/common/imx7.mk
index 156c55d..950d8fd 100644
--- a/plat/imx/imx7/common/imx7.mk
+++ b/plat/imx/imx7/common/imx7.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -78,14 +78,14 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- @if [ ! -f $(ROT_KEY) ]; then \
+ $(s)echo " OPENSSL $@"
+ $(q)if [ ! -f $(ROT_KEY) ]; then \
${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 3a87e44..40554c3 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -134,14 +134,14 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- @if [ ! -f $(ROT_KEY) ]; then \
+ $(s)echo " OPENSSL $@"
+ $(q)if [ ! -f $(ROT_KEY) ]; then \
${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 42dc781..5f4ddee 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -131,14 +131,14 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- @if [ ! -f $(ROT_KEY) ]; then \
+ $(s)echo " OPENSSL $@"
+ $(q)if [ ! -f $(ROT_KEY) ]; then \
${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index b9c28de..18f5430 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -150,90 +150,90 @@
$(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
$(if $(wildcard $(CRYPTOPP_INCDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_INCDIR' was set to '$(CRYPTOPP_INCDIR)', but '$(CRYPTOPP_INCDIR)' does not exist"))
ifdef CRYPTOPP_PATH
- $(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
+ $(q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
endif
- $(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
+ $(q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
$(WTMI_MULTI_IMG): FORCE
- $(Q)$(MAKE) --no-print-directory -C $(WTP) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
+ $(q)$(MAKE) --no-print-directory -C $(WTP) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
$(BUILD_PLAT)/wtmi.bin: $(WTMI_MULTI_IMG)
- $(Q)cp -a $(WTMI_MULTI_IMG) $(BUILD_PLAT)/wtmi.bin
+ $(q)cp -a $(WTMI_MULTI_IMG) $(BUILD_PLAT)/wtmi.bin
$(TIMDDRTOOL): FORCE
# Do not remove! Following checks are required to ensure correct TF-A builds, removing these checks leads to broken TF-A builds
$(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for ddr tool requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
$(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
- $(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
+ $(q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL)
- @$(ECHO_BLANK_LINE)
- @echo "Building uart images"
- $(Q)mkdir -p $(BUILD_PLAT)/$(BUILD_UART)
- $(Q)cp -a $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/$(BUILD_UART)/wtmi.bin
- $(Q)cp -a $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/$(BUILD_UART)/$(BOOT_IMAGE)
- $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TIMBUILD) $(TIMBLDUARTARGS)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_UART_CFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_UART_CFG)
+ $(s)echo
+ $(s)echo "Building uart images"
+ $(q)mkdir -p $(BUILD_PLAT)/$(BUILD_UART)
+ $(q)cp -a $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/$(BUILD_UART)/wtmi.bin
+ $(q)cp -a $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/$(BUILD_UART)/$(BOOT_IMAGE)
+ $(q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TIMBUILD) $(TIMBLDUARTARGS)
+ $(q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_UART_CFG)
+ $(q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_UART_CFG)
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_UART_CFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_UART_CFG)
+ $(q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_UART_CFG)
+ $(q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_UART_CFG)
endif
- $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIM_UART_CFG) -v -D
+ $(q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIM_UART_CFG) -v -D
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIMN_UART_CFG)
+ $(q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIMN_UART_CFG)
endif
- $(Q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(UART_IMAGES)
- @$(ECHO_BLANK_LINE)
- @echo "Built $@ successfully"
- @$(ECHO_BLANK_LINE)
+ $(q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(UART_IMAGES)
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
$(BUILD_PLAT)/$(FLASH_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL) $(TIM2IMG)
- @$(ECHO_BLANK_LINE)
- @echo "Building flash image"
- $(Q)cd $(BUILD_PLAT) && $(TIMBUILD) $(TIMBLDARGS)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_CFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_CFG)
+ $(s)echo
+ $(s)echo "Building flash image"
+ $(q)cd $(BUILD_PLAT) && $(TIMBUILD) $(TIMBLDARGS)
+ $(q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_CFG)
+ $(q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_CFG)
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_CFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_CFG)
- @$(ECHO_BLANK_LINE)
- @echo "=======================================================";
- @echo " Secure boot. Encrypting wtmi and boot-image";
- @echo "=======================================================";
- @$(ECHO_BLANK_LINE)
- $(Q)cp $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/wtmi-align.bin
- $(Q)truncate -s %16 $(BUILD_PLAT)/wtmi-align.bin
- $(Q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \
+ $(q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_CFG)
+ $(q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_CFG)
+ $(s)echo
+ $(s)echo "=======================================================";
+ $(s)echo " Secure boot. Encrypting wtmi and boot-image";
+ $(s)echo "=======================================================";
+ $(s)echo
+ $(q)cp $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/wtmi-align.bin
+ $(q)truncate -s %16 $(BUILD_PLAT)/wtmi-align.bin
+ $(q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/wtmi-align.bin \
-out $(BUILD_PLAT)/$(WTMI_ENC_IMG) \
-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-iv `cat $(IMAGESPATH)/iv.txt` -p
- $(Q)truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE);
- $(Q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \
+ $(q)truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE);
+ $(q)${OPENSSL_BIN_PATH}/openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \
-out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \
-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-iv `cat $(IMAGESPATH)/iv.txt` -p
endif
- $(Q)cd $(BUILD_PLAT) && $(TBB) -r $(TIM_CFG) -v -D
+ $(q)cd $(BUILD_PLAT) && $(TBB) -r $(TIM_CFG) -v -D
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)cd $(BUILD_PLAT) && $(TBB) -r $(TIMN_CFG)
- $(Q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMN_CFG)
- $(Q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMN_CFG)
+ $(q)cd $(BUILD_PLAT) && $(TBB) -r $(TIMN_CFG)
+ $(q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMN_CFG)
+ $(q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMN_CFG)
endif
- $(Q)cd $(BUILD_PLAT) && $(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
- @$(ECHO_BLANK_LINE)
- @echo "Built $@ successfully"
- @$(ECHO_BLANK_LINE)
+ $(q)cd $(BUILD_PLAT) && $(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
clean realclean distclean: mrvl_clean
.PHONY: mrvl_clean
mrvl_clean:
- -$(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) clean
- -$(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
+ -$(q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) clean
+ -$(q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
ifdef CRYPTOPP_PATH
- -$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile clean
+ -$(q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile clean
endif
else # WTP
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index 4d8a87f..bdad8b5 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -176,17 +176,17 @@
.PHONY: mrvl_clean
mrvl_clean:
- @echo " Doimage CLEAN"
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
+ $(s)echo " Doimage CLEAN"
+ $(q)${MAKE} PLAT=${PLAT} --no-print-directory -C ${DOIMAGEPATH} clean
${DOIMAGETOOL}: FORCE
- @$(DOIMAGE_LIBS_CHECK)
- ${Q}${MAKE} --no-print-directory -C ${DOIMAGEPATH}
+ $(q)$(DOIMAGE_LIBS_CHECK)
+ $(q)${MAKE} --no-print-directory -C ${DOIMAGEPATH}
${BUILD_PLAT}/${FLASH_IMAGE}: ${ROM_BIN_EXT} ${BUILD_PLAT}/${BOOT_IMAGE} ${DOIMAGETOOL}
- @${ECHO_BLANK_LINE}
- @echo "Building flash image"
- ${Q}${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo
+ $(s)echo "Building flash image"
+ $(q)${DOIMAGETOOL} ${DOIMAGE_FLAGS} ${BUILD_PLAT}/${BOOT_IMAGE} ${BUILD_PLAT}/${FLASH_IMAGE}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
diff --git a/plat/marvell/armada/a8k/common/ble/ble.mk b/plat/marvell/armada/a8k/common/ble/ble.mk
index 752ab41..5ab6123 100644
--- a/plat/marvell/armada/a8k/common/ble/ble.mk
+++ b/plat/marvell/armada/a8k/common/ble/ble.mk
@@ -32,4 +32,4 @@
$(if $(value MV_DDR_PATH),,$(error "Platform '$(PLAT)' for BLE requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
$(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
- @+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(MV_DDR_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
+ $(q)+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(MV_DDR_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index f0e6edf..2561232 100644
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -84,13 +84,13 @@
$(BUILD_PLAT)/$(BOOT_IMAGE): $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(FIP_NAME)
$(if $(shell find $(BUILD_PLAT)/bl1.bin -type f -size +128k),$(error "Image '$(BUILD_PLAT)/bl1.bin' is bigger than 128kB"))
- @cp $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
- @truncate -s %128K $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
- @cat $(BUILD_PLAT)/$(FIP_NAME) >> $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
- @truncate -s %4 $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
- @$(ECHO_BLANK_LINE)
- @echo "Built $@ successfully"
- @$(ECHO_BLANK_LINE)
+ $(q)cp $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ $(q)truncate -s %128K $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ $(q)cat $(BUILD_PLAT)/$(FIP_NAME) >> $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ $(q)truncate -s %4 $(BUILD_PLAT)/$(BOOT_IMAGE) || { rm -f $(BUILD_PLAT)/$(BOOT_IMAGE); false; }
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
.PHONY: mrvl_bootimage
mrvl_bootimage: $(BUILD_PLAT)/$(BOOT_IMAGE)
diff --git a/plat/mediatek/build_helpers/mtk_build_helpers.mk b/plat/mediatek/build_helpers/mtk_build_helpers.mk
index ac2cbad..87a7db4 100644
--- a/plat/mediatek/build_helpers/mtk_build_helpers.mk
+++ b/plat/mediatek/build_helpers/mtk_build_helpers.mk
@@ -27,12 +27,10 @@
# Determine option variable is defined or not then define it
define add_defined_option
ifdef $(1)
-ifeq ($(findstring $(value $(1)), $(uppercase_table)),)
-DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
-else
ifeq ($(strip $(value $(1))),y)
DEFINES += -D$(1)$(if $(value $(1)),=1,)
-endif
+else
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
endif
endif
endef
diff --git a/plat/mediatek/drivers/gic600/mt_gic_v3.c b/plat/mediatek/drivers/gic600/mt_gic_v3.c
index 85f9e37..2f9765c 100644
--- a/plat/mediatek/drivers/gic600/mt_gic_v3.c
+++ b/plat/mediatek/drivers/gic600/mt_gic_v3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,6 +27,10 @@
/* we save and restore the GICv3 context on system suspend */
gicv3_dist_ctx_t dist_ctx;
+static const interrupt_prop_t mtk_interrupt_props[] = {
+ PLAT_MTK_G1S_IRQ_PROPS(INTR_GROUP1S)
+};
+
static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
{
return plat_core_pos_by_mpidr(mpidr);
@@ -35,6 +39,8 @@
gicv3_driver_data_t mt_gicv3_data = {
.gicd_base = MT_GIC_BASE,
.gicr_base = MT_GIC_RDIST_BASE,
+ .interrupt_props = mtk_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(mtk_interrupt_props),
.rdistif_num = PLATFORM_CORE_COUNT,
.rdistif_base_addrs = rdistif_base_addrs,
.mpidr_to_core_pos = mt_mpidr_to_core_pos,
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index 850ce2f..98b88bd 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -83,6 +83,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define PLAT_MTK_G1S_IRQ_PROPS(grp)
+
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM (11)
#define CIRQ_IRQ_NUM (326)
diff --git a/plat/mediatek/mt8188/include/platform_def.h b/plat/mediatek/mt8188/include/platform_def.h
index 71a4e97..8e0f5f9 100644
--- a/plat/mediatek/mt8188/include/platform_def.h
+++ b/plat/mediatek/mt8188/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -96,6 +96,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE (MT_GIC_BASE)
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
/*******************************************************************************
* CIRQ related constants
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index ec377b5..1b25e00 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,6 +82,8 @@
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define PLAT_MTK_G1S_IRQ_PROPS(grp)
+
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 14
#define CIRQ_IRQ_NUM 439
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index 8696f2a..a70abec 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -95,6 +95,11 @@
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define DEV_IRQ_ID 580
+
+#define PLAT_MTK_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
#define CIRQ_REG_NUM 23
diff --git a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
index 4e84d02..14ddefd 100644
--- a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
+++ b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
@@ -1,6 +1,6 @@
#
# Copyright 2018-2020 NXP
-# Copyright (c) 2023, Arm Limited. All rights reserved.
+# Copyright (c) 2023-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -73,7 +73,7 @@
ifeq (${FUSE_PROV_FILE},)
else
${BUILD_PLAT}/${FUSE_PROV_FILE_SB}: ${FUSE_PROV_FILE}
- @echo " Generating CSF Header for $@ $<"
+ $(s)echo " Generating CSF Header for $@ $<"
$(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
--app $< ${FUSE_INPUT_FILE}
endif
@@ -81,7 +81,7 @@
ifeq (${FUSE_UP_FILE},)
else
${BUILD_PLAT}/${FUSE_UP_FILE_SB}: ${FUSE_UP_FILE}
- @echo " Generating CSF Header for $@ $<"
+ $(s)echo " Generating CSF Header for $@ $<"
$(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
--app $< ${FUSE_INPUT_FILE}
endif
@@ -94,6 +94,6 @@
endif
${FIPTOOL} create ${FUSE_FIP_ARGS} $@
${FIPTOOL} info $@
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
diff --git a/plat/nxp/common/tbbr/tbbr.mk b/plat/nxp/common/tbbr/tbbr.mk
index 4aac9d6..000e419 100644
--- a/plat/nxp/common/tbbr/tbbr.mk
+++ b/plat/nxp/common/tbbr/tbbr.mk
@@ -131,14 +131,14 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- @if [ ! -f $(ROT_KEY) ]; then \
+ $(s)echo " OPENSSL $@"
+ $(q)if [ ! -f $(ROT_KEY) ]; then \
${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null; \
fi
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif #MBEDTLS_DIR
diff --git a/plat/nxp/s32/s32g274ardb2/platform.mk b/plat/nxp/s32/s32g274ardb2/platform.mk
index ee1507e..316ed2c 100644
--- a/plat/nxp/s32/s32g274ardb2/platform.mk
+++ b/plat/nxp/s32/s32g274ardb2/platform.mk
@@ -35,6 +35,7 @@
# Selecting Drivers for SoC
$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,CLK_NEEDED,BL_COMM))
include ${PLAT_DRIVERS_PATH}/drivers.mk
diff --git a/plat/nxp/soc-lx2160a/ddr_fip.mk b/plat/nxp/soc-lx2160a/ddr_fip.mk
index f14a9e8..e717cbc 100644
--- a/plat/nxp/soc-lx2160a/ddr_fip.mk
+++ b/plat/nxp/soc-lx2160a/ddr_fip.mk
@@ -73,11 +73,11 @@
ifneq (${GENERATE_COT},0)
ddr_certificates: ${DDR_CRT_DEPS} ${CRTTOOL}
- ${Q}${CRTTOOL} ${DDR_CRT_ARGS}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @echo "DDR certificates can be found in ${BUILD_PLAT}"
- @${ECHO_BLANK_LINE}
+ $(q)${CRTTOOL} ${DDR_CRT_ARGS}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo "DDR certificates can be found in ${BUILD_PLAT}"
+ $(s)echo
endif
endif
endif
@@ -88,10 +88,10 @@
${BUILD_PLAT}/${DDR_FIP_NAME}: ${DDR_FIP_DEPS} ${FIPTOOL}
$(eval ${CHECK_DDR_FIP_CMD})
- ${Q}${FIPTOOL} create ${DDR_FIP_ARGS} $@
- ${Q}${FIPTOOL} info $@
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(q)${FIPTOOL} create ${DDR_FIP_ARGS} $@
+ $(q)${FIPTOOL} info $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
fip_ddr: ${BUILD_PLAT}/${DDR_FIP_NAME}
diff --git a/plat/nxp/soc-lx2160a/ddr_sb.mk b/plat/nxp/soc-lx2160a/ddr_sb.mk
index c11651e..119fc08 100644
--- a/plat/nxp/soc-lx2160a/ddr_sb.mk
+++ b/plat/nxp/soc-lx2160a/ddr_sb.mk
@@ -36,7 +36,7 @@
endif
%.sb: %
- @echo " Generating CSF Header for $@ $<"
+ $(s)echo " Generating CSF Header for $@ $<"
$(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
--app $< ${DDR_INPUT_FILE}
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 436e425..066554a 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -79,12 +79,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
@@ -226,14 +226,14 @@
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
qemu_fw.bios: bl1 fip
- $(ECHO) " DD $@"
- $(Q)cp ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/$@
- $(Q)dd if=${BUILD_PLAT}/fip.bin of=${BUILD_PLAT}/$@ bs=64k seek=4 status=none
+ $(s)echo " DD $@"
+ $(q)cp ${BUILD_PLAT}/bl1.bin ${BUILD_PLAT}/$@
+ $(q)dd if=${BUILD_PLAT}/fip.bin of=${BUILD_PLAT}/$@ bs=64k seek=4 status=none
qemu_fw.rom: qemu_fw.bios
- $(ECHO) " DD $@"
- $(Q)cp ${BUILD_PLAT}/$^ ${BUILD_PLAT}/$@
- $(Q)dd if=/dev/zero of=${BUILD_PLAT}/$@ bs=1M seek=64 count=0 status=none
+ $(s)echo " DD $@"
+ $(q)cp ${BUILD_PLAT}/$^ ${BUILD_PLAT}/$@
+ $(q)dd if=/dev/zero of=${BUILD_PLAT}/$@ bs=1M seek=64 count=0 status=none
ifneq (${BL33},)
all: qemu_fw.bios qemu_fw.rom
diff --git a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
index 535f0eb..83e66f3 100644
--- a/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
+++ b/plat/qemu/qemu_sbsa/sbsa_sip_svc.c
@@ -30,6 +30,7 @@
#define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101)
#define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200)
#define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY SIP_FUNCTION_ID(202)
#define SIP_SVC_GET_MEMORY_NODE_COUNT SIP_FUNCTION_ID(300)
#define SIP_SVC_GET_MEMORY_NODE SIP_FUNCTION_ID(301)
@@ -46,10 +47,24 @@
uint64_t addr_size;
} memory_data;
+/*
+ * sockets: the number of sockets on sbsa-ref platform.
+ * clusters: the number of clusters in one socket.
+ * cores: the number of cores in one cluster.
+ * threads: the number of threads in one core.
+ */
+typedef struct {
+ uint32_t sockets;
+ uint32_t clusters;
+ uint32_t cores;
+ uint32_t threads;
+} cpu_topology;
+
static struct {
uint32_t num_cpus;
uint32_t num_memnodes;
cpu_data cpu[PLATFORM_CORE_COUNT];
+ cpu_topology cpu_topo;
memory_data memory[PLAT_MAX_MEM_NODES];
} dynamic_platform_info;
@@ -71,12 +86,46 @@
* cope.
*/
+static void read_cpu_topology_from_dt(void *dtb)
+{
+ int node;
+
+ /*
+ * QEMU gives us this DeviceTree node when we config:
+ * -smp 16,sockets=2,clusters=2,cores=2,threads=2
+ *
+ * topology {
+ * threads = <0x02>;
+ * cores = <0x02>;
+ * clusters = <0x02>;
+ * sockets = <0x02>;
+ * };
+ */
+
+ node = fdt_path_offset(dtb, "/cpus/topology");
+ if (node > 0) {
+ dynamic_platform_info.cpu_topo.sockets =
+ fdt_read_uint32_default(dtb, node, "sockets", 0);
+ dynamic_platform_info.cpu_topo.clusters =
+ fdt_read_uint32_default(dtb, node, "clusters", 0);
+ dynamic_platform_info.cpu_topo.cores =
+ fdt_read_uint32_default(dtb, node, "cores", 0);
+ dynamic_platform_info.cpu_topo.threads =
+ fdt_read_uint32_default(dtb, node, "threads", 0);
+ }
+
+ INFO("Cpu topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+ dynamic_platform_info.cpu_topo.sockets,
+ dynamic_platform_info.cpu_topo.clusters,
+ dynamic_platform_info.cpu_topo.cores,
+ dynamic_platform_info.cpu_topo.threads);
+}
+
void read_cpuinfo_from_dt(void *dtb)
{
int node;
int prev;
int cpu = 0;
- uint32_t nodeid = 0;
uintptr_t mpidr;
/*
@@ -118,14 +167,12 @@
panic();
}
- if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
- fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
- }
-
- dynamic_platform_info.cpu[cpu].nodeid = nodeid;
dynamic_platform_info.cpu[cpu].mpidr = mpidr;
+ dynamic_platform_info.cpu[cpu].nodeid =
+ fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
- INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, nodeid, mpidr);
+ INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu,
+ dynamic_platform_info.cpu[cpu].nodeid, mpidr);
cpu++;
@@ -135,6 +182,8 @@
dynamic_platform_info.num_cpus = cpu;
INFO("Found %d cpus\n", dynamic_platform_info.num_cpus);
+
+ read_cpu_topology_from_dt(dtb);
}
void read_meminfo_from_dt(void *dtb)
@@ -143,7 +192,6 @@
const char *type;
int prev, node;
int len;
- uint32_t nodeid = 0;
uint32_t memnode = 0;
uint32_t higher_value, lower_value;
uint64_t cur_base, cur_size;
@@ -172,11 +220,8 @@
type = fdt_getprop(dtb, node, "device_type", &len);
if (type && strncmp(type, "memory", len) == 0) {
- if (fdt_getprop(dtb, node, "numa-node-id", NULL)) {
- fdt_read_uint32(dtb, node, "numa-node-id", &nodeid);
- }
-
- dynamic_platform_info.memory[memnode].nodeid = nodeid;
+ dynamic_platform_info.memory[memnode].nodeid =
+ fdt_read_uint32_default(dtb, node, "numa-node-id", 0);
/*
* Get the 'reg' property of this node and
@@ -274,10 +319,10 @@
node = fdt_path_offset(dtb, "/");
if (node >= 0) {
- platform_version_major = fdt32_ld(fdt_getprop(dtb, node,
- "machine-version-major", NULL));
- platform_version_minor = fdt32_ld(fdt_getprop(dtb, node,
- "machine-version-minor", NULL));
+ platform_version_major =
+ fdt_read_uint32_default(dtb, node, "machine-version-major", 0);
+ platform_version_minor =
+ fdt_read_uint32_default(dtb, node, "machine-version-minor", 0);
}
}
@@ -354,6 +399,18 @@
SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM);
}
+ case SIP_SVC_GET_CPU_TOPOLOGY:
+ if (dynamic_platform_info.cpu_topo.cores > 0) {
+ SMC_RET5(handle, NULL,
+ dynamic_platform_info.cpu_topo.sockets,
+ dynamic_platform_info.cpu_topo.clusters,
+ dynamic_platform_info.cpu_topo.cores,
+ dynamic_platform_info.cpu_topo.threads);
+ } else {
+ /* we do not know topology so we report SMC as unknown */
+ SMC_RET1(handle, SMC_UNK);
+ }
+
case SIP_SVC_GET_MEMORY_NODE_COUNT:
SMC_RET2(handle, NULL, dynamic_platform_info.num_memnodes);
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 8e3f52e..4813949 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -351,13 +351,13 @@
LAYOUT_TOOLPATH ?= tools/renesas/rcar_layout_create
clean_layout_tool:
- @echo "clean layout tool"
- ${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean
+ $(s)echo "clean layout tool"
+ $(q)${MAKE} -C ${LAYOUT_TOOLPATH} clean
.PHONY: rcar_layout_tool
rcar_layout_tool:
- @echo "generating layout srecs"
- ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
+ $(s)echo "generating layout srecs"
+ $(q)${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
# srecords
SREC_PATH = ${BUILD_PLAT}
@@ -365,16 +365,16 @@
BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf
clean_srecord:
- @echo "clean bl2 and bl31 srecs"
+ $(s)echo "clean bl2 and bl31 srecs"
rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
$(SREC_PATH)/bl2.srec: $(BL2_ELF_SRC)
- @echo "generating srec: $(SREC_PATH)/bl2.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL2_ELF_SRC) $(SREC_PATH)/bl2.srec
+ $(s)echo "generating srec: $(SREC_PATH)/bl2.srec"
+ $(q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL2_ELF_SRC) $(SREC_PATH)/bl2.srec
$(SREC_PATH)/bl31.srec: $(BL31_ELF_SRC)
- @echo "generating srec: $(SREC_PATH)/bl31.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL31_ELF_SRC) $(SREC_PATH)/bl31.srec
+ $(s)echo "generating srec: $(SREC_PATH)/bl31.srec"
+ $(q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL31_ELF_SRC) $(SREC_PATH)/bl31.srec
.PHONY: rcar_srecord
rcar_srecord: $(SREC_PATH)/bl2.srec $(SREC_PATH)/bl31.srec
diff --git a/plat/renesas/rzg/platform.mk b/plat/renesas/rzg/platform.mk
index 354eada..5da6052 100644
--- a/plat/renesas/rzg/platform.mk
+++ b/plat/renesas/rzg/platform.mk
@@ -249,13 +249,13 @@
LAYOUT_TOOLPATH ?= tools/renesas/rzg_layout_create
clean_layout_tool:
- @echo "clean layout tool"
- ${Q}${MAKE} -C ${LAYOUT_TOOLPATH} clean
+ $(s)echo "clean layout tool"
+ $(q)${MAKE} -C ${LAYOUT_TOOLPATH} clean
.PHONY: rzg_layout_create
rzg_layout_create:
- @echo "generating layout srecs"
- ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
+ $(s)echo "generating layout srecs"
+ $(q)${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${LAYOUT_TOOLPATH}
# srecords
SREC_PATH = ${BUILD_PLAT}
@@ -263,16 +263,16 @@
BL31_ELF_SRC = ${SREC_PATH}/bl31/bl31.elf
clean_srecord:
- @echo "clean bl2 and bl31 srecs"
+ $(s)echo "clean bl2 and bl31 srecs"
rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
$(SREC_PATH)/bl2.srec: $(BL2_ELF_SRC)
- @echo "generating srec: $(SREC_PATH)/bl2.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL2_ELF_SRC) $(SREC_PATH)/bl2.srec
+ $(s)echo "generating srec: $(SREC_PATH)/bl2.srec"
+ $(q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL2_ELF_SRC) $(SREC_PATH)/bl2.srec
$(SREC_PATH)/bl31.srec: $(BL31_ELF_SRC)
- @echo "generating srec: $(SREC_PATH)/bl31.srec"
- $(Q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL31_ELF_SRC) $(SREC_PATH)/bl31.srec
+ $(s)echo "generating srec: $(SREC_PATH)/bl31.srec"
+ $(q)$($(ARCH)-oc) -O srec --srec-forceS3 $(BL31_ELF_SRC) $(SREC_PATH)/bl31.srec
.PHONY: rzg_srecord
rzg_srecord: $(SREC_PATH)/bl2.srec $(SREC_PATH)/bl31.srec
diff --git a/plat/rockchip/common/aarch32/platform_common.c b/plat/rockchip/common/aarch32/platform_common.c
index 9030951..25ee964 100644
--- a/plat/rockchip/common/aarch32/platform_common.c
+++ b/plat/rockchip/common/aarch32/platform_common.c
@@ -12,7 +12,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <lib/utils.h>
-#include <lib/xlat_tables/xlat_tables.h>
+#include <lib/xlat_tables/xlat_tables_compat.h>
#include <plat_private.h>
diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c
index d563dfd..df51d89 100644
--- a/plat/rockchip/common/aarch64/platform_common.c
+++ b/plat/rockchip/common/aarch64/platform_common.c
@@ -13,6 +13,8 @@
#include <common/debug.h>
#include <drivers/arm/cci.h>
#include <lib/utils.h>
+#include <lib/xlat_tables/xlat_tables_compat.h>
+
#include <plat_private.h>
#ifdef PLAT_RK_CCI_BASE
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 465f372..44a0c46 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -49,7 +49,7 @@
#endif
#ifndef BITS_SHIFT
-#define BITS_SHIFT(bits, shift) (bits << (shift))
+#define BITS_SHIFT(bits, shift) ((bits) << (shift))
#endif
#ifndef BITS_WITH_WMASK
diff --git a/plat/rockchip/rk3399/drivers/m0/Makefile b/plat/rockchip/rk3399/drivers/m0/Makefile
index 2abcc18..e742591 100644
--- a/plat/rockchip/rk3399/drivers/m0/Makefile
+++ b/plat/rockchip/rk3399/drivers/m0/Makefile
@@ -6,6 +6,7 @@
toolchains := rk3399-m0
+include ../../../../../make_helpers/common.mk
include ../../../../../make_helpers/toolchain.mk
# Cross Compile
@@ -18,13 +19,6 @@
PLAT_M0 ?= rk3399m0
PLAT_M0_PMU ?= rk3399m0pmu
-ifeq (${V},0)
- Q=@
-else
- Q=
-endif
-export Q
-
.SUFFIXES:
INCLUDES += -Iinclude/ \
@@ -71,16 +65,16 @@
-include $(patsubst %.o,%.d,$(OBJ))
$(OBJ) : $(2)
- @echo " CC $$<"
- $$(Q)$(rk3399-m0-cc) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
+ $(s)echo " CC $$<"
+ $$(q)$(rk3399-m0-cc) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
endef
define MAKE_S
$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(OBJ) : $(2)
- @echo " AS $$<"
- $$(Q)$(rk3399-m0-cc) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@
+ $(s)echo " AS $$<"
+ $$(q)$(rk3399-m0-cc) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@
endef
define MAKE_OBJS
@@ -105,16 +99,16 @@
-include $(LINKERFILE).d
$(ELF) : $(OBJS) $(OBJS_COMMON) $(LINKERFILE)
- @echo " LD $@"
- $(Q)$(rk3399-m0-cc) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS) $(OBJS_COMMON)
+ $(s)echo " LD $@"
+ $(q)$(rk3399-m0-cc) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS) $(OBJS_COMMON)
%.bin : %.elf
- @echo " BIN $@"
- $(Q)$(rk3399-m0-oc) -O binary $< $@
+ $(s)echo " BIN $@"
+ $(q)$(rk3399-m0-oc) -O binary $< $@
$(ELF_PMU) : $(OBJS_COMMON) $(OBJS_PMU) $(LINKERFILE)
- @echo " LD $@"
- $(Q)$(rk3399-m0-cc) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE_PMU) -Wl,-T$(LINKERFILE) $(OBJS_PMU) $(OBJS_COMMON)
+ $(s)echo " LD $@"
+ $(q)$(rk3399-m0-cc) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE_PMU) -Wl,-T$(LINKERFILE) $(OBJS_PMU) $(OBJS_COMMON)
$(eval $(call MAKE_OBJS,$(BUILD),$(SOURCES_COMMON),$(1)))
$(eval $(call MAKE_OBJS,$(BUILD),$(SOURCES),$(1)))
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index 8034fa4..eaaff7d 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -73,13 +73,13 @@
# This target concatenates BL1 and the FIP so that the base addresses match the
# ones defined in the memory map
armstub: bl1 fip
- @echo " CAT $@"
- ${Q}cp ${BUILD_PLAT}/bl1.bin ${RPI3_BL1_PAD_BIN}
- ${Q}truncate --size=131072 ${RPI3_BL1_PAD_BIN}
- ${Q}cat ${RPI3_BL1_PAD_BIN} ${BUILD_PLAT}/fip.bin > ${RPI3_ARMSTUB8_BIN}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " CAT $@"
+ $(q)cp ${BUILD_PLAT}/bl1.bin ${RPI3_BL1_PAD_BIN}
+ $(q)truncate --size=131072 ${RPI3_BL1_PAD_BIN}
+ $(q)cat ${RPI3_BL1_PAD_BIN} ${BUILD_PLAT}/fip.bin > ${RPI3_ARMSTUB8_BIN}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
# Build config flags
# ------------------
@@ -213,11 +213,11 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index a6d9bef..a5ab4f7 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -72,12 +72,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif # TRUSTED_BOARD_BOOT
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index d466aa1..ebb9b8c 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -106,12 +106,12 @@
certificates: $(ROT_KEY)
$(ROT_KEY): | $(BUILD_PLAT)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl genrsa 2048 > $@ 2>/dev/null
$(ROTPK_HASH): $(ROT_KEY)
- @echo " OPENSSL $@"
- $(Q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ $(s)echo " OPENSSL $@"
+ $(q)${OPENSSL_BIN_PATH}/openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
${OPENSSL_BIN_PATH}/openssl dgst -sha256 -binary > $@ 2>/dev/null
endif
@@ -136,5 +136,5 @@
.PHONY: bl2_gzip
bl2_gzip: $(BUILD_PLAT)/bl2.bin.gz
%.gz: %
- @echo " GZIP $@"
- $(Q)gzip -n -f -9 $< --stdout > $@
+ $(s)echo " GZIP $@"
+ $(q)gzip -n -f -9 $< --stdout > $@
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index f8a0c18..c17ac7e 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,6 +47,7 @@
uintptr_t storage_dev_handle;
static const io_dev_connector_t *fip_dev_con;
+static uint32_t nand_block_sz __maybe_unused;
#ifndef DECRYPTION_SUPPORT_none
static const io_dev_connector_t *enc_dev_con;
@@ -310,11 +311,55 @@
}
#endif /* STM32MP_SPI_NOR */
+#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
+/*
+ * This function returns 0 if it can find an alternate
+ * image to be loaded or a negative errno otherwise.
+ */
+static int try_nand_backup_partitions(unsigned int image_id)
+{
+ static unsigned int backup_id;
+ static unsigned int backup_block_nb;
+
+ /* Check if NAND storage used */
+ if (nand_block_sz == 0U) {
+ return -ENODEV;
+ }
+
+ if (backup_id != image_id) {
+ backup_block_nb = PLATFORM_MTD_MAX_PART_SIZE / nand_block_sz;
+ backup_id = image_id;
+ }
+
+ if (backup_block_nb-- == 0U) {
+ return -ENOSPC;
+ }
+
+#if PSA_FWU_SUPPORT
+ if (((image_block_spec.offset < STM32MP_NAND_FIP_B_OFFSET) &&
+ ((image_block_spec.offset + nand_block_sz) >= STM32MP_NAND_FIP_B_OFFSET)) ||
+ (image_block_spec.offset + nand_block_sz >= STM32MP_NAND_FIP_B_MAX_OFFSET)) {
+ return 0;
+ }
+#endif
+
+ image_block_spec.offset += nand_block_sz;
+
+ return 0;
+}
+
+static const struct plat_try_images_ops try_img_ops = {
+ .next_instance = try_nand_backup_partitions,
+};
+#endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */
+
#if STM32MP_RAW_NAND
static void boot_fmc2_nand(boot_api_context_t *boot_context)
{
int io_result __maybe_unused;
+ plat_setup_try_img_ops(&try_img_ops);
+
io_result = stm32_fmc2_init();
assert(io_result == 0);
@@ -326,6 +371,8 @@
io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
+
+ nand_block_sz = nand_dev_spec.erase_size;
}
#endif /* STM32MP_RAW_NAND */
@@ -334,6 +381,8 @@
{
int io_result __maybe_unused;
+ plat_setup_try_img_ops(&try_img_ops);
+
io_result = stm32_qspi_init();
assert(io_result == 0);
@@ -345,6 +394,8 @@
(uintptr_t)&spi_nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
+
+ nand_block_sz = spi_nand_dev_spec.erase_size;
}
#endif /* STM32MP_SPI_NAND */
@@ -530,7 +581,14 @@
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
#endif
+/*
+ * With FWU Multi Bank feature enabled, the selection of
+ * the image to boot will be done by fwu_init calling the
+ * platform hook, plat_fwu_set_images_source.
+ */
+#if !PSA_FWU_SUPPORT
image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
+#endif
break;
#endif
@@ -596,7 +654,7 @@
return rc;
}
-#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
+#if PSA_FWU_SUPPORT
/*
* In each boot in non-trial mode, we set the BKP register to
* FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata.
@@ -710,6 +768,19 @@
}
break;
#endif
+#if (STM32MP_RAW_NAND || STM32MP_SPI_NAND)
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
+ if (guidcmp(img_guid, &STM32MP_NAND_FIP_A_GUID) == 0) {
+ image_spec->offset = STM32MP_NAND_FIP_A_OFFSET;
+ } else if (guidcmp(img_guid, &STM32MP_NAND_FIP_B_GUID) == 0) {
+ image_spec->offset = STM32MP_NAND_FIP_B_OFFSET;
+ } else {
+ ERROR("Invalid uuid mentioned in metadata\n");
+ panic();
+ }
+ break;
+#endif
default:
panic();
break;
@@ -717,9 +788,9 @@
}
}
-static int plat_set_image_source(unsigned int image_id,
- uintptr_t *handle,
- uintptr_t *image_spec)
+static int set_metadata_image_source(unsigned int image_id,
+ uintptr_t *handle,
+ uintptr_t *image_spec)
{
struct plat_io_policy *policy;
io_block_spec_t *spec __maybe_unused;
@@ -762,6 +833,19 @@
spec->length = sizeof(struct fwu_metadata);
break;
#endif
+
+#if (STM32MP_RAW_NAND || STM32MP_SPI_NAND)
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI:
+ if (image_id == FWU_METADATA_IMAGE_ID) {
+ spec->offset = STM32MP_NAND_METADATA1_OFFSET;
+ } else {
+ spec->offset = STM32MP_NAND_METADATA2_OFFSET;
+ }
+
+ spec->length = sizeof(struct fwu_metadata);
+ break;
+#endif
default:
panic();
break;
@@ -780,6 +864,6 @@
assert((image_id == FWU_METADATA_IMAGE_ID) ||
(image_id == BKUP_FWU_METADATA_IMAGE_ID));
- return plat_set_image_source(image_id, handle, image_spec);
+ return set_metadata_image_source(image_id, handle, image_spec);
}
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
+#endif /* PSA_FWU_SUPPORT */
diff --git a/plat/st/common/common.mk b/plat/st/common/common.mk
index 7ef7665..7395a36 100644
--- a/plat/st/common/common.mk
+++ b/plat/st/common/common.mk
@@ -28,6 +28,24 @@
TF_CFLAGS += -Wsign-compare
TF_CFLAGS += -Wformat-signedness
+# Number of TF-A copies in the device
+STM32_TF_A_COPIES := 2
+
+# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
+PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + $(STM32_EXTRA_PARTS))))
+
+ifeq (${PSA_FWU_SUPPORT},1)
+# Number of banks of updatable firmware
+NR_OF_FW_BANKS := 2
+NR_OF_IMAGES_IN_FW_BANK := 1
+
+FWU_MAX_PART = $(shell echo $$(($(STM32_TF_A_COPIES) + 2 + $(NR_OF_FW_BANKS))))
+ifeq ($(shell test $(FWU_MAX_PART) -gt $(PLAT_PARTITION_MAX_ENTRIES); echo $$?),0)
+$(error "Required partition number is $(FWU_MAX_PART) where PLAT_PARTITION_MAX_ENTRIES is only \
+$(PLAT_PARTITION_MAX_ENTRIES)")
+endif
+endif
+
# Boot devices
STM32MP_EMMC ?= 0
STM32MP_SDMMC ?= 0
@@ -120,6 +138,9 @@
include lib/fconf/fconf.mk
include lib/libfdt/libfdt.mk
include lib/zlib/zlib.mk
+ifeq (${PSA_FWU_SUPPORT},1)
+include drivers/fwu/fwu.mk
+endif
PLAT_BL_COMMON_SOURCES += common/uuid.c \
plat/st/common/stm32mp_common.c
diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index 212a67d..8b81c7f 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk
@@ -15,7 +15,7 @@
bl2: check_boot_device
check_boot_device:
- @if [ ${STM32MP_EMMC} != 1 ] && \
+ $(q)if [ ${STM32MP_EMMC} != 1 ] && \
[ ${STM32MP_SDMMC} != 1 ] && \
[ ${STM32MP_RAW_NAND} != 1 ] && \
[ ${STM32MP_SPI_NAND} != 1 ] && \
@@ -29,55 +29,55 @@
stm32image: ${STM32IMAGE}
${STM32IMAGE}: ${STM32IMAGE_SRC}
- ${Q}${MAKE} CPPFLAGS="" --no-print-directory -C ${STM32IMAGEPATH}
+ $(q)${MAKE} CPPFLAGS="" --no-print-directory -C ${STM32IMAGEPATH}
clean_stm32image:
- ${Q}${MAKE} --no-print-directory -C ${STM32IMAGEPATH} clean
+ $(q)${MAKE} --no-print-directory -C ${STM32IMAGEPATH} clean
check_dtc_version:
- @if [ ${DTC_VERSION} -lt 10407 ]; then \
+ $(q)if [ ${DTC_VERSION} -lt 10407 ]; then \
echo "dtc version too old (${DTC_V}), you need at least version 1.4.7"; \
false; \
fi
# Create DTB file for BL2
${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | ${BUILD_PLAT} fdt_dirs
- @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
- @echo '#include "${BL2_DTSI}"' >> $@
+ $(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@
+ $(q)echo '#include "${BL2_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl2.dtb: ${BUILD_PLAT}/fdts/%-bl2.dts
${BUILD_PLAT}/$(PLAT)-%.o: ${BUILD_PLAT}/fdts/%-bl2.dtb $(STM32_BINARY_MAPPING) bl2
- @echo " AS $${PLAT}.S"
- ${Q}$($(ARCH)-as) -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) ${ASFLAGS} ${TF_CFLAGS} \
+ $(s)echo " AS $${PLAT}.S"
+ $(q)$($(ARCH)-as) -x assembler-with-cpp $(TF_CFLAGS_$(ARCH)) ${ASFLAGS} ${TF_CFLAGS} \
-DDTB_BIN_PATH=\"$<\" \
-c $(word 2,$^) -o $@
$(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},$(STM32_LD_FILE),bl2))
tf-a-%.elf: $(PLAT)-%.o ${STM32_TF_LINKERFILE}
- @echo " LDS $<"
+ $(s)echo " LDS $<"
ifeq ($($(ARCH)-ld-id),gnu-gcc)
- ${Q}$($(ARCH)-ld) -o $@ $(subst --,-Wl$(comma)--,${STM32_TF_ELF_LDFLAGS}) -nostartfiles -Wl,-Map=$(@:.elf=.map) -Wl,-dT ${STM32_TF_LINKERFILE} $<
+ $(q)$($(ARCH)-ld) -o $@ $(subst --,-Wl$(comma)--,${STM32_TF_ELF_LDFLAGS}) -nostartfiles -Wl,-Map=$(@:.elf=.map) -Wl,-dT ${STM32_TF_LINKERFILE} $<
else
- ${Q}$($(ARCH)-ld) -o $@ ${STM32_TF_ELF_LDFLAGS} -Map=$(@:.elf=.map) --script ${STM32_TF_LINKERFILE} $<
+ $(q)$($(ARCH)-ld) -o $@ ${STM32_TF_ELF_LDFLAGS} -Map=$(@:.elf=.map) --script ${STM32_TF_LINKERFILE} $<
endif
tf-a-%.bin: tf-a-%.elf
- ${Q}$($(ARCH)-oc) -O binary $< $@
- @echo
- @echo "Built $@ successfully"
- @echo
+ $(q)$($(ARCH)-oc) -O binary $< $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
tf-a-%.stm32: tf-a-%.bin ${STM32_DEPS}
- @echo
- @echo "Generate $@"
+ $(s)echo
+ $(s)echo "Generate $@"
$(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep '^RAM' | awk '{print $$2}'))
$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
- ${Q}${STM32IMAGE} -s $< -d $@ \
+ $(q)${STM32IMAGE} -s $< -d $@ \
-l $(LOADADDR) -e ${ENTRY} \
-v ${STM32_TF_VERSION} \
-m ${STM32_HEADER_VERSION_MAJOR} \
-n ${STM32_HEADER_VERSION_MINOR} \
-b ${STM32_HEADER_BL2_BINARY_TYPE}
- @echo
+ $(s)echo
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 41b86ae..9af221c 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -131,7 +131,8 @@
void stm32_display_board_info(uint32_t board_id);
#if PSA_FWU_SUPPORT
-void stm32mp1_fwu_set_boot_idx(void);
+uintptr_t stm32_get_bkpr_fwu_info_addr(void);
+void stm32_fwu_set_boot_idx(void);
uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void);
void stm32_set_max_fwu_trial_boot_cnt(void);
void stm32_clear_fwu_trial_boot_cnt(void);
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 6f36011..d2f8784 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -55,6 +55,12 @@
#define BOOT_INST_MASK GENMASK_32(11, 8)
#define BOOT_INST_SHIFT 8
+/* Layout for fwu update information. */
+#define FWU_INFO_IDX_MSK GENMASK(3, 0)
+#define FWU_INFO_IDX_OFF U(0)
+#define FWU_INFO_CNT_MSK GENMASK(7, 4)
+#define FWU_INFO_CNT_OFF U(4)
+
static console_t console;
uintptr_t plat_get_ns_image_entrypoint(void)
@@ -378,3 +384,53 @@
*interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
*instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
}
+
+#if PSA_FWU_SUPPORT
+void stm32_fwu_set_boot_idx(void)
+{
+ clk_enable(TAMP_BKP_REG_CLK);
+ mmio_clrsetbits_32(stm32_get_bkpr_fwu_info_addr(),
+ FWU_INFO_IDX_MSK,
+ (plat_fwu_get_boot_idx() << FWU_INFO_IDX_OFF) &
+ FWU_INFO_IDX_MSK);
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+
+uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void)
+{
+ uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
+ uint32_t try_cnt;
+
+ clk_enable(TAMP_BKP_REG_CLK);
+ try_cnt = (mmio_read_32(bkpr_fwu_cnt) & FWU_INFO_CNT_MSK) >> FWU_INFO_CNT_OFF;
+
+ assert(try_cnt <= FWU_MAX_TRIAL_REBOOT);
+
+ if (try_cnt != 0U) {
+ mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK,
+ (try_cnt - 1U) << FWU_INFO_CNT_OFF);
+ }
+ clk_disable(TAMP_BKP_REG_CLK);
+
+ return try_cnt;
+}
+
+void stm32_set_max_fwu_trial_boot_cnt(void)
+{
+ uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
+
+ clk_enable(TAMP_BKP_REG_CLK);
+ mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK,
+ (FWU_MAX_TRIAL_REBOOT << FWU_INFO_CNT_OFF) & FWU_INFO_CNT_MSK);
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+
+void stm32_clear_fwu_trial_boot_cnt(void)
+{
+ uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
+
+ clk_enable(TAMP_BKP_REG_CLK);
+ mmio_clrbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK);
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+#endif /* PSA_FWU_SUPPORT */
diff --git a/plat/st/common/stm32mp_fconf_io.c b/plat/st/common/stm32mp_fconf_io.c
index 5514c09..6ed09d9 100644
--- a/plat/st/common/stm32mp_fconf_io.c
+++ b/plat/st/common/stm32mp_fconf_io.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2021-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,12 +27,12 @@
};
#endif
-#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
+#if PSA_FWU_SUPPORT
static io_block_spec_t metadata_block_spec = {
.offset = 0, /* To be filled at runtime */
.length = 0, /* To be filled at runtime */
};
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
+#endif /* PSA_FWU_SUPPORT */
/* By default, STM32 platforms load images from the FIP */
struct plat_io_policy policies[MAX_NUMBER_IDS] = {
@@ -58,7 +58,7 @@
.check = open_storage
},
#endif
-#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT
+#if PSA_FWU_SUPPORT
[FWU_METADATA_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&metadata_block_spec,
@@ -71,7 +71,7 @@
.img_type_guid = NULL_GUID,
.check = open_storage
},
-#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */
+#endif /* PSA_FWU_SUPPORT */
};
#define DEFAULT_UUID_NUMBER U(7)
diff --git a/plat/st/common/stm32mp_gic.c b/plat/st/common/stm32mp_gic.c
index d02b635..a4cc4a5 100644
--- a/plat/st/common/stm32mp_gic.c
+++ b/plat/st/common/stm32mp_gic.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/debug.h>
+#include <common/fdt_wrappers.h>
#include <drivers/arm/gicv2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <lib/utils.h>
@@ -45,25 +46,29 @@
int node;
void *fdt;
const fdt32_t *cuint;
- struct dt_node_info dt_gic;
+ uintptr_t addr;
+ int err;
if (fdt_get_address(&fdt) == 0) {
panic();
}
- node = dt_get_node(&dt_gic, -1, "arm,cortex-a7-gic");
+ node = fdt_node_offset_by_compatible(fdt, -1, "arm,cortex-a7-gic");
if (node < 0) {
panic();
}
- platform_gic_data.gicd_base = dt_gic.base;
-
- cuint = fdt_getprop(fdt, node, "reg", NULL);
- if (cuint == NULL) {
+ err = fdt_get_reg_props_by_index(fdt, node, 0, &addr, NULL);
+ if (err < 0) {
panic();
}
+ platform_gic_data.gicd_base = addr;
- platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2));
+ err = fdt_get_reg_props_by_index(fdt, node, 1, &addr, NULL);
+ if (err < 0) {
+ panic();
+ }
+ platform_gic_data.gicc_base = addr;
cuint = fdt_getprop(fdt, node, "#interrupt-cells", NULL);
if (cuint == NULL) {
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 24ecb32..2ade242 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -507,7 +507,7 @@
assert(bl32_mem_params != NULL);
bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
#if PSA_FWU_SUPPORT
- stm32mp1_fwu_set_boot_idx();
+ stm32_fwu_set_boot_idx();
#endif /* PSA_FWU_SUPPORT */
break;
diff --git a/plat/st/stm32mp1/cert_create_tbbr.mk b/plat/st/stm32mp1/cert_create_tbbr.mk
index e747e39..fb9e5ec 100644
--- a/plat/st/stm32mp1/cert_create_tbbr.mk
+++ b/plat/st/stm32mp1/cert_create_tbbr.mk
@@ -11,7 +11,7 @@
PLAT_INCLUDE += -I${PLAT_DIR}include
src/stm32mp1_tbb_cert.o: ${PLAT_DIR}stm32mp1_tbb_cert.c
- ${Q}$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
+ $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
PLAT_OBJECTS = src/stm32mp1_tbb_cert.o
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index c411edf..a1f44e8 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -4,6 +4,10 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# Extra partitions used to find FIP, contains:
+# metadata (2) and the FIP partitions (default is 2).
+STM32_EXTRA_PARTS := 4
+
include plat/st/common/common.mk
ARM_CORTEX_A7 := yes
@@ -80,25 +84,6 @@
WORKAROUND_CVE_2017_5715:= 0
WORKAROUND_CVE_2022_23960:= 0
-# Number of TF-A copies in the device
-STM32_TF_A_COPIES := 2
-
-# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
-# such as metadata (2) to find all the FIP partitions (default is 2).
-PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4)))
-
-ifeq (${PSA_FWU_SUPPORT},1)
-# Number of banks of updatable firmware
-NR_OF_FW_BANKS := 2
-NR_OF_IMAGES_IN_FW_BANK := 1
-
-FWU_MAX_PART = $(shell echo $$(($(STM32_TF_A_COPIES) + 2 + $(NR_OF_FW_BANKS))))
-ifeq ($(shell test $(FWU_MAX_PART) -gt $(PLAT_PARTITION_MAX_ENTRIES); echo $$?),0)
-$(error "Required partition number is $(FWU_MAX_PART) where PLAT_PARTITION_MAX_ENTRIES is only \
-$(PLAT_PARTITION_MAX_ENTRIES)")
-endif
-endif
-
ifeq ($(STM32MP13),1)
STM32_HASH_VER := 4
STM32_RNG_VER := 4
@@ -228,10 +213,6 @@
BL2_SOURCES += plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
plat/st/stm32mp1/stm32mp1_fconf_firewall.c
-ifeq (${PSA_FWU_SUPPORT},1)
-include drivers/fwu/fwu.mk
-endif
-
BL2_SOURCES += drivers/st/crypto/stm32_hash.c \
plat/st/stm32mp1/bl2_plat_setup.c
@@ -275,8 +256,8 @@
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | ${BUILD_PLAT} fdt_dirs
- @echo '#include "$(patsubst fdts/%,%,$<)"' > $@
- @echo '#include "${BL32_DTSI}"' >> $@
+ $(q)echo '#include "$(patsubst fdts/%,%,$<)"' > $@
+ $(q)echo '#include "${BL32_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts
endif
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 8a1d76d..824563f 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -10,6 +10,7 @@
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/st/stm32mp1_rcc.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/gpio/stm32-gpio.h>
#include <dt-bindings/reset/stm32mp1-resets.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
@@ -231,21 +232,7 @@
#endif
#define GPIO_BANK_OFFSET U(0x1000)
-/* Bank IDs used in GPIO driver API */
-#define GPIO_BANK_A U(0)
-#define GPIO_BANK_B U(1)
-#define GPIO_BANK_C U(2)
-#define GPIO_BANK_D U(3)
-#define GPIO_BANK_E U(4)
-#define GPIO_BANK_F U(5)
-#define GPIO_BANK_G U(6)
-#define GPIO_BANK_H U(7)
-#define GPIO_BANK_I U(8)
#if STM32MP15
-#define GPIO_BANK_J U(9)
-#define GPIO_BANK_K U(10)
-#define GPIO_BANK_Z U(25)
-
#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
#endif
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index f098eb3..189f83d 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -29,10 +29,6 @@
* (so it should be in Zone 2).
*/
#define TAMP_BOOT_FWU_INFO_REG_ID U(10)
-#define TAMP_BOOT_FWU_INFO_IDX_MSK GENMASK(3, 0)
-#define TAMP_BOOT_FWU_INFO_IDX_OFF U(0)
-#define TAMP_BOOT_FWU_INFO_CNT_MSK GENMASK(7, 4)
-#define TAMP_BOOT_FWU_INFO_CNT_OFF U(4)
#if defined(IMAGE_BL2)
#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
@@ -115,14 +111,14 @@
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
#if STM32MP13
- assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I));
+ assert(bank <= GPIO_BANK_I);
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return GPIOZ_BASE;
}
- assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K));
+ assert(bank <= GPIO_BANK_K);
#endif
return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
@@ -131,14 +127,14 @@
uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
{
#if STM32MP13
- assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I));
+ assert(bank <= GPIO_BANK_I);
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return 0;
}
- assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K));
+ assert(bank <= GPIO_BANK_K);
#endif
return bank * GPIO_BANK_OFFSET;
@@ -161,14 +157,14 @@
unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
{
#if STM32MP13
- assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_I));
+ assert(bank <= GPIO_BANK_I);
#endif
#if STM32MP15
if (bank == GPIO_BANK_Z) {
return GPIOZ;
}
- assert((GPIO_BANK_A == 0) && (bank <= GPIO_BANK_K));
+ assert(bank <= GPIO_BANK_K);
#endif
return GPIOA + (bank - GPIO_BANK_A);
@@ -674,53 +670,8 @@
}
#if PSA_FWU_SUPPORT
-void stm32mp1_fwu_set_boot_idx(void)
+uintptr_t stm32_get_bkpr_fwu_info_addr(void)
{
- clk_enable(RTCAPB);
- mmio_clrsetbits_32(tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID),
- TAMP_BOOT_FWU_INFO_IDX_MSK,
- (plat_fwu_get_boot_idx() << TAMP_BOOT_FWU_INFO_IDX_OFF) &
- TAMP_BOOT_FWU_INFO_IDX_MSK);
- clk_disable(RTCAPB);
-}
-
-uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void)
-{
- uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
- uint32_t try_cnt;
-
- clk_enable(RTCAPB);
- try_cnt = (mmio_read_32(bkpr_fwu_cnt) & TAMP_BOOT_FWU_INFO_CNT_MSK) >>
- TAMP_BOOT_FWU_INFO_CNT_OFF;
-
- assert(try_cnt <= FWU_MAX_TRIAL_REBOOT);
-
- if (try_cnt != 0U) {
- mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK,
- (try_cnt - 1U) << TAMP_BOOT_FWU_INFO_CNT_OFF);
- }
- clk_disable(RTCAPB);
-
- return try_cnt;
-}
-
-void stm32_set_max_fwu_trial_boot_cnt(void)
-{
- uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
-
- clk_enable(RTCAPB);
- mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK,
- (FWU_MAX_TRIAL_REBOOT << TAMP_BOOT_FWU_INFO_CNT_OFF) &
- TAMP_BOOT_FWU_INFO_CNT_MSK);
- clk_disable(RTCAPB);
-}
-
-void stm32_clear_fwu_trial_boot_cnt(void)
-{
- uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
-
- clk_enable(RTCAPB);
- mmio_clrbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK);
- clk_disable(RTCAPB);
+ return tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
}
#endif /* PSA_FWU_SUPPORT */
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index bf2952d..11b1138 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -4,6 +4,10 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# Extra partitions used to find FIP, contains:
+# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2).
+STM32_EXTRA_PARTS := 6
+
include plat/st/common/common.mk
CRASH_REPORTING := 1
@@ -19,13 +23,6 @@
STM32_HEADER_VERSION_MAJOR := 2
STM32_HEADER_VERSION_MINOR := 2
-# Number of TF-A copies in the device
-STM32_TF_A_COPIES := 2
-
-# PLAT_PARTITION_MAX_ENTRIES must take care of STM32_TF-A_COPIES and other partitions
-# such as metadata (2) and fsbl-m (2) to find all the FIP partitions (default is 2).
-PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 6)))
-
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 56c62e1..e3662ad 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -14,6 +14,7 @@
#include <drivers/st/stm32mp25_rcc.h>
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/clock/stm32mp25-clksrc.h>
+#include <dt-bindings/gpio/stm32-gpio.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
#ifndef __ASSEMBLER__
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 08c0205..594784f 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -118,19 +118,6 @@
panic();
} else {
INFO("BL31: PLM to TF-A handover success %u\n", ret);
-
- /*
- * The BL32 load address is indicated as 0x0 in the handoff
- * parameters, which is different from the default/user-provided
- * load address of 0x60000000 but the flags are correctly
- * configured. Consequently, in this scenario, set the PC
- * to the requested BL32_BASE address.
- */
-
- /* TODO: Remove the following check once this is fixed from PLM */
- if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
- bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
- }
}
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index b38f394..5af2b1d 100644
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -59,6 +59,20 @@
DISABLE_ALL_EXCEPTIONS);
}
+/* Define read and write function for clusterbusqos register */
+DEFINE_RENAME_SYSREG_RW_FUNCS(cluster_bus_qos, S3_0_C15_C4_4)
+
+static void versal_net_setup_qos(void)
+{
+ int ret;
+
+ ret = read_cluster_bus_qos();
+ INFO("BL31: default cluster bus qos: 0x%x\n", ret);
+ write_cluster_bus_qos(0);
+ ret = read_cluster_bus_qos();
+ INFO("BL31: cluster bus qos written: 0x%x\n", ret);
+}
+
/*
* Perform any BL31 specific platform actions. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
@@ -103,6 +117,8 @@
NOTICE("TF-A running on %s %d.%d\n", board_name_decode(),
platform_version / 10U, platform_version % 10U);
+ versal_net_setup_qos();
+
/* Initialize the platform config for future decision making */
versal_net_config_setup();
@@ -137,18 +153,6 @@
INFO("BL31: PLM to TF-A handover success\n");
- /*
- * The BL32 load address is indicated as 0x0 in the handoff
- * parameters, which is different from the default/user-provided
- * load address of 0x60000000 but the flags are correctly
- * configured. Consequently, in this scenario, set the PC
- * to the requested BL32_BASE address.
- */
-
- /* TODO: Remove the following check once this is fixed from PLM */
- if (bl32_image_ep_info.pc == 0 && bl32_image_ep_info.spsr != 0) {
- bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
- }
} else {
INFO("BL31: setting up default configs\n");
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index e266615..3a752b2 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -2,7 +2,7 @@
# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
# Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
# Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved.
-# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -16,6 +16,7 @@
IPI_CRC_CHECK := 0
override RESET_TO_BL31 := 1
override WARMBOOT_ENABLE_DCACHE_EARLY := 1
+ENABLE_LTO := 1
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/tools/amlogic/Makefile b/tools/amlogic/Makefile
index 5ff26e5..7a53437 100644
--- a/tools/amlogic/Makefile
+++ b/tools/amlogic/Makefile
@@ -10,11 +10,11 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
PROJECT := doimage${BIN_EXT}
OBJECTS := doimage.o
-V := 0
HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE
@@ -24,26 +24,20 @@
HOSTCCFLAGS += -O2
endif
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
-
.PHONY: all clean distclean
all: ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- ${Q}$(host-cc) ${OBJECTS} -o $@
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} -o $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
%.o: %.c Makefile
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${HOSTCCFLAGS} $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${HOSTCCFLAGS} $< -o $@
clean:
$(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS})
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index 21523f6..16f4aa3 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -5,7 +5,6 @@
#
PLAT := none
-V ?= 0
DEBUG := 0
CRTTOOL ?= cert_create${BIN_EXT}
BINARY := $(notdir ${CRTTOOL})
@@ -16,8 +15,10 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
+include ${MAKE_HELPERS_DIRECTORY}utilities.mk
ifneq (${PLAT},none)
TF_PLATFORM_ROOT := ../../plat/
@@ -60,13 +61,7 @@
HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
endif
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
-
-HOSTCCFLAGS += ${DEFINES}
+HOSTCCFLAGS += ${DEFINES} -DPLAT_MSG=$(call escape-shell,"$(PLAT_MSG)")
# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
# computed value.
HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3)
@@ -89,23 +84,20 @@
all: --openssl ${BINARY}
${BINARY}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \
- const char platform_msg[] = "${PLAT_MSG}";' | \
- $(host-cc) -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o
- ${Q}$(host-cc) src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
%.o: %.c
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
--openssl:
ifeq ($(DEBUG),1)
- @echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}"
+ $(s)echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}"
endif
clean:
- $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})
+ $(call SHELL_DELETE_ALL,${OBJECTS})
realclean: clean
$(call SHELL_DELETE,${BINARY})
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index 14610ed..edc2d68 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,10 +66,8 @@
static int save_keys;
static int print_cert;
-/* Info messages created in the Makefile */
-extern const char build_msg[];
-extern const char platform_msg[];
-
+static const char build_msg[] = "Built : " __TIME__ ", " __DATE__;
+static const char platform_msg[] = PLAT_MSG;
static char *strdup(const char *str)
{
diff --git a/tools/encrypt_fw/Makefile b/tools/encrypt_fw/Makefile
index 83f2f57..0210c36 100644
--- a/tools/encrypt_fw/Makefile
+++ b/tools/encrypt_fw/Makefile
@@ -1,10 +1,10 @@
#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
# Copyright (c) 2019-2022, Linaro Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-V ?= 0
BUILD_INFO ?= 1
DEBUG := 0
ENCTOOL ?= encrypt_fw${BIN_EXT}
@@ -16,6 +16,7 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
@@ -38,11 +39,6 @@
HOSTCCFLAGS += -O2 -DLOG_LEVEL=10
endif
endif
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
HOSTCCFLAGS += ${DEFINES}
# USING_OPENSSL3 flag will be added to the HOSTCCFLAGS variable with the proper
@@ -68,22 +64,20 @@
all: --openssl ${BINARY}
${BINARY}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__;' | \
- $(host-cc) -c ${HOSTCCFLAGS} -xc - -o src/build_msg.o
- ${Q}$(host-cc) src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} ${LIB_DIR} ${LIB} -o $@
%.o: %.c
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INC_DIR} $< -o $@
--openssl:
ifeq ($(DEBUG),1)
- @echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}"
+ $(s)echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}"
endif
clean:
- $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS})
+ $(call SHELL_DELETE_ALL,${OBJECTS})
realclean: clean
$(call SHELL_DELETE,${BINARY})
diff --git a/tools/encrypt_fw/src/main.c b/tools/encrypt_fw/src/main.c
index 39b7af7..6e43e73 100644
--- a/tools/encrypt_fw/src/main.c
+++ b/tools/encrypt_fw/src/main.c
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Linaro Limited. All rights reserved.
* Author: Sumit Garg <sumit.garg@linaro.org>
*
@@ -25,8 +26,7 @@
/* Global options */
-/* Info messages created in the Makefile */
-extern const char build_msg[];
+static const char build_msg[] = "Built : " __TIME__ ", " __DATE__;
static char *key_algs_str[] = {
[KEY_ALG_GCM] = "gcm",
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index 865ff4c..23c8e64 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -9,13 +9,13 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}defaults.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
FIPTOOL ?= fiptool${BIN_EXT}
PROJECT := $(notdir ${FIPTOOL})
OBJECTS := fiptool.o tbbr_config.o
-V ?= 0
STATIC ?= 0
override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
@@ -55,12 +55,6 @@
HOSTCCFLAGS += ${DEFINES}
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
-
ifneq (${PLAT},)
TF_PLATFORM_ROOT := ../../plat/
include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
@@ -81,22 +75,22 @@
all: --openssl ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- ${Q}$(host-cc) ${OBJECTS} -o $@ $(LDOPTS)
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} -o $@ $(LDOPTS)
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
%.o: %.c Makefile
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} -MD -MP $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} -MD -MP $< -o $@
-include $(DEPS)
--openssl:
ifeq ($(STATIC),0)
ifeq ($(DEBUG),1)
- @echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}"
+ $(s)echo "Selected OpenSSL version: ${OPENSSL_CURRENT_VER}"
endif
endif # STATIC
diff --git a/tools/marvell/doimage/Makefile b/tools/marvell/doimage/Makefile
index 6e59aa2..488b768 100644
--- a/tools/marvell/doimage/Makefile
+++ b/tools/marvell/doimage/Makefile
@@ -6,6 +6,7 @@
toolchains := host
+include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
PROJECT = doimage
@@ -36,16 +37,16 @@
all: ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- ${Q}$(host-cc) ${OBJECTS} ${DOIMAGE_LD_FLAGS} -o $@
- @echo
- @echo "Built $@ successfully"
- @echo
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} ${DOIMAGE_LD_FLAGS} -o $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
%.o: %.c Makefile
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
clean:
- ${Q}${RM} ${PROJECT}
- ${Q}${RM} ${OBJECTS}
+ $(q)${RM} ${PROJECT}
+ $(q)${RM} ${OBJECTS}
diff --git a/tools/nxp/create_pbl/Makefile b/tools/nxp/create_pbl/Makefile
index b6b3b04..7648b7f 100644
--- a/tools/nxp/create_pbl/Makefile
+++ b/tools/nxp/create_pbl/Makefile
@@ -9,13 +9,13 @@
MAKE_HELPERS_DIRECTORY := ../../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
PROJECT_1 := create_pbl${BIN_EXT}
OBJECTS_1 := create_pbl.o
PROJECT_2 := byte_swap${BIN_EXT}
OBJECTS_2 := byte_swap.o
-V ?= 0
override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
CFLAGS := -Wall -Werror -pedantic -std=c99
@@ -26,12 +26,6 @@
endif
LDLIBS :=
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
-
INCLUDE_PATHS :=
.PHONY: all clean distclean
@@ -39,22 +33,22 @@
all: create_pbl byte_swap
${PROJECT_1}: ${OBJECTS_1} Makefile
- @echo " LD $@"
- ${Q}$(host-cc) ${OBJECTS_1} -o $@ ${LDLIBS}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " LD $@"
+ $(q)$(host-cc) ${OBJECTS_1} -o $@ ${LDLIBS}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
${PROJECT_2}: ${OBJECTS_2} Makefile
- @echo " LD $@"
- ${Q}$(host-cc) ${OBJECTS_2} -o $@ ${LDLIBS}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " LD $@"
+ $(q)$(host-cc) ${OBJECTS_2} -o $@ ${LDLIBS}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
%.o: %.c %.h Makefile
- @echo " CC $<"
- ${Q}$(host-cc) -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@
+ $(s)echo " CC $<"
+ $(q)$(host-cc) -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@
clean:
$(call SHELL_DELETE_ALL, ${PROJECT_1} ${OBJECTS_1})
diff --git a/tools/nxp/create_pbl/pbl_ch2.mk b/tools/nxp/create_pbl/pbl_ch2.mk
index e6f1d8b..bf05a12 100644
--- a/tools/nxp/create_pbl/pbl_ch2.mk
+++ b/tools/nxp/create_pbl/pbl_ch2.mk
@@ -15,12 +15,12 @@
ifeq ($(SECURE_BOOT),yes)
pbl: ${BUILD_PLAT}/bl2.bin
ifeq ($(RCW),"")
- ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+ $(s)echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
else
# Generate header for bl2.bin
- $(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
+ $(q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
# Compile create_pbl tool
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
+ $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
# Add bl2.bin to RCW
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;\
@@ -31,7 +31,7 @@
# Swapping of RCW is required for QSPi Chassis 2 devices
ifeq (${BOOT_MODE}, qspi)
ifeq ($(SWAP),1)
- ${Q}echo "Byteswapping RCW for QSPI"
+ $(s)echo "Byteswapping RCW for QSPI"
${BYTE_SWAP} ${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl;
endif # SWAP
endif # BOOT_MODE
@@ -39,22 +39,19 @@
endif
else # NON SECURE_BOOT
ifeq ($(RCW),"")
- ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+ $(s)echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
else
# -a option appends the image for Chassis 3 devices in case of non secure boot
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
+ $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;
# Swapping of RCW is required for QSPi Chassis 2 devices
ifeq (${BOOT_MODE}, qspi)
ifeq ($(SWAP),1)
- ${Q}echo "Byteswapping RCW for QSPI"
+ $(s)echo "Byteswapping RCW for QSPI"
${BYTE_SWAP} ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl;
endif # SWAP
endif # BOOT_MODE
cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
endif
endif # SECURE_BOOT
-
-
-
diff --git a/tools/nxp/create_pbl/pbl_ch3.mk b/tools/nxp/create_pbl/pbl_ch3.mk
index 9283474..15129e4 100644
--- a/tools/nxp/create_pbl/pbl_ch3.mk
+++ b/tools/nxp/create_pbl/pbl_ch3.mk
@@ -21,13 +21,13 @@
ifeq ($(SECURE_BOOT),yes)
pbl: ${BUILD_PLAT}/bl2.bin
ifeq ($(RCW),"")
- ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+ $(s)echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
else
# Generate header for bl2.bin
- $(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
+ $(q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
# Compile create_pbl tool
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
+ $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
# Add Block Copy command for bl2.bin to RCW
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
@@ -39,14 +39,14 @@
-o ${BUILD_PLAT}/rcw_sec.pbl
# Sign and add "Load Security Header command to PBI commands
- $(Q)$(CST_DIR)/create_hdr_pbi --out ${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl --in ${BUILD_PLAT}/rcw_sec.pbl ${PBI_INPUT_FILE}
+ $(q)$(CST_DIR)/create_hdr_pbi --out ${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl --in ${BUILD_PLAT}/rcw_sec.pbl ${PBI_INPUT_FILE}
# Append the bl2_hdr to the RCW image
- @echo "${bl2_hdr_loc}"
+ $(s)echo "${bl2_hdr_loc}"
dd if=${BUILD_PLAT}/hdr_bl2 of=${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl bs=1K seek=${bl2_hdr_loc}
# Append the bl2.bin to the RCW image
- @echo "${bl2_loc}"
+ $(s)echo "${bl2_loc}"
dd if=${BUILD_PLAT}/bl2.bin of=${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl bs=1K seek=${bl2_loc}
rm ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl
@@ -54,16 +54,16 @@
endif
else #SECURE_BOOT
ifeq ($(RCW),"")
- ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+ $(s)echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
else
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
+ $(q)${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
# Add Block Copy command and populate boot loc ptrfor bl2.bin to RCW
${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
-o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};
# Append the bl2.bin to the RCW image
- @echo "bl2_loc is ${bl2_loc} KB"
+ $(s)echo "bl2_loc is ${bl2_loc} KB"
dd if=${BUILD_PLAT}/bl2.bin of=${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl bs=1K seek=${bl2_loc}
cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
diff --git a/tools/renesas/rcar_layout_create/makefile b/tools/renesas/rcar_layout_create/makefile
index 919c1de..8c2c054 100644
--- a/tools/renesas/rcar_layout_create/makefile
+++ b/tools/renesas/rcar_layout_create/makefile
@@ -6,6 +6,7 @@
toolchains := aarch64
+include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
###################################################
diff --git a/tools/renesas/rzg_layout_create/makefile b/tools/renesas/rzg_layout_create/makefile
index e1c242d..d2a54ea 100644
--- a/tools/renesas/rzg_layout_create/makefile
+++ b/tools/renesas/rzg_layout_create/makefile
@@ -6,6 +6,7 @@
toolchains := aarch64
+include ../../../make_helpers/common.mk
include ../../../make_helpers/toolchain.mk
###################################################
diff --git a/tools/sptool/Makefile b/tools/sptool/Makefile
index a913ce5..e336a0c 100644
--- a/tools/sptool/Makefile
+++ b/tools/sptool/Makefile
@@ -9,12 +9,12 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
SPTOOL ?= sptool${BIN_EXT}
PROJECT := $(notdir ${SPTOOL})
OBJECTS := sptool.o
-V ?= 0
override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99
@@ -24,12 +24,6 @@
HOSTCCFLAGS += -O2
endif
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
-
INCLUDE_PATHS := -I../../include/tools_share
.PHONY: all clean distclean
@@ -37,15 +31,15 @@
all: ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- ${Q}$(host-cc) ${OBJECTS} -o $@ ${LDLIBS}
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} -o $@ ${LDLIBS}
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
%.o: %.c Makefile
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
clean:
$(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS})
diff --git a/tools/stm32image/Makefile b/tools/stm32image/Makefile
index c75e941..2b34ef8 100644
--- a/tools/stm32image/Makefile
+++ b/tools/stm32image/Makefile
@@ -9,11 +9,11 @@
MAKE_HELPERS_DIRECTORY := ../../make_helpers/
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+include ${MAKE_HELPERS_DIRECTORY}common.mk
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
PROJECT := stm32image${BIN_EXT}
OBJECTS := stm32image.o
-V := 0
HOSTCCFLAGS := -Wall -Werror -pedantic -std=c99 -D_GNU_SOURCE
@@ -23,26 +23,20 @@
HOSTCCFLAGS += -O2
endif
-ifeq (${V},0)
- Q := @
-else
- Q :=
-endif
-
.PHONY: all clean distclean
all: ${PROJECT}
${PROJECT}: ${OBJECTS} Makefile
- @echo " HOSTLD $@"
- ${Q}$(host-cc) ${OBJECTS} -o $@
- @${ECHO_BLANK_LINE}
- @echo "Built $@ successfully"
- @${ECHO_BLANK_LINE}
+ $(s)echo " HOSTLD $@"
+ $(q)$(host-cc) ${OBJECTS} -o $@
+ $(s)echo
+ $(s)echo "Built $@ successfully"
+ $(s)echo
%.o: %.c Makefile
- @echo " HOSTCC $<"
- ${Q}$(host-cc) -c ${HOSTCCFLAGS} $< -o $@
+ $(s)echo " HOSTCC $<"
+ $(q)$(host-cc) -c ${HOSTCCFLAGS} $< -o $@
clean:
$(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS})