Merge pull request #895 from vwadekar/tegra186-platform-support-v5
Tegra186 platform support v5
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index fb57b2b..b8c0e03 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -48,193 +48,6 @@
static uint64_t video_mem_base;
static uint64_t video_mem_size_mb;
-/* array to hold stream_id override config register offsets */
-const static uint32_t streamid_overrides[] = {
- MC_STREAMID_OVERRIDE_CFG_PTCR,
- MC_STREAMID_OVERRIDE_CFG_AFIR,
- MC_STREAMID_OVERRIDE_CFG_HDAR,
- MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
- MC_STREAMID_OVERRIDE_CFG_SATAR,
- MC_STREAMID_OVERRIDE_CFG_MPCORER,
- MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
- MC_STREAMID_OVERRIDE_CFG_AFIW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_MPCOREW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_HDAW,
- MC_STREAMID_OVERRIDE_CFG_ISPRA,
- MC_STREAMID_OVERRIDE_CFG_ISPWA,
- MC_STREAMID_OVERRIDE_CFG_ISPWB,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRD,
- MC_STREAMID_OVERRIDE_CFG_TSECSWR,
- MC_STREAMID_OVERRIDE_CFG_GPUSRD,
- MC_STREAMID_OVERRIDE_CFG_GPUSWR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCW,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
- MC_STREAMID_OVERRIDE_CFG_VICSRD,
- MC_STREAMID_OVERRIDE_CFG_VICSWR,
- MC_STREAMID_OVERRIDE_CFG_VIW,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
- MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
- MC_STREAMID_OVERRIDE_CFG_APER,
- MC_STREAMID_OVERRIDE_CFG_APEW,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
- MC_STREAMID_OVERRIDE_CFG_SESRD,
- MC_STREAMID_OVERRIDE_CFG_SESWR,
- MC_STREAMID_OVERRIDE_CFG_ETRR,
- MC_STREAMID_OVERRIDE_CFG_ETRW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
- MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
- MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
- MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
- MC_STREAMID_OVERRIDE_CFG_AXISR,
- MC_STREAMID_OVERRIDE_CFG_AXISW,
- MC_STREAMID_OVERRIDE_CFG_EQOSR,
- MC_STREAMID_OVERRIDE_CFG_EQOSW,
- MC_STREAMID_OVERRIDE_CFG_UFSHCR,
- MC_STREAMID_OVERRIDE_CFG_UFSHCW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
- MC_STREAMID_OVERRIDE_CFG_BPMPR,
- MC_STREAMID_OVERRIDE_CFG_BPMPW,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
- MC_STREAMID_OVERRIDE_CFG_AONR,
- MC_STREAMID_OVERRIDE_CFG_AONW,
- MC_STREAMID_OVERRIDE_CFG_AONDMAR,
- MC_STREAMID_OVERRIDE_CFG_AONDMAW,
- MC_STREAMID_OVERRIDE_CFG_SCER,
- MC_STREAMID_OVERRIDE_CFG_SCEW,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_APEDMAR,
- MC_STREAMID_OVERRIDE_CFG_APEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
- MC_STREAMID_OVERRIDE_CFG_VICSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
-};
-
-/* array to hold the security configs for stream IDs */
-const static mc_streamid_security_cfg_t sec_cfgs[] = {
- mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
- mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
- mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
- mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-};
-
-const static mc_txn_override_cfg_t mc_override_cfgs[] = {
- mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
- mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
- mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
- mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
- mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
- mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
- mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
-};
-
static void tegra_memctrl_reconfig_mss_clients(void)
{
#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
@@ -248,8 +61,10 @@
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
- wdata_0 = MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
- MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
+ wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
+#if ENABLE_AFI_DEVICE
+ MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
+#endif
MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
@@ -296,7 +111,9 @@
* of control on overriding the memory type. So, remove TSA's
* memtype override.
*/
+#if ENABLE_AFI_DEVICE
mc_set_tsa_passthrough(AFIW);
+#endif
mc_set_tsa_passthrough(HDAW);
mc_set_tsa_passthrough(SATAW);
mc_set_tsa_passthrough(XUSB_HOSTW);
@@ -321,15 +138,19 @@
* whose AXI IDs we know and trust.
*/
+#if ENABLE_AFI_DEVICE
/* Match AFIW */
mc_set_forced_coherent_so_dev_cfg(AFIR);
+#endif
/*
* See bug 200131110 comment #35 - there are no normal requests
* and AWID for SO/DEV requests is hardcoded in RTL for a
* particular PCIE controller
*/
+#if ENABLE_AFI_DEVICE
mc_set_forced_coherent_so_dev_cfg(AFIW);
+#endif
mc_set_forced_coherent_cfg(HDAR);
mc_set_forced_coherent_cfg(HDAW);
mc_set_forced_coherent_cfg(SATAR);
@@ -374,7 +195,9 @@
* boot and strongly ordered MSS clients
*/
val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
+#if ENABLE_AFI_DEVICE
mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
+#endif
mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
@@ -411,7 +234,9 @@
* for boot and strongly ordered MSS clients
*/
val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL &
+#if ENABLE_AFI_DEVICE
mc_set_smmu_unordered_boot_so_mss(1, AFIW) &
+#endif
mc_set_smmu_unordered_boot_so_mss(1, HDAW) &
mc_set_smmu_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val);
@@ -486,27 +311,41 @@
void tegra_memctrl_setup(void)
{
uint32_t val;
- uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t);
- uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t);
- uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t);
+ const uint32_t *mc_streamid_override_regs;
+ uint32_t num_streamid_override_regs;
+ const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
+ uint32_t num_streamid_sec_cfgs;
+ const mc_txn_override_cfg_t *mc_txn_override_cfgs;
+ uint32_t num_txn_override_cfgs;
+ tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
int i;
INFO("Tegra Memory Controller (v2)\n");
+#if ENABLE_SMMU_DEVICE
/* Program the SMMU pagesize */
tegra_smmu_init();
+#endif
+ /* Get the settings from the platform */
+ assert(plat_mc_settings);
+ mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
+ num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
+ mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
+ num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
+ mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
+ num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/* Program all the Stream ID overrides */
- for (i = 0; i < num_overrides; i++)
- tegra_mc_streamid_write_32(streamid_overrides[i],
+ for (i = 0; i < num_streamid_override_regs; i++)
+ tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
MC_STREAM_ID_MAX);
/* Program the security config settings for all Stream IDs */
- for (i = 0; i < num_sec_cfgs; i++) {
- val = sec_cfgs[i].override_enable << 16 |
- sec_cfgs[i].override_client_inputs << 8 |
- sec_cfgs[i].override_client_ns_flag << 0;
- tegra_mc_streamid_write_32(sec_cfgs[i].offset, val);
+ for (i = 0; i < num_streamid_sec_cfgs; i++) {
+ val = mc_streamid_sec_cfgs[i].override_enable << 16 |
+ mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
+ mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
+ tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
}
/*
@@ -523,7 +362,7 @@
* mode, as it could be used to circumvent SMMU security checks.
*/
tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG,
- MC_SMMU_BYPASS_CONFIG_SETTINGS);
+ MC_SMMU_BYPASS_CONFIG_SETTINGS);
/*
* Re-configure MSS to allow ROC to deal with ordering of the
@@ -558,11 +397,11 @@
} else {
/* settings for rev. A02 */
- for (i = 0; i < num_txn_overrides; i++) {
- val = tegra_mc_read_32(mc_override_cfgs[i].offset);
+ for (i = 0; i < num_txn_override_cfgs; i++) {
+ val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
- tegra_mc_write_32(mc_override_cfgs[i].offset,
- val | mc_override_cfgs[i].cgid_tag);
+ tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
+ val | mc_txn_override_cfgs[i].cgid_tag);
}
}
@@ -659,13 +498,6 @@
tegra_mc_write_32(index, 0);
/*
- * Allow CPU read/write access to the aperture
- */
- tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1,
- TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT |
- TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT);
-
- /*
* Set the TZRAM base. TZRAM base must be 4k aligned, at least.
*/
assert(!(phys_base & 0xFFF));
diff --git a/plat/nvidia/tegra/soc/t186/drivers/smmu/smmu.c b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
similarity index 98%
rename from plat/nvidia/tegra/soc/t186/drivers/smmu/smmu.c
rename to plat/nvidia/tegra/common/drivers/smmu/smmu.c
index bca6f2e..6c7e94d 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/smmu/smmu.c
+++ b/plat/nvidia/tegra/common/drivers/smmu/smmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -50,7 +50,9 @@
#define mc_make_sid_security_cfg(name) \
{ \
- .reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_SECURITY_CFG_ ## name, \
+ .reg = TEGRA_MC_STREAMID_BASE + \
+ MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
+ MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000, \
}
diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c
index 0431d98..f4c5661 100644
--- a/plat/nvidia/tegra/common/tegra_topology.c
+++ b/plat/nvidia/tegra/common/tegra_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
#include <psci.h>
extern const unsigned char tegra_power_domain_tree_desc[];
+#pragma weak plat_core_pos_by_mpidr
/*******************************************************************************
* This function returns the Tegra default topology tree information.
@@ -52,23 +53,18 @@
{
unsigned int cluster_id, cpu_id;
- mpidr &= MPIDR_AFFINITY_MASK;
-
- if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
- return -1;
-
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
if (cluster_id >= PLATFORM_CLUSTER_COUNT)
- return -1;
+ return PSCI_E_NOT_PRESENT;
/*
* Validate cpu_id by checking whether it represents a CPU in
* one of the two clusters present on the platform.
*/
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
- return -1;
+ return PSCI_E_NOT_PRESENT;
return (cpu_id + (cluster_id * 4));
}
diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h
new file mode 100644
index 0000000..6cc845d
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/mce.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MCE_H__
+#define __MCE_H__
+
+#include <mmio.h>
+#include <tegra_def.h>
+
+/*******************************************************************************
+ * MCE commands
+ ******************************************************************************/
+typedef enum mce_cmd {
+ MCE_CMD_ENTER_CSTATE = 0,
+ MCE_CMD_UPDATE_CSTATE_INFO = 1,
+ MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
+ MCE_CMD_READ_CSTATE_STATS = 3,
+ MCE_CMD_WRITE_CSTATE_STATS = 4,
+ MCE_CMD_IS_SC7_ALLOWED = 5,
+ MCE_CMD_ONLINE_CORE = 6,
+ MCE_CMD_CC3_CTRL = 7,
+ MCE_CMD_ECHO_DATA = 8,
+ MCE_CMD_READ_VERSIONS = 9,
+ MCE_CMD_ENUM_FEATURES = 10,
+ MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
+ MCE_CMD_ENUM_READ_MCA = 12,
+ MCE_CMD_ENUM_WRITE_MCA = 13,
+ MCE_CMD_ROC_FLUSH_CACHE = 14,
+ MCE_CMD_ROC_CLEAN_CACHE = 15,
+ MCE_CMD_ENABLE_LATIC = 16,
+ MCE_CMD_UNCORE_PERFMON_REQ = 17,
+ MCE_CMD_MISC_CCPLEX = 18,
+ MCE_CMD_IS_CCX_ALLOWED = 0xFE,
+ MCE_CMD_MAX = 0xFF,
+} mce_cmd_t;
+
+#define MCE_CMD_MASK 0xFF
+
+/*******************************************************************************
+ * Timeout value used to powerdown a core
+ ******************************************************************************/
+#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
+
+/*******************************************************************************
+ * Struct to prepare UPDATE_CSTATE_INFO request
+ ******************************************************************************/
+typedef struct mce_cstate_info {
+ /* cluster cstate value */
+ uint32_t cluster;
+ /* ccplex cstate value */
+ uint32_t ccplex;
+ /* system cstate value */
+ uint32_t system;
+ /* force system state? */
+ uint8_t system_state_force;
+ /* wake mask value */
+ uint32_t wake_mask;
+ /* update the wake mask? */
+ uint8_t update_wake_mask;
+} mce_cstate_info_t;
+
+/* public interfaces */
+int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
+ uint64_t arg2);
+int mce_update_reset_vector(void);
+int mce_update_gsc_videomem(void);
+int mce_update_gsc_tzdram(void);
+int mce_update_gsc_tzram(void);
+__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
+void mce_update_cstate_info(mce_cstate_info_t *cstate);
+void mce_verify_firmware_version(void);
+
+#endif /* __MCE_H__ */
diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
index 559ea2c..201025d 100644
--- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h
+++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,10 @@
#include <tegra_def.h>
+#ifndef __ASSEMBLY__
+
+#include <sys/types.h>
+
/*******************************************************************************
* StreamID to indicate no SMMU translations (requests to be steered on the
* SMMU bypass path)
@@ -42,19 +46,18 @@
/*******************************************************************************
* Stream ID Override Config registers
******************************************************************************/
-#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x0
-#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x70
-#define MC_STREAMID_OVERRIDE_CFG_HDAR 0xA8
-#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0xB0
-#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0xE0
-#define MC_STREAMID_OVERRIDE_CFG_SATAR 0xF8
+#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000
+#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070
+#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8
+#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0
+#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8
#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138
#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158
#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188
-#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
+#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8
#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
-#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220
#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230
#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238
@@ -117,96 +120,11 @@
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518
/*******************************************************************************
- * Stream ID Security Config registers
+ * Macro to calculate Security cfg register addr from StreamID Override register
******************************************************************************/
-#define MC_STREAMID_SECURITY_CFG_PTCR 0x4
-#define MC_STREAMID_SECURITY_CFG_AFIR 0x74
-#define MC_STREAMID_SECURITY_CFG_HDAR 0xAC
-#define MC_STREAMID_SECURITY_CFG_HOST1XDMAR 0xB4
-#define MC_STREAMID_SECURITY_CFG_NVENCSRD 0xE4
-#define MC_STREAMID_SECURITY_CFG_SATAR 0xFC
-#define MC_STREAMID_SECURITY_CFG_HDAW 0x1AC
-#define MC_STREAMID_SECURITY_CFG_MPCORER 0x13C
-#define MC_STREAMID_SECURITY_CFG_NVENCSWR 0x15C
-#define MC_STREAMID_SECURITY_CFG_AFIW 0x18C
-#define MC_STREAMID_SECURITY_CFG_MPCOREW 0x1CC
-#define MC_STREAMID_SECURITY_CFG_SATAW 0x1EC
-#define MC_STREAMID_SECURITY_CFG_ISPRA 0x224
-#define MC_STREAMID_SECURITY_CFG_ISPWA 0x234
-#define MC_STREAMID_SECURITY_CFG_ISPWB 0x23C
-#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTR 0x254
-#define MC_STREAMID_SECURITY_CFG_XUSB_HOSTW 0x25C
-#define MC_STREAMID_SECURITY_CFG_XUSB_DEVR 0x264
-#define MC_STREAMID_SECURITY_CFG_XUSB_DEVW 0x26C
-#define MC_STREAMID_SECURITY_CFG_TSECSRD 0x2A4
-#define MC_STREAMID_SECURITY_CFG_TSECSWR 0x2AC
-#define MC_STREAMID_SECURITY_CFG_GPUSRD 0x2C4
-#define MC_STREAMID_SECURITY_CFG_GPUSWR 0x2CC
-#define MC_STREAMID_SECURITY_CFG_SDMMCRA 0x304
-#define MC_STREAMID_SECURITY_CFG_SDMMCRAA 0x30C
-#define MC_STREAMID_SECURITY_CFG_SDMMCR 0x314
-#define MC_STREAMID_SECURITY_CFG_SDMMCRAB 0x31C
-#define MC_STREAMID_SECURITY_CFG_SDMMCWA 0x324
-#define MC_STREAMID_SECURITY_CFG_SDMMCWAA 0x32C
-#define MC_STREAMID_SECURITY_CFG_SDMMCW 0x334
-#define MC_STREAMID_SECURITY_CFG_SDMMCWAB 0x33C
-#define MC_STREAMID_SECURITY_CFG_VICSRD 0x364
-#define MC_STREAMID_SECURITY_CFG_VICSWR 0x36C
-#define MC_STREAMID_SECURITY_CFG_VIW 0x394
-#define MC_STREAMID_SECURITY_CFG_NVDECSRD 0x3C4
-#define MC_STREAMID_SECURITY_CFG_NVDECSWR 0x3CC
-#define MC_STREAMID_SECURITY_CFG_APER 0x3D4
-#define MC_STREAMID_SECURITY_CFG_APEW 0x3DC
-#define MC_STREAMID_SECURITY_CFG_NVJPGSRD 0x3F4
-#define MC_STREAMID_SECURITY_CFG_NVJPGSWR 0x3FC
-#define MC_STREAMID_SECURITY_CFG_SESRD 0x404
-#define MC_STREAMID_SECURITY_CFG_SESWR 0x40C
-#define MC_STREAMID_SECURITY_CFG_ETRR 0x424
-#define MC_STREAMID_SECURITY_CFG_ETRW 0x42C
-#define MC_STREAMID_SECURITY_CFG_TSECSRDB 0x434
-#define MC_STREAMID_SECURITY_CFG_TSECSWRB 0x43C
-#define MC_STREAMID_SECURITY_CFG_GPUSRD2 0x444
-#define MC_STREAMID_SECURITY_CFG_GPUSWR2 0x44C
-#define MC_STREAMID_SECURITY_CFG_AXISR 0x464
-#define MC_STREAMID_SECURITY_CFG_AXISW 0x46C
-#define MC_STREAMID_SECURITY_CFG_EQOSR 0x474
-#define MC_STREAMID_SECURITY_CFG_EQOSW 0x47C
-#define MC_STREAMID_SECURITY_CFG_UFSHCR 0x484
-#define MC_STREAMID_SECURITY_CFG_UFSHCW 0x48C
-#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR 0x494
-#define MC_STREAMID_SECURITY_CFG_BPMPR 0x49C
-#define MC_STREAMID_SECURITY_CFG_BPMPW 0x4A4
-#define MC_STREAMID_SECURITY_CFG_BPMPDMAR 0x4AC
-#define MC_STREAMID_SECURITY_CFG_BPMPDMAW 0x4B4
-#define MC_STREAMID_SECURITY_CFG_AONR 0x4BC
-#define MC_STREAMID_SECURITY_CFG_AONW 0x4C4
-#define MC_STREAMID_SECURITY_CFG_AONDMAR 0x4CC
-#define MC_STREAMID_SECURITY_CFG_AONDMAW 0x4D4
-#define MC_STREAMID_SECURITY_CFG_SCER 0x4DC
-#define MC_STREAMID_SECURITY_CFG_SCEW 0x4E4
-#define MC_STREAMID_SECURITY_CFG_SCEDMAR 0x4EC
-#define MC_STREAMID_SECURITY_CFG_SCEDMAW 0x4F4
-#define MC_STREAMID_SECURITY_CFG_APEDMAR 0x4FC
-#define MC_STREAMID_SECURITY_CFG_APEDMAW 0x504
-#define MC_STREAMID_SECURITY_CFG_NVDISPLAYR1 0x50C
-#define MC_STREAMID_SECURITY_CFG_VICSRD1 0x514
-#define MC_STREAMID_SECURITY_CFG_NVDECSRD1 0x51C
+#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) (addr + sizeof(uint32_t))
/*******************************************************************************
- * Memory Controller SMMU Bypass config register
- ******************************************************************************/
-#define MC_SMMU_BYPASS_CONFIG 0x1820
-#define MC_SMMU_BYPASS_CTRL_MASK 0x3
-#define MC_SMMU_BYPASS_CTRL_SHIFT 0
-#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT)
-#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31)
-#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
- MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
-
-/*******************************************************************************
* Memory Controller transaction override config registers
******************************************************************************/
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
@@ -282,24 +200,6 @@
#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
-#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0)
-#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4)
-#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12)
-
-/*******************************************************************************
- * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
- * MC_TXN_OVERRIDE_CONFIG_{module} registers
- ******************************************************************************/
-#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0
-#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1
-#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2
-#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3
-#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3
-
-#ifndef __ASSEMBLY__
-
-#include <sys/types.h>
-
/*******************************************************************************
* Structure to hold the transaction override settings to use to override
* client inputs
@@ -342,17 +242,58 @@
#define CLIENT_INPUTS_NO_OVERRIDE 0
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
- { \
- .name = # off, \
- .offset = MC_STREAMID_SECURITY_CFG_ ## off, \
- .override_client_ns_flag = CLIENT_FLAG_ ## ns, \
- .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
- .override_enable = OVERRIDE_ ## access \
- }
+ { \
+ .name = # off, \
+ .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
+ MC_STREAMID_OVERRIDE_CFG_ ## off), \
+ .override_client_ns_flag = CLIENT_FLAG_ ## ns, \
+ .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
+ .override_enable = OVERRIDE_ ## access \
+ }
+
+/*******************************************************************************
+ * Structure to hold Memory Controller's Configuration settings
+ ******************************************************************************/
+typedef struct tegra_mc_settings {
+ const uint32_t *streamid_override_cfg;
+ uint32_t num_streamid_override_cfgs;
+ const mc_streamid_security_cfg_t *streamid_security_cfg;
+ uint32_t num_streamid_security_cfgs;
+ const mc_txn_override_cfg_t *txn_override_cfg;
+ uint32_t num_txn_override_cfgs;
+} tegra_mc_settings_t;
#endif /* __ASSEMBLY__ */
/*******************************************************************************
+ * Memory Controller SMMU Bypass config register
+ ******************************************************************************/
+#define MC_SMMU_BYPASS_CONFIG 0x1820
+#define MC_SMMU_BYPASS_CTRL_MASK 0x3
+#define MC_SMMU_BYPASS_CTRL_SHIFT 0
+#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT)
+#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31)
+#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
+ MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
+
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0)
+#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4)
+#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12)
+
+/*******************************************************************************
+ * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
+ * MC_TXN_OVERRIDE_CONFIG_{module} registers
+ ******************************************************************************/
+#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0
+#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1
+#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2
+#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3
+#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3
+
+/*******************************************************************************
* Memory Controller Reset Control registers
******************************************************************************/
#define MC_CLIENT_HOTRESET_CTRL0 0x200
@@ -548,6 +489,14 @@
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID | \
MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT); \
}
+
+/*******************************************************************************
+ * Handler to read memory configuration settings
+ *
+ * Implemented by SoCs under tegra/soc/txxx
+ ******************************************************************************/
+tegra_mc_settings_t *tegra_get_mc_settings(void);
+
#endif /* __ASSMEBLY__ */
#endif /* __MEMCTRLV2_H__ */
diff --git a/plat/nvidia/tegra/include/drivers/smmu.h b/plat/nvidia/tegra/include/drivers/smmu.h
index 0640846..a051b49 100644
--- a/plat/nvidia/tegra/include/drivers/smmu.h
+++ b/plat/nvidia/tegra/include/drivers/smmu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,6 +31,7 @@
#ifndef __SMMU_H
#define __SMMU_H
+#include <memctrl_v2.h>
#include <mmio.h>
#include <tegra_def.h>
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 6bac0d7..8a1dd3f 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -182,8 +182,6 @@
#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
-#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
-#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
@@ -249,6 +247,8 @@
* Tegra scratch registers constants
******************************************************************************/
#define TEGRA_SCRATCH_BASE 0x0C390000
+#define SECURE_SCRATCH_RSV1_LO 0x658
+#define SECURE_SCRATCH_RSV1_HI 0x65C
#define SECURE_SCRATCH_RSV6 0x680
#define SECURE_SCRATCH_RSV11_LO 0x6A8
#define SECURE_SCRATCH_RSV11_HI 0x6AC
@@ -259,11 +259,17 @@
#define SECURE_SCRATCH_RSV55_HI 0x80C
/*******************************************************************************
- * Tegra Memory Mapped Control Register Access Bus constants
+ * Tegra Memory Mapped Control Register Access constants
******************************************************************************/
#define TEGRA_MMCRAB_BASE 0x0E000000
/*******************************************************************************
+ * Tegra Memory Mapped Activity Monitor Register Access constants
+ ******************************************************************************/
+#define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000
+#define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000
+
+/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
#define TEGRA_SMMU_BASE 0x12000000
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
similarity index 85%
rename from plat/nvidia/tegra/soc/t186/drivers/include/mce.h
rename to plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
index 441a2c1..ac4be57 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/mce.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,60 +28,13 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __MCE_H__
-#define __MCE_H__
+#ifndef __MCE_PRIVATE_H__
+#define __MCE_PRIVATE_H__
#include <mmio.h>
#include <tegra_def.h>
/*******************************************************************************
- * MCE commands
- ******************************************************************************/
-typedef enum mce_cmd {
- MCE_CMD_ENTER_CSTATE = 0,
- MCE_CMD_UPDATE_CSTATE_INFO = 1,
- MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
- MCE_CMD_READ_CSTATE_STATS = 3,
- MCE_CMD_WRITE_CSTATE_STATS = 4,
- MCE_CMD_IS_SC7_ALLOWED = 5,
- MCE_CMD_ONLINE_CORE = 6,
- MCE_CMD_CC3_CTRL = 7,
- MCE_CMD_ECHO_DATA = 8,
- MCE_CMD_READ_VERSIONS = 9,
- MCE_CMD_ENUM_FEATURES = 10,
- MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
- MCE_CMD_ENUM_READ_MCA = 12,
- MCE_CMD_ENUM_WRITE_MCA = 13,
- MCE_CMD_ROC_FLUSH_CACHE = 14,
- MCE_CMD_ROC_CLEAN_CACHE = 15,
- MCE_CMD_ENABLE_LATIC = 16,
- MCE_CMD_UNCORE_PERFMON_REQ = 17,
- MCE_CMD_MISC_CCPLEX = 18,
- MCE_CMD_IS_CCX_ALLOWED = 0xFE,
- MCE_CMD_MAX = 0xFF,
-} mce_cmd_t;
-
-#define MCE_CMD_MASK 0xFF
-
-/*******************************************************************************
- * Struct to prepare UPDATE_CSTATE_INFO request
- ******************************************************************************/
-typedef struct mce_cstate_info {
- /* cluster cstate value */
- uint32_t cluster;
- /* ccplex cstate value */
- uint32_t ccplex;
- /* system cstate value */
- uint32_t system;
- /* force system state? */
- uint8_t system_state_force;
- /* wake mask value */
- uint32_t wake_mask;
- /* update the wake mask? */
- uint8_t update_wake_mask;
-} mce_cstate_info_t;
-
-/*******************************************************************************
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
@@ -127,11 +80,6 @@
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
/*******************************************************************************
- * Timeout value used to powerdown a core
- ******************************************************************************/
-#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
-
-/*******************************************************************************
* MCA command struct
******************************************************************************/
typedef union mca_cmd {
@@ -353,16 +301,6 @@
uint32_t value);
} arch_mce_ops_t;
-int mce_command_handler(mce_cmd_t cmd, uint64_t arg0, uint64_t arg1,
- uint64_t arg2);
-int mce_update_reset_vector(void);
-int mce_update_gsc_videomem(void);
-int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
-__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
-void mce_update_cstate_info(mce_cstate_info_t *cstate);
-void mce_verify_firmware_version(void);
-
/* declarations for ARI/NVG handler functions */
int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time);
int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex,
@@ -399,4 +337,4 @@
int nvg_online_core(uint32_t ari_base, uint32_t core);
int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
-#endif /* __MCE_H__ */
+#endif /* __MCE_PRIVATE_H__ */
diff --git a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
index cb48de6..ba4bb51 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
+++ b/plat/nvidia/tegra/soc/t186/drivers/include/t18x_ari.h
@@ -41,7 +41,7 @@
enum {
TEGRA_ARI_VERSION_MAJOR = 3,
- TEGRA_ARI_VERSION_MINOR = 0,
+ TEGRA_ARI_VERSION_MINOR = 1,
};
typedef enum {
@@ -87,6 +87,7 @@
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF = 0,
TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT = 1,
TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL = 2,
+ TEGRA_ARI_MISC_CCPLEX_EDBGREQ = 3,
} tegra_ari_misc_ccplex_index_t;
typedef enum {
@@ -226,6 +227,7 @@
TEGRA_ARI_MCA_RD_WR_CCE = 3,
TEGRA_ARI_MCA_RD_WR_CQX = 4,
TEGRA_ARI_MCA_RD_WR_CTU = 5,
+ TEGRA_ARI_MCA_RD_WR_JSR_MTS = 7,
TEGRA_ARI_MCA_RD_BANK_INFO = 0x0f,
TEGRA_ARI_MCA_RD_BANK_TEMPLATE = 0x10,
TEGRA_ARI_MCA_RD_WR_SECURE_ACCESS_REGISTER = 0x11,
@@ -393,6 +395,17 @@
TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_ASERR5_CTRL_EN_CTUPAR, 0, 0),
} tegra_ari_mca_aserr5_bitmasks_t;
+typedef enum {
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_SERR_ERR_CODE, 0, 15),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_AV, 58, 58),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_MV, 59, 59),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_EN, 60, 60),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_UC, 61, 61),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_OVF, 62, 62),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_STAT_VAL, 63, 63),
+ TEGRA_ARI_ENUM_MASK_LSB_MSB(TEGRA_ARI_MCA_SERR1_ADDR_TBD_INFO, 0, 63),
+} tegra_ari_mca_serr1_bitmasks_t;
+
#undef TEGRA_ARI_ENUM_MASK_LSB_MSB
typedef enum {
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
index 7597c12..7f711a7 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c
@@ -33,7 +33,7 @@
#include <debug.h>
#include <denver.h>
#include <mmio.h>
-#include <mce.h>
+#include <mce_private.h>
#include <sys/errno.h>
#include <t18x_ari.h>
@@ -483,7 +483,7 @@
* used to enable/disable coresight clock gating.
*/
- if ((index > TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) ||
+ if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) ||
((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) &&
(value > 1))) {
ERROR("%s: invalid parameters \n", __func__);
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 3a0edfb..0489f79 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -37,6 +37,7 @@
#include <debug.h>
#include <denver.h>
#include <mce.h>
+#include <mce_private.h>
#include <mmio.h>
#include <string.h>
#include <sys/errno.h>
@@ -491,7 +492,7 @@
uint32_t major, minor;
/*
- * MCE firmware is not running on simulation platforms.
+ * MCE firmware is not supported on simulation platforms.
*/
if (tegra_platform_is_emulation())
return;
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
index 25479a2..7ddafcb 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/nvg.c
@@ -33,7 +33,7 @@
#include <debug.h>
#include <denver.h>
#include <mmio.h>
-#include <mce.h>
+#include <mce_private.h>
#include <sys/errno.h>
#include <t18x_ari.h>
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
new file mode 100644
index 0000000..6fabaf2
--- /dev/null
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bl_common.h>
+#include <memctrl_v2.h>
+
+/*******************************************************************************
+ * Array to hold stream_id override config register offsets
+ ******************************************************************************/
+const static uint32_t tegra186_streamid_override_regs[] = {
+ MC_STREAMID_OVERRIDE_CFG_PTCR,
+ MC_STREAMID_OVERRIDE_CFG_AFIR,
+ MC_STREAMID_OVERRIDE_CFG_HDAR,
+ MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
+ MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
+ MC_STREAMID_OVERRIDE_CFG_SATAR,
+ MC_STREAMID_OVERRIDE_CFG_MPCORER,
+ MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
+ MC_STREAMID_OVERRIDE_CFG_AFIW,
+ MC_STREAMID_OVERRIDE_CFG_HDAW,
+ MC_STREAMID_OVERRIDE_CFG_MPCOREW,
+ MC_STREAMID_OVERRIDE_CFG_SATAW,
+ MC_STREAMID_OVERRIDE_CFG_ISPRA,
+ MC_STREAMID_OVERRIDE_CFG_ISPWA,
+ MC_STREAMID_OVERRIDE_CFG_ISPWB,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
+ MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
+ MC_STREAMID_OVERRIDE_CFG_TSECSRD,
+ MC_STREAMID_OVERRIDE_CFG_TSECSWR,
+ MC_STREAMID_OVERRIDE_CFG_GPUSRD,
+ MC_STREAMID_OVERRIDE_CFG_GPUSWR,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCR,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCW,
+ MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
+ MC_STREAMID_OVERRIDE_CFG_VICSRD,
+ MC_STREAMID_OVERRIDE_CFG_VICSWR,
+ MC_STREAMID_OVERRIDE_CFG_VIW,
+ MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
+ MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
+ MC_STREAMID_OVERRIDE_CFG_APER,
+ MC_STREAMID_OVERRIDE_CFG_APEW,
+ MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
+ MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
+ MC_STREAMID_OVERRIDE_CFG_SESRD,
+ MC_STREAMID_OVERRIDE_CFG_SESWR,
+ MC_STREAMID_OVERRIDE_CFG_ETRR,
+ MC_STREAMID_OVERRIDE_CFG_ETRW,
+ MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
+ MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
+ MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
+ MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
+ MC_STREAMID_OVERRIDE_CFG_AXISR,
+ MC_STREAMID_OVERRIDE_CFG_AXISW,
+ MC_STREAMID_OVERRIDE_CFG_EQOSR,
+ MC_STREAMID_OVERRIDE_CFG_EQOSW,
+ MC_STREAMID_OVERRIDE_CFG_UFSHCR,
+ MC_STREAMID_OVERRIDE_CFG_UFSHCW,
+ MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
+ MC_STREAMID_OVERRIDE_CFG_BPMPR,
+ MC_STREAMID_OVERRIDE_CFG_BPMPW,
+ MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
+ MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
+ MC_STREAMID_OVERRIDE_CFG_AONR,
+ MC_STREAMID_OVERRIDE_CFG_AONW,
+ MC_STREAMID_OVERRIDE_CFG_AONDMAR,
+ MC_STREAMID_OVERRIDE_CFG_AONDMAW,
+ MC_STREAMID_OVERRIDE_CFG_SCER,
+ MC_STREAMID_OVERRIDE_CFG_SCEW,
+ MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
+ MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
+ MC_STREAMID_OVERRIDE_CFG_APEDMAR,
+ MC_STREAMID_OVERRIDE_CFG_APEDMAW,
+ MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
+ MC_STREAMID_OVERRIDE_CFG_VICSRD1,
+ MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
+};
+
+/*******************************************************************************
+ * Array to hold the security configs for stream IDs
+ ******************************************************************************/
+const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
+ mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
+ mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
+ mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
+ mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
+};
+
+/*******************************************************************************
+ * Array to hold the transaction override configs
+ ******************************************************************************/
+const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
+ mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
+ mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
+};
+
+/*******************************************************************************
+ * Struct to hold the memory controller settings
+ ******************************************************************************/
+static tegra_mc_settings_t tegra186_mc_settings = {
+ .streamid_override_cfg = tegra186_streamid_override_regs,
+ .num_streamid_override_cfgs = ARRAY_SIZE(tegra186_streamid_override_regs),
+ .streamid_security_cfg = tegra186_streamid_sec_cfgs,
+ .num_streamid_security_cfgs = ARRAY_SIZE(tegra186_streamid_sec_cfgs),
+ .txn_override_cfg = tegra186_txn_override_cfgs,
+ .num_txn_override_cfgs = ARRAY_SIZE(tegra186_txn_override_cfgs)
+};
+
+/*******************************************************************************
+ * Handler to return the pointer to the memory controller's settings struct
+ ******************************************************************************/
+tegra_mc_settings_t *tegra_get_mc_settings(void)
+{
+ return &tegra186_mc_settings;
+}
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index a170b99..66a5999 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -260,7 +260,7 @@
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA186_STATE_ID_MASK;
- uint32_t val;
+ uint64_t val;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
/*
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index e848eab..13f867e 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -50,6 +50,13 @@
extern uint64_t tegra_enable_l2_ecc_parity_prot;
/*******************************************************************************
+ * Tegra186 CPU numbers in cluster #0
+ *******************************************************************************
+ */
+#define TEGRA186_CLUSTER0_CORE2 2
+#define TEGRA186_CLUSTER0_CORE3 3
+
+/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
* the number of power domains at the highest power level.
@@ -102,8 +109,12 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */
+ MT_DEVICE | MT_RW | MT_SECURE),
+#if ENABLE_SMMU_DEVICE
MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
+#endif
{0}
};
@@ -252,3 +263,40 @@
return (plat_params_from_bl2_t *)(uintptr_t)val;
}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id, pos;
+
+ cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ /*
+ * Validate cluster_id by checking whether it represents
+ * one of the two clusters present on the platform.
+ */
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT)
+ return PSCI_E_NOT_PRESENT;
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in
+ * one of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
+ return PSCI_E_NOT_PRESENT;
+
+ /* calculate the core position */
+ pos = cpu_id + (cluster_id << 2);
+
+ /* check for non-existent CPUs */
+ if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3)
+ return PSCI_E_NOT_PRESENT;
+
+ return pos;
+}
diff --git a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
index 31e903e..fa39749 100644
--- a/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t186/plat_sip_calls.c
@@ -34,6 +34,7 @@
#include <bl_common.h>
#include <context_mgmt.h>
#include <debug.h>
+#include <denver.h>
#include <errno.h>
#include <mce.h>
#include <memctrl.h>
@@ -44,10 +45,15 @@
extern uint32_t tegra186_system_powerdn_state;
/*******************************************************************************
+ * Offset to read the ref_clk counter value
+ ******************************************************************************/
+#define REF_CLK_OFFSET 4
+
+/*******************************************************************************
* Tegra186 SiP SMCs
******************************************************************************/
-#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0x82FFFE01
+#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0x82FFFE02
#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0x82FFFF00
#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0x82FFFF01
#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0x82FFFF02
@@ -81,6 +87,8 @@
uint64_t flags)
{
int mce_ret;
+ int impl, cpu;
+ uint32_t base, core_clk_ctr, ref_clk_ctr;
switch (smc_fid) {
@@ -143,6 +151,36 @@
return 0;
+ /*
+ * This function ID reads the Activity monitor's core/ref clock
+ * counter values for a core/cluster.
+ *
+ * x1 = MPIDR of the target core
+ * x2 = MIDR of the target core
+ */
+ case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS:
+
+ cpu = (uint32_t)x1 & MPIDR_CPU_MASK;
+ impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
+
+ /* sanity check target CPU number */
+ if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER)
+ return -EINVAL;
+
+ /* get the base address for the current CPU */
+ base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE :
+ TEGRA_ARM_ACTMON_CTR_BASE;
+
+ /* read the clock counter values */
+ core_clk_ctr = mmio_read_32(base + (8 * cpu));
+ ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET);
+
+ /* return the counter values as two different parameters */
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, core_clk_ctr);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, ref_clk_ctr);
+
+ return 0;
+
default:
break;
}
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index b62d47d..97e3463 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
@@ -29,6 +29,9 @@
#
# platform configs
+ENABLE_AFI_DEVICE := 1
+$(eval $(call add_define,ENABLE_AFI_DEVICE))
+
ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
@@ -38,6 +41,9 @@
ENABLE_CHIP_VERIFICATION_HARNESS := 0
$(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
+ENABLE_SMMU_DEVICE := 1
+$(eval $(call add_define,ENABLE_SMMU_DEVICE))
+
RESET_TO_BL31 := 1
PROGRAMMABLE_RESET_ADDRESS := 1
@@ -54,10 +60,10 @@
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
-MAX_XLAT_TABLES := 20
+MAX_XLAT_TABLES := 24
$(eval $(call add_define,MAX_XLAT_TABLES))
-MAX_MMAP_REGIONS := 20
+MAX_MMAP_REGIONS := 24
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
@@ -66,13 +72,15 @@
BL31_SOURCES += lib/cpus/aarch64/denver.S \
lib/cpus/aarch64/cortex_a57.S \
${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
+ ${COMMON_DIR}/drivers/smmu/smmu.c \
${SOC_DIR}/drivers/mce/mce.c \
${SOC_DIR}/drivers/mce/ari.c \
${SOC_DIR}/drivers/mce/nvg.c \
${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
- ${SOC_DIR}/drivers/smmu/smmu.c \
+ ${SOC_DIR}/plat_memctrl.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c \
${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_trampoline.S
+