Move include and source files to logical locations
Move almost all system include files to a logical sub-directory
under ./include. The only remaining system include directories
not under ./include are specific to the platform. Move the
corresponding source files to match the include directory
structure.
Also remove pm.h as it is no longer used.
Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
diff --git a/include/bl1.h b/include/bl1/bl1.h
similarity index 100%
rename from include/bl1.h
rename to include/bl1/bl1.h
diff --git a/include/bl2.h b/include/bl2/bl2.h
similarity index 100%
rename from include/bl2.h
rename to include/bl2/bl2.h
diff --git a/include/bl31.h b/include/bl31/bl31.h
similarity index 100%
rename from include/bl31.h
rename to include/bl31/bl31.h
diff --git a/include/cm_macros.S b/include/bl31/cm_macros.S
similarity index 100%
rename from include/cm_macros.S
rename to include/bl31/cm_macros.S
diff --git a/include/context.h b/include/bl31/context.h
similarity index 100%
rename from include/context.h
rename to include/bl31/context.h
diff --git a/include/context_mgmt.h b/include/bl31/context_mgmt.h
similarity index 100%
rename from include/context_mgmt.h
rename to include/bl31/context_mgmt.h
diff --git a/include/runtime_svc.h b/include/bl31/runtime_svc.h
similarity index 100%
rename from include/runtime_svc.h
rename to include/bl31/runtime_svc.h
diff --git a/include/psci.h b/include/bl31/services/psci.h
similarity index 100%
rename from include/psci.h
rename to include/bl31/services/psci.h
diff --git a/include/std_svc.h b/include/bl31/services/std_svc.h
similarity index 100%
rename from include/std_svc.h
rename to include/bl31/services/std_svc.h
diff --git a/include/bl32.h b/include/bl32/bl32.h
similarity index 100%
rename from include/bl32.h
rename to include/bl32/bl32.h
diff --git a/include/tsp.h b/include/bl32/payloads/tsp.h
similarity index 100%
rename from include/tsp.h
rename to include/bl32/payloads/tsp.h
diff --git a/include/asm_macros.S b/include/common/asm_macros.S
similarity index 100%
rename from include/asm_macros.S
rename to include/common/asm_macros.S
diff --git a/include/bl_common.h b/include/common/bl_common.h
similarity index 93%
rename from include/bl_common.h
rename to include/common/bl_common.h
index ba6dc11..a751d78 100644
--- a/include/bl_common.h
+++ b/include/common/bl_common.h
@@ -127,19 +127,22 @@
extern void __dead2 change_el(el_change_info *);
extern unsigned long make_spsr(unsigned long, unsigned long, unsigned long);
extern void init_bl2_mem_layout(meminfo *,
- meminfo *,
- unsigned int,
- unsigned long) __attribute__((weak));
+ meminfo *,
+ unsigned int,
+ unsigned long) __attribute__((weak));
extern void init_bl31_mem_layout(const meminfo *,
- meminfo *,
- unsigned int) __attribute__((weak));
+ meminfo *,
+ unsigned int) __attribute__((weak));
extern unsigned long image_size(const char *);
-extern unsigned long load_image(meminfo *, const char *, unsigned int, unsigned long);
+extern unsigned long load_image(meminfo *,
+ const char *,
+ unsigned int,
+ unsigned long);
extern void __dead2 run_image(unsigned long entrypoint,
- unsigned long spsr,
- unsigned long security_state,
- void *first_arg,
- void *second_arg);
+ unsigned long spsr,
+ unsigned long security_state,
+ void *first_arg,
+ void *second_arg);
extern unsigned long *get_el_change_mem_ptr(void);
extern const char build_message[];
diff --git a/include/debug.h b/include/common/debug.h
similarity index 100%
rename from include/debug.h
rename to include/common/debug.h
diff --git a/include/firmware_image_package.h b/include/common/firmware_image_package.h
similarity index 100%
rename from include/firmware_image_package.h
rename to include/common/firmware_image_package.h
diff --git a/include/drivers/arm/cci400.h b/include/drivers/arm/cci400.h
new file mode 100644
index 0000000..3921675
--- /dev/null
+++ b/include/drivers/arm/cci400.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CCI_400_H__
+#define __CCI_400_H__
+
+/* Slave interface offsets from PERIPHBASE */
+#define SLAVE_IFACE4_OFFSET 0x5000
+#define SLAVE_IFACE3_OFFSET 0x4000
+#define SLAVE_IFACE2_OFFSET 0x3000
+#define SLAVE_IFACE1_OFFSET 0x2000
+#define SLAVE_IFACE0_OFFSET 0x1000
+#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + (0x1000 * index)
+
+/* Control and ID register offsets */
+#define CTRL_OVERRIDE_REG 0x0
+#define SPEC_CTRL_REG 0x4
+#define SECURE_ACCESS_REG 0x8
+#define STATUS_REG 0xc
+#define IMPRECISE_ERR_REG 0x10
+#define PERFMON_CTRL_REG 0x100
+
+/* Slave interface register offsets */
+#define SNOOP_CTRL_REG 0x0
+#define SH_OVERRIDE_REG 0x4
+#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100
+#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104
+#define QOS_CTRL_REG 0x10c
+#define MAX_OT_REG 0x110
+#define TARGET_LATENCY_REG 0x130
+#define LATENCY_REGULATION_REG 0x134
+#define QOS_RANGE_REG 0x138
+
+/* Snoop Control register bit definitions */
+#define DVM_EN_BIT (1 << 1)
+#define SNOOP_EN_BIT (1 << 0)
+
+/* Status register bit definitions */
+#define CHANGE_PENDING_BIT (1 << 0)
+
+/* Function declarations */
+extern void cci_enable_coherency(unsigned long mpidr);
+extern void cci_disable_coherency(unsigned long mpidr);
+
+#endif /* __CCI_400_H__ */
diff --git a/include/drivers/arm/gic.h b/include/drivers/arm/gic.h
new file mode 100644
index 0000000..3266043
--- /dev/null
+++ b/include/drivers/arm/gic.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+#define MAX_SPIS 480
+#define MAX_PPIS 14
+#define MAX_SGIS 16
+
+#define GRP0 0
+#define GRP1 1
+#define GIC_PRI_MASK 0xff
+#define GIC_HIGHEST_SEC_PRIORITY 0
+#define GIC_LOWEST_SEC_PRIORITY 127
+#define GIC_HIGHEST_NS_PRIORITY 128
+#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */
+
+#define ENABLE_GRP0 (1 << 0)
+#define ENABLE_GRP1 (1 << 1)
+
+/* Distributor interface definitions */
+#define GICD_CTLR 0x0
+#define GICD_TYPER 0x4
+#define GICD_IGROUPR 0x80
+#define GICD_ISENABLER 0x100
+#define GICD_ICENABLER 0x180
+#define GICD_ISPENDR 0x200
+#define GICD_ICPENDR 0x280
+#define GICD_ISACTIVER 0x300
+#define GICD_ICACTIVER 0x380
+#define GICD_IPRIORITYR 0x400
+#define GICD_ITARGETSR 0x800
+#define GICD_ICFGR 0xC00
+#define GICD_SGIR 0xF00
+#define GICD_CPENDSGIR 0xF10
+#define GICD_SPENDSGIR 0xF20
+
+#define IGROUPR_SHIFT 5
+#define ISENABLER_SHIFT 5
+#define ICENABLER_SHIFT ISENABLER_SHIFT
+#define ISPENDR_SHIFT 5
+#define ICPENDR_SHIFT ISPENDR_SHIFT
+#define ISACTIVER_SHIFT 5
+#define ICACTIVER_SHIFT ISACTIVER_SHIFT
+#define IPRIORITYR_SHIFT 2
+#define ITARGETSR_SHIFT 2
+#define ICFGR_SHIFT 4
+#define CPENDSGIR_SHIFT 2
+#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
+
+/* GICD_TYPER bit definitions */
+#define IT_LINES_NO_MASK 0x1f
+
+/* Physical CPU Interface registers */
+#define GICC_CTLR 0x0
+#define GICC_PMR 0x4
+#define GICC_BPR 0x8
+#define GICC_IAR 0xC
+#define GICC_EOIR 0x10
+#define GICC_RPR 0x14
+#define GICC_HPPIR 0x18
+#define GICC_IIDR 0xFC
+#define GICC_DIR 0x1000
+#define GICC_PRIODROP GICC_EOIR
+
+/* GICC_CTLR bit definitions */
+#define EOI_MODE_NS (1 << 10)
+#define EOI_MODE_S (1 << 9)
+#define IRQ_BYP_DIS_GRP1 (1 << 8)
+#define FIQ_BYP_DIS_GRP1 (1 << 7)
+#define IRQ_BYP_DIS_GRP0 (1 << 6)
+#define FIQ_BYP_DIS_GRP0 (1 << 5)
+#define CBPR (1 << 4)
+#define FIQ_EN (1 << 3)
+#define ACK_CTL (1 << 2)
+
+/* GICC_IIDR bit masks and shifts */
+#define GICC_IIDR_PID_SHIFT 20
+#define GICC_IIDR_ARCH_SHIFT 16
+#define GICC_IIDR_REV_SHIFT 12
+#define GICC_IIDR_IMP_SHIFT 0
+
+#define GICC_IIDR_PID_MASK 0xfff
+#define GICC_IIDR_ARCH_MASK 0xf
+#define GICC_IIDR_REV_MASK 0xf
+#define GICC_IIDR_IMP_MASK 0xfff
+
+/* HYP view virtual CPU Interface registers */
+#define GICH_CTL 0x0
+#define GICH_VTR 0x4
+#define GICH_ELRSR0 0x30
+#define GICH_ELRSR1 0x34
+#define GICH_APR0 0xF0
+#define GICH_LR_BASE 0x100
+
+/* Virtual CPU Interface registers */
+#define GICV_CTL 0x0
+#define GICV_PRIMASK 0x4
+#define GICV_BP 0x8
+#define GICV_INTACK 0xC
+#define GICV_EOI 0x10
+#define GICV_RUNNINGPRI 0x14
+#define GICV_HIGHESTPEND 0x18
+#define GICV_DEACTIVATE 0x1000
+
+/* GICv3 Re-distributor interface registers & shifts */
+#define GICR_PCPUBASE_SHIFT 0x11
+#define GICR_TYPER 0x08
+#define GICR_WAKER 0x14
+
+/* GICR_WAKER bit definitions */
+#define WAKER_CA (1UL << 2)
+#define WAKER_PS (1UL << 1)
+
+/* GICR_TYPER bit definitions */
+#define GICR_TYPER_AFF_SHIFT 32
+#define GICR_TYPER_AFF_MASK 0xffffffff
+#define GICR_TYPER_LAST (1UL << 4)
+
+/* GICv3 ICC_SRE register bit definitions*/
+#define ICC_SRE_EN (1UL << 3)
+#define ICC_SRE_SRE (1UL << 0)
+
+#ifndef __ASSEMBLY__
+
+#include <gic_v2.h>
+#include <gic_v3.h>
+
+/*******************************************************************************
+ * Function prototypes
+ ******************************************************************************/
+
+extern unsigned int gicd_read_igroupr(unsigned int, unsigned int);
+extern unsigned int gicd_read_isenabler(unsigned int, unsigned int);
+extern unsigned int gicd_read_icenabler(unsigned int, unsigned int);
+extern unsigned int gicd_read_ispendr(unsigned int, unsigned int);
+extern unsigned int gicd_read_icpendr(unsigned int, unsigned int);
+extern unsigned int gicd_read_isactiver(unsigned int, unsigned int);
+extern unsigned int gicd_read_icactiver(unsigned int, unsigned int);
+extern unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
+extern unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
+extern unsigned int gicd_read_icfgr(unsigned int, unsigned int);
+extern unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
+extern unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
+extern void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
+extern void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
+extern unsigned int gicd_get_igroupr(unsigned int, unsigned int);
+extern void gicd_set_igroupr(unsigned int, unsigned int);
+extern void gicd_clr_igroupr(unsigned int, unsigned int);
+extern void gicd_set_isenabler(unsigned int, unsigned int);
+extern void gicd_set_icenabler(unsigned int, unsigned int);
+extern void gicd_set_ispendr(unsigned int, unsigned int);
+extern void gicd_set_icpendr(unsigned int, unsigned int);
+extern void gicd_set_isactiver(unsigned int, unsigned int);
+extern void gicd_set_icactiver(unsigned int, unsigned int);
+extern void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
+extern void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
+
+/* GICv3 functions */
+
+extern unsigned int read_icc_sre_el1(void);
+extern unsigned int read_icc_sre_el2(void);
+extern unsigned int read_icc_sre_el3(void);
+extern void write_icc_sre_el1(unsigned int);
+extern void write_icc_sre_el2(unsigned int);
+extern void write_icc_sre_el3(unsigned int);
+extern void write_icc_pmr_el1(unsigned int);
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __GIC_H__ */
+
diff --git a/include/drivers/arm/gic_v2.h b/include/drivers/arm/gic_v2.h
new file mode 100644
index 0000000..30bd4fc
--- /dev/null
+++ b/include/drivers/arm/gic_v2.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __GIC_V2_H__
+#define __GIC_V2_H__
+
+#include <mmio.h>
+
+/*******************************************************************************
+ * GIC Distributor interface accessors for reading entire registers
+ ******************************************************************************/
+
+static inline unsigned int gicd_read_ctlr(unsigned int base)
+{
+ return mmio_read_32(base + GICD_CTLR);
+}
+
+static inline unsigned int gicd_read_typer(unsigned int base)
+{
+ return mmio_read_32(base + GICD_TYPER);
+}
+
+static inline unsigned int gicd_read_sgir(unsigned int base)
+{
+ return mmio_read_32(base + GICD_SGIR);
+}
+
+
+/*******************************************************************************
+ * GIC Distributor interface accessors for writing entire registers
+ ******************************************************************************/
+
+static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICD_CTLR, val);
+}
+
+static inline void gicd_write_sgir(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICD_SGIR, val);
+}
+
+
+/*******************************************************************************
+ * GIC CPU interface accessors for reading entire registers
+ ******************************************************************************/
+
+static inline unsigned int gicc_read_ctlr(unsigned int base)
+{
+ return mmio_read_32(base + GICC_CTLR);
+}
+
+static inline unsigned int gicc_read_pmr(unsigned int base)
+{
+ return mmio_read_32(base + GICC_PMR);
+}
+
+static inline unsigned int gicc_read_BPR(unsigned int base)
+{
+ return mmio_read_32(base + GICC_BPR);
+}
+
+static inline unsigned int gicc_read_IAR(unsigned int base)
+{
+ return mmio_read_32(base + GICC_IAR);
+}
+
+static inline unsigned int gicc_read_EOIR(unsigned int base)
+{
+ return mmio_read_32(base + GICC_EOIR);
+}
+
+static inline unsigned int gicc_read_hppir(unsigned int base)
+{
+ return mmio_read_32(base + GICC_HPPIR);
+}
+
+static inline unsigned int gicc_read_dir(unsigned int base)
+{
+ return mmio_read_32(base + GICC_DIR);
+}
+
+static inline unsigned int gicc_read_iidr(unsigned int base)
+{
+ return mmio_read_32(base + GICC_IIDR);
+}
+
+
+/*******************************************************************************
+ * GIC CPU interface accessors for writing entire registers
+ ******************************************************************************/
+
+static inline void gicc_write_ctlr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_CTLR, val);
+}
+
+static inline void gicc_write_pmr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_PMR, val);
+}
+
+static inline void gicc_write_BPR(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_BPR, val);
+}
+
+
+static inline void gicc_write_IAR(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_IAR, val);
+}
+
+static inline void gicc_write_EOIR(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_EOIR, val);
+}
+
+static inline void gicc_write_hppir(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_HPPIR, val);
+}
+
+static inline void gicc_write_dir(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + GICC_DIR, val);
+}
+
+#endif /* __GIC_V2_H__ */
diff --git a/include/bakery_lock.h b/include/drivers/arm/gic_v3.h
similarity index 63%
copy from include/bakery_lock.h
copy to include/drivers/arm/gic_v3.h
index da5d9dd..df7e7fd 100644
--- a/include/bakery_lock.h
+++ b/include/drivers/arm/gic_v3.h
@@ -28,26 +28,38 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BAKERY_LOCK_H__
-#define __BAKERY_LOCK_H__
+#ifndef __GIC_V3_H__
+#define __GIC_V3_H__
-#include <platform.h>
+#include <stdint.h>
+#include <mmio.h>
-#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
+#define GICV3_AFFLVL_MASK 0xff
+#define GICV3_AFF0_SHIFT 0
+#define GICV3_AFF1_SHIFT 8
+#define GICV3_AFF2_SHIFT 16
+#define GICV3_AFF3_SHIFT 24
+#define GICV3_AFFINITY_MASK 0xffffffff
-#ifndef __ASSEMBLY__
-typedef struct {
- int owner;
- volatile char entering[BAKERY_LOCK_MAX_CPUS];
- volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
-} bakery_lock;
+uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr);
-#define NO_OWNER (-1)
+/*******************************************************************************
+ * GIC Redistributor interface accessors
+ ******************************************************************************/
+static inline uint32_t gicr_read_waker(uintptr_t base)
+{
+ return mmio_read_32(base + GICR_WAKER);
+}
-void bakery_lock_init(bakery_lock* bakery);
-void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery);
-void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery);
-int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery);
-#endif /*__ASSEMBLY__*/
+static inline void gicr_write_waker(uintptr_t base, uint32_t val)
+{
+ mmio_write_32(base + GICR_WAKER, val);
+}
+
+static inline uint64_t gicr_read_typer(uintptr_t base)
+{
+ return mmio_read_64(base + GICR_TYPER);
+}
+
-#endif /* __BAKERY_LOCK_H__ */
+#endif /* __GIC_V3_H__ */
diff --git a/include/drivers/arm/pl011.h b/include/drivers/arm/pl011.h
new file mode 100644
index 0000000..5ad2fc7
--- /dev/null
+++ b/include/drivers/arm/pl011.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PL011_H__
+#define __PL011_H__
+
+/* PL011 Registers */
+#define UARTDR 0x000
+#define UARTRSR 0x004
+#define UARTECR 0x004
+#define UARTFR 0x018
+#define UARTILPR 0x020
+#define UARTIBRD 0x024
+#define UARTFBRD 0x028
+#define UARTLCR_H 0x02C
+#define UARTCR 0x030
+#define UARTIFLS 0x034
+#define UARTIMSC 0x038
+#define UARTRIS 0x03C
+#define UARTMIS 0x040
+#define UARTICR 0x044
+#define UARTDMACR 0x048
+
+/* Data status bits */
+#define UART_DATA_ERROR_MASK 0x0F00
+
+/* Status reg bits */
+#define UART_STATUS_ERROR_MASK 0x0F
+
+/* Flag reg bits */
+#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */
+#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */
+#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */
+#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */
+#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */
+#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */
+#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */
+#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */
+#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */
+
+/* Control reg bits */
+#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */
+#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */
+#define PL011_UARTCR_RTS (1 << 11) /* Request to send */
+#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */
+#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */
+#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */
+#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */
+#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */
+
+#if !defined(PL011_BASE)
+#error "The PL011_BASE macro must be defined."
+#endif
+
+#if !defined(PL011_BAUDRATE)
+#define PL011_BAUDRATE 115200
+#endif
+
+#if !defined(PL011_CLK_IN_HZ)
+#define PL011_CLK_IN_HZ 24000000
+#endif
+
+#if !defined(PL011_LINE_CONTROL)
+/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */
+#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8)
+#endif
+
+/* Line Control Register Bits */
+#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */
+#define PL011_UARTLCR_H_WLEN_8 (3 << 5)
+#define PL011_UARTLCR_H_WLEN_7 (2 << 5)
+#define PL011_UARTLCR_H_WLEN_6 (1 << 5)
+#define PL011_UARTLCR_H_WLEN_5 (0 << 5)
+#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */
+#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */
+#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */
+#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */
+#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */
+
+/*******************************************************************************
+ * Pl011 CPU interface accessors for writing registers
+ ******************************************************************************/
+
+static inline void pl011_write_ibrd(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + UARTIBRD, val);
+}
+
+static inline void pl011_write_fbrd(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + UARTFBRD, val);
+}
+
+static inline void pl011_write_lcr_h(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + UARTLCR_H, val);
+}
+
+static inline void pl011_write_ecr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + UARTECR, val);
+}
+
+static inline void pl011_write_cr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + UARTCR, val);
+}
+
+static inline void pl011_write_dr(unsigned int base, unsigned int val)
+{
+ mmio_write_32(base + UARTDR, val);
+}
+
+/*******************************************************************************
+ * Pl011 CPU interface accessors for reading registers
+ ******************************************************************************/
+
+static inline unsigned int pl011_read_fr(unsigned int base)
+{
+ return mmio_read_32(base + UARTFR);
+}
+
+static inline unsigned int pl011_read_dr(unsigned int base)
+{
+ return mmio_read_32(base + UARTDR);
+}
+
+/*******************************************************************************
+ * Function prototypes
+ ******************************************************************************/
+
+void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate);
+
+#endif /* __PL011_H__ */
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
new file mode 100644
index 0000000..7eaafd2
--- /dev/null
+++ b/include/drivers/arm/tzc400.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __TZC400_H__
+#define __TZC400_H__
+
+#include <stdint.h>
+
+#define BUILD_CONFIG_OFF 0x000
+#define ACTION_OFF 0x004
+#define GATE_KEEPER_OFF 0x008
+#define SPECULATION_CTRL_OFF 0x00c
+#define INT_STATUS 0x010
+#define INT_CLEAR 0x014
+
+#define FAIL_ADDRESS_LOW_OFF 0x020
+#define FAIL_ADDRESS_HIGH_OFF 0x024
+#define FAIL_CONTROL_OFF 0x028
+#define FAIL_ID 0x02c
+
+#define REGION_BASE_LOW_OFF 0x100
+#define REGION_BASE_HIGH_OFF 0x104
+#define REGION_TOP_LOW_OFF 0x108
+#define REGION_TOP_HIGH_OFF 0x10c
+#define REGION_ATTRIBUTES_OFF 0x110
+#define REGION_ID_ACCESS_OFF 0x114
+#define REGION_NUM_OFF(region) (0x20 * region)
+
+/* ID Registers */
+#define PID0_OFF 0xfe0
+#define PID1_OFF 0xfe4
+#define PID2_OFF 0xfe8
+#define PID3_OFF 0xfec
+#define PID4_OFF 0xfd0
+#define PID5_OFF 0xfd4
+#define PID6_OFF 0xfd8
+#define PID7_OFF 0xfdc
+#define CID0_OFF 0xff0
+#define CID1_OFF 0xff4
+#define CID2_OFF 0xff8
+#define CID3_OFF 0xffc
+
+#define BUILD_CONFIG_NF_SHIFT 24
+#define BUILD_CONFIG_NF_MASK 0x3
+#define BUILD_CONFIG_AW_SHIFT 8
+#define BUILD_CONFIG_AW_MASK 0x3f
+#define BUILD_CONFIG_NR_SHIFT 0
+#define BUILD_CONFIG_NR_MASK 0x1f
+
+/* Not describing the case where regions 1 to 8 overlap */
+#define ACTION_RV_SHIFT 0
+#define ACTION_RV_MASK 0x3
+#define ACTION_RV_LOWOK 0x0
+#define ACTION_RV_LOWERR 0x1
+#define ACTION_RV_HIGHOK 0x2
+#define ACTION_RV_HIGHERR 0x3
+
+/*
+ * Number of gate keepers is implementation defined. But we know the max for
+ * this device is 4. Get implementation details from BUILD_CONFIG.
+ */
+#define GATE_KEEPER_OS_SHIFT 16
+#define GATE_KEEPER_OS_MASK 0xf
+#define GATE_KEEPER_OR_SHIFT 0
+#define GATE_KEEPER_OR_MASK 0xf
+
+/* Speculation is enabled by default. */
+#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1)
+#define SPECULATION_CTRL_READ_DISABLE (1 << 0)
+
+/* Max number of filters allowed is 4. */
+#define INT_STATUS_OVERLAP_SHIFT 16
+#define INT_STATUS_OVERLAP_MASK 0xf
+#define INT_STATUS_OVERRUN_SHIFT 8
+#define INT_STATUS_OVERRUN_MASK 0xf
+#define INT_STATUS_STATUS_SHIFT 0
+#define INT_STATUS_STATUS_MASK 0xf
+
+#define INT_CLEAR_CLEAR_SHIFT 0
+#define INT_CLEAR_CLEAR_MASK 0xf
+
+#define FAIL_CONTROL_DIR_SHIFT (1 << 24)
+#define FAIL_CONTROL_DIR_READ 0x0
+#define FAIL_CONTROL_DIR_WRITE 0x1
+#define FAIL_CONTROL_NS_SHIFT (1 << 21)
+#define FAIL_CONTROL_NS_SECURE 0x0
+#define FAIL_CONTROL_NS_NONSECURE 0x1
+#define FAIL_CONTROL_PRIV_SHIFT (1 << 20)
+#define FAIL_CONTROL_PRIV_PRIV 0x0
+#define FAIL_CONTROL_PRIV_UNPRIV 0x1
+
+/*
+ * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
+ * Platform should provide the value on initialisation.
+ */
+#define FAIL_ID_VNET_SHIFT 24
+#define FAIL_ID_VNET_MASK 0xf
+#define FAIL_ID_ID_SHIFT 0
+
+/* Used along with 'tzc_region_attributes_t' below */
+#define REGION_ATTRIBUTES_SEC_SHIFT 30
+#define REGION_ATTRIBUTES_F_EN_SHIFT 0
+#define REGION_ATTRIBUTES_F_EN_MASK 0xf
+
+#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16
+#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0
+#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf
+
+
+/* Macros for setting Region ID access permissions based on NSAID */
+#define TZC_REGION_ACCESS_RD(id) \
+ ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \
+ REGION_ID_ACCESS_NSAID_RD_EN_SHIFT)
+#define TZC_REGION_ACCESS_WR(id) \
+ ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \
+ REGION_ID_ACCESS_NSAID_WR_EN_SHIFT)
+#define TZC_REGION_ACCESS_RDWR(id) \
+ (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id))
+
+/* Filters are bit mapped 0 to 3. */
+#define TZC400_COMPONENT_ID 0xb105f00d
+
+#ifndef __ASSEMBLY__
+
+/*******************************************************************************
+ * Function & variable prototypes
+ ******************************************************************************/
+
+/*
+ * What type of action is expected when an access violation occurs.
+ * The memory requested is zeroed. But we can also raise and event to
+ * let the system know it happened.
+ * We can raise an interrupt(INT) and/or cause an exception(ERR).
+ * TZC_ACTION_NONE - No interrupt, no Exception
+ * TZC_ACTION_ERR - No interrupt, raise exception -> sync external
+ * data abort
+ * TZC_ACTION_INT - Raise interrupt, no exception
+ * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync
+ * external data abort
+ */
+enum tzc_action {
+ TZC_ACTION_NONE = 0,
+ TZC_ACTION_ERR = 1,
+ TZC_ACTION_INT = 2,
+ TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT)
+};
+
+/*
+ * Controls secure access to a region. If not enabled secure access is not
+ * allowed to region.
+ */
+enum tzc_region_attributes {
+ TZC_REGION_S_NONE = 0,
+ TZC_REGION_S_RD = 1,
+ TZC_REGION_S_WR = 2,
+ TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR)
+};
+
+/*
+ * Implementation defined values used to validate inputs later.
+ * Filters : max of 4 ; 0 to 3
+ * Regions : max of 9 ; 0 to 8
+ * Address width : Values between 32 to 64
+ */
+struct tzc_instance {
+ uint64_t base;
+ uint32_t aid_width;
+ uint8_t addr_width;
+ uint8_t num_filters;
+ uint8_t num_regions;
+};
+
+void tzc_init(struct tzc_instance *controller);
+void tzc_configure_region(const struct tzc_instance *controller, uint32_t filters,
+ uint8_t region, uint64_t region_base, uint64_t region_top,
+ enum tzc_region_attributes sec_attr, uint32_t ns_device_access);
+void tzc_enable_filters(const struct tzc_instance *controller);
+void tzc_disable_filters(const struct tzc_instance *controller);
+void tzc_set_action(const struct tzc_instance *controller,
+ enum tzc_action action);
+
+#endif /*__ASSEMBLY__*/
+
+#endif /* __TZC400__ */
diff --git a/include/bakery_lock.h b/include/drivers/console.h
similarity index 71%
copy from include/bakery_lock.h
copy to include/drivers/console.h
index da5d9dd..e285909 100644
--- a/include/bakery_lock.h
+++ b/include/drivers/console.h
@@ -28,26 +28,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BAKERY_LOCK_H__
-#define __BAKERY_LOCK_H__
+#ifndef __CONSOLE_H__
+#define __CONSOLE_H__
-#include <platform.h>
+void console_init(unsigned long base_addr);
+int console_putc(int c);
+int console_getc(void);
-#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
-
-#ifndef __ASSEMBLY__
-typedef struct {
- int owner;
- volatile char entering[BAKERY_LOCK_MAX_CPUS];
- volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
-} bakery_lock;
-
-#define NO_OWNER (-1)
-
-void bakery_lock_init(bakery_lock* bakery);
-void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery);
-void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery);
-int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery);
-#endif /*__ASSEMBLY__*/
+#endif /* __CONSOLE_H__ */
-#endif /* __BAKERY_LOCK_H__ */
diff --git a/include/pm.h b/include/drivers/fvp_pwrc.h
similarity index 60%
rename from include/pm.h
rename to include/drivers/fvp_pwrc.h
index bfdbf67..f600a24 100644
--- a/include/pm.h
+++ b/include/drivers/fvp_pwrc.h
@@ -28,39 +28,50 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __PM_H__
-#define __PM_H__
+#ifndef __FVP_PWRC_H__
+#define __FVP_PWRC_H__
-#ifndef __ASSEMBLY__
+/* FVP Power controller register offset etc */
+#define PPOFFR_OFF 0x0
+#define PPONR_OFF 0x4
+#define PCOFFR_OFF 0x8
+#define PWKUPR_OFF 0xc
+#define PSYSR_OFF 0x10
-/*******************************************************************************
- * Structure populated by platform specific code to export routines which
- * perform common low level pm functions
- ******************************************************************************/
-typedef struct {
- int (*cpu_on)(unsigned long);
- int (*cpu_off)(unsigned long);
- int (*cpu_suspend)(unsigned long);
- int (*affinity_info)(unsigned long, unsigned int);
-} pm_frontend_ops;
+#define PWKUPR_WEN (1ull << 31)
-/*******************************************************************************
- * Structure populated by a generic power management api implementation e.g.
- * psci to perform api specific bits after a cpu has been turned on.
- ******************************************************************************/
-typedef struct {
- unsigned long (*cpu_off_finisher)(unsigned long);
- unsigned long (*cpu_suspend_finisher)(unsigned long);
-} pm_backend_ops;
+#define PSYSR_AFF_L2 (1 << 31)
+#define PSYSR_AFF_L1 (1 << 30)
+#define PSYSR_AFF_L0 (1 << 29)
+#define PSYSR_WEN (1 << 28)
+#define PSYSR_PC (1 << 27)
+#define PSYSR_PP (1 << 26)
+
+#define PSYSR_WK_SHIFT 24
+#define PSYSR_WK_MASK 0x3
+#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK
+
+#define WKUP_COLD 0x0
+#define WKUP_RESET 0x1
+#define WKUP_PPONR 0x2
+#define WKUP_GICREQ 0x3
+
+#define PSYSR_INVALID 0xffffffff
+
+#ifndef __ASSEMBLY__
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
-extern pm_frontend_ops *get_pm_frontend_ops(void);
-extern pm_backend_ops *get_pm_backend_ops(void);
-extern void set_pm_frontend_ops(pm_frontend_ops *);
-extern void set_pm_backend_ops(pm_backend_ops *);
+extern int fvp_pwrc_setup(void);
+extern void fvp_pwrc_write_pcoffr(unsigned long);
+extern void fvp_pwrc_write_ppoffr(unsigned long);
+extern void fvp_pwrc_write_pponr(unsigned long);
+extern void fvp_pwrc_set_wen(unsigned long);
+extern void fvp_pwrc_clr_wen(unsigned long);
+extern unsigned int fvp_pwrc_read_psysr(unsigned long);
+extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long);
#endif /*__ASSEMBLY__*/
-#endif /* __PM_H__ */
+#endif /* __FVP_PWRC_H__ */
diff --git a/include/drivers/io_driver.h b/include/drivers/io_driver.h
new file mode 100644
index 0000000..82dbbf1
--- /dev/null
+++ b/include/drivers/io_driver.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __IO_DRIVER_H__
+#define __IO_DRIVER_H__
+
+#include "platform.h" /* For MAX_IO_DEVICES */
+
+
+/* Generic IO entity structure,representing an accessible IO construct on the
+ * device, such as a file */
+struct io_entity {
+ io_dev_handle dev_handle;
+ uintptr_t info;
+};
+
+
+/* Device info structure, providing device-specific functions and a means of
+ * adding driver-specific state */
+struct io_dev_info {
+ struct io_dev_funcs *funcs;
+ uintptr_t info;
+};
+
+
+/* Structure used to create a connection to a type of device */
+struct io_dev_connector {
+ /* dev_open opens a connection to a particular device driver */
+ int (*dev_open)(void *spec, struct io_dev_info **dev_info);
+};
+
+
+/* Structure to hold device driver function pointers */
+struct io_dev_funcs {
+ io_type (*type)(void);
+ int (*open)(struct io_dev_info *dev_info, const void *spec,
+ struct io_entity *entity);
+ int (*seek)(struct io_entity *entity, int mode, ssize_t offset);
+ int (*size)(struct io_entity *entity, size_t *length);
+ int (*read)(struct io_entity *entity, void *buffer, size_t length,
+ size_t *length_read);
+ int (*write)(struct io_entity *entity, const void *buffer,
+ size_t length, size_t *length_written);
+ int (*close)(struct io_entity *entity);
+ int (*dev_init)(struct io_dev_info *dev_info, const void *init_params);
+ int (*dev_close)(struct io_dev_info *dev_info);
+};
+
+
+/* IO platform data - used to track devices registered for a specific
+ * platform */
+struct io_plat_data {
+ struct io_dev_info *devices[MAX_IO_DEVICES];
+ unsigned int dev_count;
+};
+
+
+/* Operations intended to be performed during platform initialisation */
+
+/* Initialise the IO layer */
+void io_init(struct io_plat_data *data);
+
+/* Register a device driver */
+int io_register_device(struct io_dev_info *dev_info);
+
+#endif /* __IO_DRIVER_H__ */
diff --git a/include/bakery_lock.h b/include/drivers/io_fip.h
similarity index 67%
copy from include/bakery_lock.h
copy to include/drivers/io_fip.h
index da5d9dd..56dd1e0 100644
--- a/include/bakery_lock.h
+++ b/include/drivers/io_fip.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,26 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BAKERY_LOCK_H__
-#define __BAKERY_LOCK_H__
+#ifndef __IO_FIP_H__
+#define __IO_FIP_H__
-#include <platform.h>
-
-#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
-
-#ifndef __ASSEMBLY__
-typedef struct {
- int owner;
- volatile char entering[BAKERY_LOCK_MAX_CPUS];
- volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
-} bakery_lock;
-
-#define NO_OWNER (-1)
-
-void bakery_lock_init(bakery_lock* bakery);
-void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery);
-void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery);
-int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery);
-#endif /*__ASSEMBLY__*/
+int register_io_dev_fip(struct io_dev_connector **dev_con);
-#endif /* __BAKERY_LOCK_H__ */
+#endif /* __IO_FIP_H__ */
diff --git a/include/bakery_lock.h b/include/drivers/io_memmap.h
similarity index 67%
copy from include/bakery_lock.h
copy to include/drivers/io_memmap.h
index da5d9dd..5fa7bc9 100644
--- a/include/bakery_lock.h
+++ b/include/drivers/io_memmap.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,26 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BAKERY_LOCK_H__
-#define __BAKERY_LOCK_H__
+#ifndef __IO_MEMMAP_H__
+#define __IO_MEMMAP_H__
-#include <platform.h>
-
-#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
-
-#ifndef __ASSEMBLY__
-typedef struct {
- int owner;
- volatile char entering[BAKERY_LOCK_MAX_CPUS];
- volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
-} bakery_lock;
-
-#define NO_OWNER (-1)
-
-void bakery_lock_init(bakery_lock* bakery);
-void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery);
-void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery);
-int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery);
-#endif /*__ASSEMBLY__*/
+int register_io_dev_memmap(struct io_dev_connector **dev_con);
-#endif /* __BAKERY_LOCK_H__ */
+#endif /* __IO_MEMMAP_H__ */
diff --git a/include/bakery_lock.h b/include/drivers/io_semihosting.h
similarity index 67%
copy from include/bakery_lock.h
copy to include/drivers/io_semihosting.h
index da5d9dd..7dc632d 100644
--- a/include/bakery_lock.h
+++ b/include/drivers/io_semihosting.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -28,26 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef __BAKERY_LOCK_H__
-#define __BAKERY_LOCK_H__
+#ifndef __IO_SH_H__
+#define __IO_SH_H__
-#include <platform.h>
-
-#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT
-
-#ifndef __ASSEMBLY__
-typedef struct {
- int owner;
- volatile char entering[BAKERY_LOCK_MAX_CPUS];
- volatile unsigned number[BAKERY_LOCK_MAX_CPUS];
-} bakery_lock;
-
-#define NO_OWNER (-1)
-
-void bakery_lock_init(bakery_lock* bakery);
-void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery);
-void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery);
-int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery);
-#endif /*__ASSEMBLY__*/
+int register_io_dev_sh(struct io_dev_connector **dev_con);
-#endif /* __BAKERY_LOCK_H__ */
+#endif /* __IO_SH_H__ */
diff --git a/include/aarch64/arch.h b/include/lib/aarch64/arch.h
similarity index 100%
rename from include/aarch64/arch.h
rename to include/lib/aarch64/arch.h
diff --git a/include/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
similarity index 100%
rename from include/aarch64/arch_helpers.h
rename to include/lib/aarch64/arch_helpers.h
diff --git a/include/aarch64/xlat_tables.h b/include/lib/aarch64/xlat_tables.h
similarity index 100%
rename from include/aarch64/xlat_tables.h
rename to include/lib/aarch64/xlat_tables.h
diff --git a/include/bakery_lock.h b/include/lib/bakery_lock.h
similarity index 88%
rename from include/bakery_lock.h
rename to include/lib/bakery_lock.h
index da5d9dd..6e6e966 100644
--- a/include/bakery_lock.h
+++ b/include/lib/bakery_lock.h
@@ -44,10 +44,10 @@
#define NO_OWNER (-1)
-void bakery_lock_init(bakery_lock* bakery);
-void bakery_lock_get(unsigned long mpidr, bakery_lock* bakery);
-void bakery_lock_release(unsigned long mpidr, bakery_lock* bakery);
-int bakery_lock_try(unsigned long mpidr, bakery_lock* bakery);
+void bakery_lock_init(bakery_lock *bakery);
+void bakery_lock_get(unsigned long mpidr, bakery_lock *bakery);
+void bakery_lock_release(unsigned long mpidr, bakery_lock *bakery);
+int bakery_lock_try(unsigned long mpidr, bakery_lock *bakery);
#endif /*__ASSEMBLY__*/
#endif /* __BAKERY_LOCK_H__ */
diff --git a/include/io_storage.h b/include/lib/io_storage.h
similarity index 100%
rename from include/io_storage.h
rename to include/lib/io_storage.h
diff --git a/include/mmio.h b/include/lib/mmio.h
similarity index 100%
rename from include/mmio.h
rename to include/lib/mmio.h
diff --git a/include/semihosting.h b/include/lib/semihosting.h
similarity index 100%
rename from include/semihosting.h
rename to include/lib/semihosting.h
diff --git a/include/spinlock.h b/include/lib/spinlock.h
similarity index 100%
rename from include/spinlock.h
rename to include/lib/spinlock.h