commit a5d062715cead3cfbf22f3952378455253063882
author Grzegorz Jaszczyk <jaz@semihalf.com> Thu Dec 20 17:13:19 2018 +0100
committer Marcin Wojtas <mw@semihalf.com> Sun Jun 07 00:06:03 2020 +0200
tree 614e1bf401628018f9a16eb6589bcba6b5600e8c
parent 2d3d86ac2d4af8c4ae701321e030c2adf5ae84de

plat: marvell: add support for PLL 2.2GHz mode

Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

include/drivers/marvell/aro.h

diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h
index c16f625..c9dd36e 100644
--- a/include/drivers/marvell/aro.h
+++ b/include/drivers/marvell/aro.h
@@ -21,11 +21,17 @@
 	DDR_FREQ_SAR
 };
 
+#include <mvebu_def.h>
+
 enum cpu_clock_freq_mode {
 	CPU_2000_DDR_1200_RCLK_1200 = 0x0,
 	CPU_2000_DDR_1050_RCLK_1050 = 0x1,
 	CPU_1600_DDR_800_RCLK_800   = 0x4,
+#ifdef MVEBU_SOC_AP807
+	CPU_2200_DDR_1200_RCLK_1200 = 0x6,
+#else
 	CPU_1800_DDR_1200_RCLK_1200 = 0x6,
+#endif
 	CPU_1800_DDR_1050_RCLK_1050 = 0x7,
 	CPU_1600_DDR_900_RCLK_900   = 0x0B,
 	CPU_1600_DDR_1050_RCLK_1050 = 0x0D,