plat: marvell: add support for PLL 2.2GHz mode
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
diff --git a/drivers/marvell/ap807_clocks_init.c b/drivers/marvell/ap807_clocks_init.c
index 04c256b..5604453 100644
--- a/drivers/marvell/ap807_clocks_init.c
+++ b/drivers/marvell/ap807_clocks_init.c
@@ -96,6 +96,11 @@
case CPU_2000_DDR_1200_RCLK_1200:
pll_set_freq(PLL_FREQ_2000);
break;
+#ifdef MVEBU_SOC_AP807
+ case CPU_2200_DDR_1200_RCLK_1200:
+ pll_set_freq(PLL_FREQ_2200);
+ break;
+#endif
default:
break;
}
diff --git a/include/drivers/marvell/aro.h b/include/drivers/marvell/aro.h
index c16f625..c9dd36e 100644
--- a/include/drivers/marvell/aro.h
+++ b/include/drivers/marvell/aro.h
@@ -21,11 +21,17 @@
DDR_FREQ_SAR
};
+#include <mvebu_def.h>
+
enum cpu_clock_freq_mode {
CPU_2000_DDR_1200_RCLK_1200 = 0x0,
CPU_2000_DDR_1050_RCLK_1050 = 0x1,
CPU_1600_DDR_800_RCLK_800 = 0x4,
+#ifdef MVEBU_SOC_AP807
+ CPU_2200_DDR_1200_RCLK_1200 = 0x6,
+#else
CPU_1800_DDR_1200_RCLK_1200 = 0x6,
+#endif
CPU_1800_DDR_1050_RCLK_1050 = 0x7,
CPU_1600_DDR_900_RCLK_900 = 0x0B,
CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c
index 7f9e242..166f18b 100644
--- a/plat/marvell/armada/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c
@@ -89,6 +89,12 @@
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
+#define AVS_CN9130_HIGH_CLK_VALUE ((0x80 << 24) | \
+ (0x2dc << 13) | \
+ (0x2dc << 3) | \
+ (0x1 << AVS_SOFT_RESET_OFFSET) | \
+ (0x1 << AVS_ENABLE_OFFSET))
+
#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
@@ -224,10 +230,19 @@
/* Check which SoC is running and act accordingly */
if (ble_get_ap_type() == CHIP_ID_AP807) {
/* Increase CPU voltage for higher CPU clock */
- if (freq_mode == CPU_2000_DDR_1200_RCLK_1200)
+ switch (freq_mode) {
+ case CPU_2000_DDR_1200_RCLK_1200:
avs_val = AVS_A3900_HIGH_CLK_VALUE;
- else
+ break;
+#ifdef MVEBU_SOC_AP807
+ case CPU_2200_DDR_1200_RCLK_1200:
+ avs_val = AVS_CN9130_HIGH_CLK_VALUE;
+ break;
+#endif
+ default:
avs_val = AVS_A3900_CLK_VALUE;
+ }
+
} else {
/* Check which SoC is running and act accordingly */
device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
@@ -463,7 +478,9 @@
NOTICE("SVC: DEV ID: %s, FREQ Mode: 0x%x\n",
single_cluster == 0 ? "8040" : "8020", freq_pidi_mode);
switch (freq_pidi_mode) {
+#ifndef MVEBU_SOC_AP807
case CPU_1800_DDR_1200_RCLK_1200:
+#endif
case CPU_1800_DDR_1050_RCLK_1050:
if (perr[1])
goto perror;