Fix MISRA C issues in BL1/BL2/BL31
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.
Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c
index 210c358..fec513d 100644
--- a/bl1/aarch64/bl1_context_mgmt.c
+++ b/bl1/aarch64/bl1_context_mgmt.c
@@ -43,7 +43,7 @@
void bl1_prepare_next_image(unsigned int image_id)
{
unsigned int security_state, mode = MODE_EL1;
- image_desc_t *image_desc;
+ image_desc_t *desc;
entry_point_info_t *next_bl_ep;
#if CTX_INCLUDE_AARCH32_REGS
@@ -59,11 +59,11 @@
#endif
/* Get the image descriptor. */
- image_desc = bl1_plat_get_image_desc(image_id);
- assert(image_desc);
+ desc = bl1_plat_get_image_desc(image_id);
+ assert(desc != NULL);
/* Get the entry point info. */
- next_bl_ep = &image_desc->ep_info;
+ next_bl_ep = &desc->ep_info;
/* Get the image security state. */
security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
@@ -77,7 +77,7 @@
mode = MODE_EL2;
}
- next_bl_ep->spsr = SPSR_64(mode, MODE_SP_ELX,
+ next_bl_ep->spsr = (uint32_t)SPSR_64(mode, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
/* Allow platform to make change */
@@ -88,7 +88,7 @@
cm_prepare_el3_exit(security_state);
/* Indicate that image is in execution state. */
- image_desc->state = IMAGE_STATE_EXECUTED;
+ desc->state = IMAGE_STATE_EXECUTED;
print_entry_point_info(next_bl_ep);
}