doc: Update description for AT speculative workaround
Documented the CPU specific build macros created for AT
speculative workaround.
Updated the description of 'ERRATA_SPECULATIVE_AT' errata
workaround option.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie46a80d4e8183c1d5c8b153f08742a04d41a2af2
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 6b6c639..33b5090 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -127,6 +127,9 @@
Earlier revisions of the CPU have other errata which require the same
workaround in software, so they should be covered anyway.
+- ``ERRATA_A53_1530924``: This applies errata 1530924 workaround to all
+ revisions of Cortex-A53 CPU.
+
For Cortex-A55, the following errata build flags are defined :
- ``ERRATA_A55_768277``: This applies errata 768277 workaround to Cortex-A55
@@ -147,6 +150,9 @@
- ``ERRATA_A55_1221012``: This applies errata 1221012 workaround to Cortex-A55
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
+- ``ERRATA_A55_1530923``: This applies errata 1530923 workaround to all
+ revisions of Cortex-A55 CPU.
+
For Cortex-A57, the following errata build flags are defined :
- ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
@@ -182,12 +188,17 @@
- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
+- ``ERRATA_A57_1319537``: This applies errata 1319537 workaround to all
+ revisions of Cortex-A57 CPU.
For Cortex-A72, the following errata build flags are defined :
- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72
CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
+- ``ERRATA_A72_1319367``: This applies errata 1319367 workaround to all
+ revisions of Cortex-A72 CPU.
+
For Cortex-A73, the following errata build flags are defined :
- ``ERRATA_A73_852427``: This applies errata 852427 workaround to Cortex-A73
@@ -233,6 +244,11 @@
- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76
CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
+- ``ERRATA_A76_1165522``: This applies errata 1165522 workaround to all
+ revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
+ limitation of errata framework this errata is applied to all revisions
+ of Cortex-A76 CPU.
+
For Cortex-A77, the following errata build flags are defined :
- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index ae328c7..b4fe404 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -694,28 +694,36 @@
default value of this flag is ``no``. Note this option must be enabled only
for ARM architecture greater than Armv8.5-A.
-- ``ERRATA_SPECULATIVE_AT``: This flag enables/disables page table walk during
- context restore as speculative AT instructions using an out-of-context
- translation regime could cause subsequent requests to generate an incorrect
- translation.
- System registers are not updated during context save, hence this workaround
- need not be applied in the context save path.
+- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT``
+ speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``.
+ The default value of this flag is ``0``.
+
+ ``AT`` speculative errata workaround disables stage1 page table walk for
+ lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point
+ produces either the correct result or failure without TLB allocation.
This boolean option enables errata for all below CPUs.
- +---------+--------------+
- | Errata | CPU |
- +=========+==============+
- | 1165522 | Cortex-A76 |
- +---------+--------------+
- | 1319367 | Cortex-A72 |
- +---------+--------------+
- | 1319537 | Cortex-A57 |
- +---------+--------------+
- | 1530923 | Cortex-A55 |
- +---------+--------------+
- | 1530924 | Cortex-A53 |
- +---------+--------------+
+ +---------+--------------+-------------------------+
+ | Errata | CPU | Workaround Define |
+ +=========+==============+=========================+
+ | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` |
+ +---------+--------------+-------------------------+
+ | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` |
+ +---------+--------------+-------------------------+
+ | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |
+ +---------+--------------+-------------------------+
+ | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` |
+ +---------+--------------+-------------------------+
+ | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` |
+ +---------+--------------+-------------------------+
+
+ .. note::
+ This option is enabled by build only if platform sets any of above defines
+ mentioned in ’Workaround Define' column in the table.
+ If this option is enabled for the EL3 software then EL2 software also must
+ implement this workaround due to the behaviour of the errata mentioned
+ in new SDEN document which will get published soon.
- ``RAS_TRAP_LOWER_EL_ERR_ACCESS``: This flag enables/disables the SCR_EL3.TERR
bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
diff --git a/docs/glossary.rst b/docs/glossary.rst
index e087079..08add3a 100644
--- a/docs/glossary.rst
+++ b/docs/glossary.rst
@@ -18,6 +18,9 @@
API
Application Programming Interface
+ AT
+ Address Translation
+
BTI
Branch Target Identification. An Armv8.5 extension providing additional
control flow integrity around indirect branches and their targets.