Tegra: memctrl: check GPU reset state from common place
This patch moves the GPU reset state check, during VideoMem resize, to the
common SiP handler, to reduce code duplication.
Change-Id: I3818c5f104b809da83dc2a61d6a8149606f81c13
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index 2faefc8..9944e72 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -15,9 +15,6 @@
#include <utils.h>
#include <xlat_tables_v2.h>
-#define TEGRA_GPU_RESET_REG_OFFSET 0x28c
-#define GPU_RESET_BIT (1 << 24)
-
/* Video Memory base and size (live values) */
static uint64_t video_mem_base;
static uint64_t video_mem_size;
@@ -135,21 +132,9 @@
{
uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20);
uintptr_t vmem_end_new = phys_base + size_in_bytes;
- uint32_t regval;
unsigned long long non_overlap_area_size;
/*
- * The GPU is the user of the Video Memory region. In order to
- * transition to the new memory region smoothly, we program the
- * new base/size ONLY if the GPU is in reset mode.
- */
- regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
- if ((regval & GPU_RESET_BIT) == 0) {
- ERROR("GPU not in reset! Video Memory setup failed\n");
- return;
- }
-
- /*
* Setup the Memory controller to restrict CPU accesses to the Video
* Memory region
*/
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 76e21f6..92fdadc 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -19,9 +19,6 @@
#include <utils.h>
#include <xlat_tables_v2.h>
-#define TEGRA_GPU_RESET_REG_OFFSET 0x30
-#define GPU_RESET_BIT (1 << 0)
-
/* Video Memory base and size (live values) */
static uint64_t video_mem_base;
static uint64_t video_mem_size_mb;
@@ -603,21 +600,9 @@
{
uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20);
uintptr_t vmem_end_new = phys_base + size_in_bytes;
- uint32_t regval;
unsigned long long non_overlap_area_size;
/*
- * The GPU is the user of the Video Memory region. In order to
- * transition to the new memory region smoothly, we program the
- * new base/size ONLY if the GPU is in reset mode.
- */
- regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
- if ((regval & GPU_RESET_BIT) == 0U) {
- ERROR("GPU not in reset! Video Memory setup failed\n");
- return;
- }
-
- /*
* Setup the Memory controller to restrict CPU accesses to the Video
* Memory region
*/
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c
index 9b0a36c..dcad21e 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/common/tegra_sip_calls.c
@@ -11,6 +11,7 @@
#include <debug.h>
#include <errno.h>
#include <memctrl.h>
+#include <mmio.h>
#include <runtime_svc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
@@ -57,6 +58,7 @@
void *handle,
uint64_t flags)
{
+ uint32_t regval;
int err;
/* Check if this is a SoC specific SiP */
@@ -87,6 +89,18 @@
SMC_RET1(handle, -ENOTSUP);
}
+ /*
+ * The GPU is the user of the Video Memory region. In order to
+ * transition to the new memory region smoothly, we program the
+ * new base/size ONLY if the GPU is in reset mode.
+ */
+ regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
+ TEGRA_GPU_RESET_REG_OFFSET);
+ if ((regval & GPU_RESET_BIT) == 0U) {
+ ERROR("GPU not in reset! Video Memory setup failed\n");
+ SMC_RET1(handle, -ENOTSUP);
+ }
+
/* new video memory carveout settings */
tegra_memctrl_videomem_setup(x1, x2);
diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
index 8804e8e..ae00fb5 100644
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ b/plat/nvidia/tegra/include/t132/tegra_def.h
@@ -40,6 +40,8 @@
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000)
+#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
+#define GPU_RESET_BIT (U(1) << 24)
/*******************************************************************************
* Tegra Flow Controller constants
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 9308b93..d033147 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -196,6 +196,8 @@
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x05000000)
+#define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
+#define GPU_RESET_BIT (U(1) << 0)
/*******************************************************************************
* Tegra micro-seconds timer constants
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index 2fcf25c..454c666 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -65,6 +65,8 @@
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000)
+#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
+#define GPU_RESET_BIT (U(1) << 24)
/*******************************************************************************
* Tegra Flow Controller constants