fix(st-ddr): fix coverity issue in ddrphyinit
Address issue CID 445362 and CID 445361 found during coverity scan.
Change-Id: I1ab460d2e1353b81517788e32de662f203b0352f
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
diff --git a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c
index 38b8a07..a0712b5 100644
--- a/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c
+++ b/drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c
@@ -71,7 +71,7 @@
uint32_t anib;
uint32_t atxpren; /* Default to 0xf (max). Optimal setting is technology specific */
uint32_t atxprep; /* Default to 0xf (max). Optimal setting is technology specific */
- uint32_t ck_anib_inst[2];
+ uint32_t ck_anib_inst[2] = {0};
atxprep = config->uia.txslewriseac;
atxpren = config->uia.txslewfallac;
@@ -1012,7 +1012,6 @@
} else if (anib == 7U) {
aforcetricont = 0xFU;
}
-#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
/*
* If all the lanes can be disabled, and Anib is not the first or last disable
@@ -1022,6 +1021,8 @@
(anib != (config->uib.numanib - 1U))) {
acx4anibdis = acx4anibdis | (0x1U << anib);
}
+#endif /* STM32MP_DDR3_TYPE || STM32MP_DDR4_TYPE */
+
mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * (TANIB | c_addr |
CSR_AFORCETRICONT_ADDR))),
aforcetricont);